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  • Mobile Intel® Pentium® 4 Processor-M and Intel® 845MP/845MZ Chipset Platform Design Guide

    April 2002

    Order Number: 250688-002

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  • Mobile Intel® Pentium® 4 Processor-M and Intel® 845MP/845MZ Chipset Platform

    2 Design Guide

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    Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications.

    Actual system-level properties, such as skin temperature, are a function of various factors, including component placement, component power characteristics, system power and thermal management techniques, software application usage and general system design. Intel is not responsible for its customers’ system designs, nor is Intel responsible for ensuring that its customers’ products comply with all applicable laws and regulations. Intel provides this and other thermal design information for informational purposes only. System design is the sole responsibility of Intel’s customers, and Intel’s customers should not rely on any Intel-provided information as either an endorsement or recommendation of any particular system design characteristics.

    Intel may make changes to specifications and product descriptions at any time, without notice.

    Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

    The Intel® 845MP/845MZ chipset MCH-M may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.

    Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

    I2C is a 2-wire communications bus/protocol developed by Philips. SMBus is a subset of the I2C bus/protocol and was developed by Intel. Implementations of the I2C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips Corporation.

    Alert on LAN is a result of the Intel-IBM Advanced Manageability Alliance and a trademark of IBM.

    Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from:

    Intel Corporation

    www.intel.com

    or call 1-800-548-4725

    Intel®, Pentium®, NetBurst , and SpeedStep™ technology is a registered trademark or trademark of Intel Corporation and its subsidiaries in the United States and other countries.

    *Other brands and names may be claimed as the property of others.

    Copyright © Intel Corporation 2002

  • Mobile Intel® Pentium® 4 Processor-M and Intel® 845MP/845MZ Chipset Platform

    Design Guide 3

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    Contents 1. Introduction ................................................................................................................................ 14

    1.1. Related Documentation................................................................................................. 15 1.2. Conventions and Terminology....................................................................................... 16 1.3. Mobile Intel® Pentium® 4 Processor-M in 478- Pin Package......................................... 18 1.4. Intel 845MP/845MZ Chipset .......................................................................................... 19

    1.4.1. Intel Memory Controller Hub (MCH-M)........................................................ 20 1.4.1.1. Processor System Bus Support...................................................... 21 1.4.1.2. Integrated System Memory DRAM Controller ................................ 21

    1.4.1.2.1. Accelerated Graphics Port (AGP) Interface ................. 21 1.4.1.3. Packaging/Power............................................................................ 22 1.4.1.4. I/O Controller Hub (ICH3-M)........................................................... 22

    1.4.1.4.1. Packaging/Power.......................................................... 22 1.4.1.5. Firmware Hub (FWH) ..................................................................... 22

    1.4.1.5.1. Packaging/Power.......................................................... 22 1.4.2. Bandwidth Summary ................................................................................... 22

    2. General Design Considerations ................................................................................................. 24 2.1. Nominal Board Stackup................................................................................................. 24

    3. Processor System Bus Design Guidelines ................................................................................ 25 3.1. Introduction.................................................................................................................... 25 3.2. Processor System Bus (PSB) Routing Guidelines ........................................................ 26

    3.2.1. Return Path Evaluation ............................................................................... 27 3.2.2. GTLREF Layout and Routing Recommendations....................................... 28

    3.3. Processor Configuration................................................................................................ 28 3.3.1. Mobile Intel Pentium 4 Processor-M in the 478 -Pin Package Configuration ............................................................................................... 28

    3.4. General Topology and Layout Guidelines ..................................................................... 29 3.4.1. Design Recommendations .......................................................................... 29 3.4.2. Source Synchronous (SS) Signals .............................................................. 30 3.4.3. Common Clock (CC) AGTL+ Signals.......................................................... 32

    3.4.3.1. CC Topology with ODT................................................................... 32 3.4.4. Asynchronous AGTL+ Signals .................................................................... 34

    3.4.4.1. CPU THRMTRIP# Circuit Recommendation.................................. 35 3.4.4.1.1. Topology #1: Asynchronous AGTL+ Signals Driven by

    the Processor; FERR#, IERR#, PROCHOT# and THRMTRIP#................................................................. 36

    3.4.4.1.2. Topology #2, #2A: Asynchronous AGTL+ Signals Driven by ICH3-M..................................................................... 36

    3.4.4.1.3. Topology #2B: Asynchronous AGTL+ Signals Driven by ICH3-M to Both CPU and FWH; INIT#......................... 37

    3.4.4.2. Voltage Translator Circuit ............................................................... 38 3.5. ITP Debug Port.............................................................................................................. 38

    3.5.1.1. Logic Analyzer Interface (LAI) ........................................................ 38 3.5.1.1.1. Mechanical Considerations .......................................... 38 3.5.1.1.2. Electrical Considerations .............................................. 39

    4. Processor Power Requirements ................................................................................................ 40 4.1. General Description....................................................................................................... 40 4.2. Power Delivery Architectural Block Diagram................................................................. 41

  • Mobile Intel® Pentium® 4 Processor-M and Intel® 845MP/845MZ Chipset Platform

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    4.3. Processor Phase Lock Loop Design Guidelines............................................................41 4.3.1. Filter Specifications for VCCA, VCCIOPLL, and VSSA ...............................41

    4.4. Voltage and Current.......................................................................................................44 4.4.1. Voltage Identification....................................................................................44 4.4.2. VCC Power Sequencing ................................................................................44

    4.4.2.1. Core Converter Soft Start Timer .....................................................44 4.4.2.2. Power On/Off Sequencing ..............................................................44

    4.5. Voltage Regulator Design Recommendations...............................................................45 4.6. Processor Decoupling Recommendation ......................................................................45

    4.6.1. Transient Response.....................................................................................46 4.6.2. Processor Voltage Pl

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