Click here to load reader

Microarchitecture. Outline Architecture vs. Microarchitecture Components MIPS Datapath 1

  • View

  • Download

Embed Size (px)

Text of Microarchitecture. Outline Architecture vs. Microarchitecture Components MIPS Datapath 1

Slide 0


OutlineArchitecture vs. Microarchitecture ComponentsMIPS Datapath1

Architecture vs. MicroarchitectureArchitectureWhat the CPU does

MicroarchitectureHow the CPU does it2

ArchitectureWhat the CPU does

CPU is a black boxOnly care about what goes in / comes out

Only need to know what instructions the CPU can executeInstruction set architecture (ISA)

Realm of computer scientistsDont really care how it works under the hood3MicroarchitectureHow the CPU does it

Electrical mechanisms that allow CPU to execute instructionsControl paths, adder(s), multiplexors, memory units, etc.

Many possible microarchitectures for single architecture

Domain of computer and electrical engineers

4Architecture vs. MicroarchitectureAnalogy: factory that produces auto parts5

Architecture vs. MicroarchitectureArchitecture: dont care about how factory runs, as long as the parts are good6

Architecture vs. MicroarchitectureMicroarchitecture: care about how the factory runs 7

efficiency, safety, power, 7Architecture vs. MicroarchitectureMicroarchitecture: care about how the factory runs 8

efficiency, safety, power, 8Architecture vs. Microarchitecture9

Intel Pentium IV

AMD Bobcatx86 ArchitectureOutlineArchitecture vs. Microarchitecture ComponentsMIPS Datapath10

Von Neumann Model (basic structure of computer)11MEMORYINPUT




PROCESSING UNITCONTROL UNITPCIRMARMDRTEMPALUComponents: Memory2k m array of stored bitsE.g., 24 8AddressUnique (k-bit) identifier of locationContentsm-bit value stored in location

Basic operationsSTORE: write a value to memory locationLOAD: read a value from memory location13MEMORYMARMDR0000000100100110 111100111101111011110001 0110Result of LOAD 0010?14Components: MemoryMEMORYMARMDR0000000100100110 111100111101111011110001 0110Result of LOAD 0010? 0110 111115Components: Memory0000000100100110 111100111101111011110001 0110MEMORYMARMDRComponents: Memory

How to read data to/from memory?MAR: Memory Address RegisterMDR: Memory Data Register

LOAD data from memory (address A)Write the address (A) into MARSend a read signal to memory unit(memory unit will go get bytes, put into MDR)Read the data from MDR

16MEMORYMARMDRComponents: Memory

How to read data to/from memory?MAR: Memory Address RegisterMDR: Memory Data Register

STORE data X in memory BWrite the data (X) into MDRWrite the address (B) into MARSend a write signal to memory(memory unit will do its thing to write X in location B)

17MEMORYMARMDRComponents: Memory

What is controlling Memory?The CONTROL UNIT of course!!

CONTROL UNIT sends signals Instructs the other components

How does it know what signals (instructions) to send?18MEMORYCONTROL UNITPCIRMARMDRComponents19MEMORYPROCESSING UNITCONTROL UNITPCIRMARMDRTEMPALUCONTROL UNITComponents: Control UnitHow does CONTROL UNIT know what to do?Well, it doesnt know..

Control Unit follows command in the Instruction Register (IR)

Program Counter (PC) register holds memory address of the current instruction

What types of instructions do you think are available?LOAD? STORE? ADD? SUBTRACT? OTHERS?20PCIRCONTROL UNITComponents: Control UnitControl Unit decodes instruction stored in IR

Sends signals to components based on decoded instruction

For example, perhaps the following instruction is in the IR21PCIR00011001CONTROL UNITComponents: Control UnitIn this simplified example, the instruction is decoded as:22PCIR00011001first two bits:00 means LOADnext four bits:memory address to read from (0110)last two bits:01 refer to MDRCONTROL UNITComponents: Control UnitBased on this instruction, the Control Unit will activate the corresponding circuitry to signal the memory unit to get dataThis circuitry goes beyond the scope of this courseConsists of finite state machines of multiplexors, system clock, bus etc.23PCIR00011001first two bits:00 means LOADnext four bits:memory address to read from (0110)last two bits:01 refer to MDRCONTROL UNITComponents: Control UnitIf the instruction in the IR contains logic or arithmetic, the Processing Unit gets involved24PCIRComponents25MEMORYPROCESSING UNITCONTROL UNITPCIRMARMDRTEMPALUComponents: Processing UnitContains ALUArithmetic Logic Unit

Also contains temporary registers (TEMP)Used for arithmetic operandsUsed to store intermediate results of arithmetic operations

May also contain other functional unitsSpecial purpose arithmetic: e.g., multiply, divide, etc.26PROCESSING UNITTEMPALUComponents: Processing UnitHow does Processing Unit know what to do?

Again, Control Unit sends electric signals that correspond to the appropriate instruction (e.g., ADD, SUBTRACT)

27PROCESSING UNITTEMPALUCONTROL UNITPCIRComponents: Processing UnitProcessing Unit gets data from Memory UnitProcessing Unit puts data into Memory Unit28MEMORYPROCESSING UNITMARMDRTEMPALUComponents: Processing Unit ALUALU has its own inputs and outputA is m-bit binary (input)B is m-bit binary (input)control tells ALU what to do (input)E.g., add, subtract, divide, etc.Usually control pins (high / low)C is m-bit result (output)29PROCESSING UNITTEMPALUcontrolABCBreak Time!!30

... wish I was there!!!OutlineArchitecture vs. Microarchitecture ComponentsMIPS Datapath31

MIPS DatapathMIPSMicroprocessor without Interlocked Pipeline StagesRISC Architecture: Reduced Instruction Set Computer

Microarchitecture of single-cycle MIPS processor32

MIPS Single-Cycle MicroarchitectureWe are going to build a single-cycle MIPS CPU33MIPS Single-Cycle MicroarchitectureSystem clockAn oscillator that produces a square waveE.g., 2.4 GHz processor- means 2.4 billion square waves per secondComponents of CPU (memory, ALU, bus, etc.) synchronized to clockActions occur on rising or falling edge34

MIPS Single-Cycle MicroarchitectureSingle-cycle CPU: Executes an entire instruction in one clock cycleClock cycle time limited by slowest instruction


one cycleMIPS Single-Cycle MicroarchitectureOverview of components used in diagram36

MIPS Single-Cycle MicroarchitecturePC: Program Counter32-bit registerInput (PC): next instructionOutput (PC): current instructionCLK: system clock37

MIPS Single-Cycle MicroarchitectureInstruction MemorySingle read portInput: 32-bit instruction address (A)Output: 32-bit data (i.e., instruction) (RD)

Note: this is an oversimplification that assumes the instruction memory is ROM (read only memory)In reality, the instruction memory is writable; the OS can load new programs into memory38

MIPS Single-Cycle MicroarchitectureRegister File (32 registers, 32-bits each)Inputs:A1: 5-bit address specifying a register (to read)A2: 5-bit address specifying a register (to read)A3: 5-bit address specifying a register (to write)WD3: 32-bit data to write to registerCLK: system clockWE3: write enable (single bit)

Outputs:RD1: 32-bit register value specified by 5-bit address A1RD2: 32-bit register value specified by 5-bit address A239

MIPS Single-Cycle MicroarchitectureData MemoryIf WE (Write Enable) is 1, Writes data WD into address A on rising edge of clock (CLK)

If WE is 0,Reads address A onto RD on rising edge of clock (CLK)40

MIPS Single-Cycle MicroarchitectureStart by building the datapathFirst step, connect PC to Instruction MemoryPC register contains address of instructionInstruction Memory fetches instruction (instr) from memory


PCinstrMIPS Single-Cycle Microarchitecture42

MIPS Single-Cycle MicroarchitectureNext step, things start to get more complicatedThe instruction (instr) gets decoded by the control unitThe appropriates pins (e.g., write enable) get setThe 5-bit register addresses (in the Register File) get specified

(Things get set up for execution)43MIPS Single-Cycle Microarchitecture44

MIPS Single-Cycle MicroarchitectureNext, execution occurs (based on instruction)


MIPS Single-Cycle MicroarchitectureThen, the result of execution interacts with memory (somehow)46

MIPS Single-Cycle MicroarchitectureThe process then starts over47

MIPS Single-Cycle MicroarchitectureLets look at the datapath for a concrete exampleMIPS assembly instruction lw (stands for Load Word)lw loads 32-bits of data from a memory address to a register

Please keep in mind that we will NOT use MIPS assembly, we will use x86This is for demonstration purposes only, x86 datapath is more complex 48MIPS Single-Cycle Microarchitecture: lw exampleStep 1: fetch the instruction49

MIPS Single-Cycle Microarchitecture: lw exampleStep 2: decode the instructionIn this case, read source operands from register fileSource operands come from the instruction itselfSays what registers to get information from50

MIPS Single-Cycle Microarchitecture: lw exampleStep 3: sign-extend the immediate result (decode)This has to do with the offset of the memory addressThis is a mechanism to make the offset 32-bits long Dont worry about this..51

MIPS Single-Cycle Microarchitecture: lw exampleStep 4: Compute the memory address (execute)ALUControl2:0 is from the control unit, tells ALU to addSrcA is baseSrcB is offset52

MIPS Single-Cycle Microarchitecture: lw exampleStep 5: Read data from memory, write back to Register FileRegWrite is command from Control Unit20:16 is part of instruction: 5-bit register address to load word53

MIPS Single-Cycle Microarchitecture: lw exampleStep 6: Increment the Program Counter (PC)PC will point to next instruction32-bit instruction width = 4 bytes (hence PC + 4)54

MIPS Single-Cycle