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MIPS CPU:
Simple Datapath
CptS 260Introduction to Computer Architecture
Week 3.1Mon 2014/06/23
Reading Assignment
• [P&H12] Chapter 4 The Processor– §4.1 Introduction– §4.2 Logic Design Conventions– §4.3 Building a Datapath– §4.4 A Simple Implementation Scheme ProcessorSim
MIPS Assembly:Instruction Bitfields and Instruction Types
• R-type arithmetic-logical add, sub, srl, sll“3-register” and, or, xor
• I-type arithmetic-logical addi, ori, …“immediate” branch beq, bne, …
load / store lw/lh/lb, sw/sh/sb
• J-type jump j, jal, jalr
bits
type 6 5 5 5 5 6
R-type op rs rt rd shamt funct
I-type op rs rt 16-bit immediate
J-type op 26-bit address
6 5 5 5 5 6
R op rs rt rd shamt funct
I op rs rt 16-bit immediate
J op 26-bit address
How to Read a MIPS CPU DiagramElectrical Engineering / Computer Engineering
How to Read a MIPS CPU DiagramElectrical Engineering / Computer Engineering
black dot =electricaljunction
no dot =electrically
disconnected
How to Read a MIPS CPU DiagramElectrical Engineering / Computer Engineering
black =data line(5-32 bits)
black =address
line(32 bits)
which bitsin [31–0]
blue =control line
(1 bit)
ALUop(2 bits)
How to Read a MIPS CPU DiagramElectrical Engineering / Computer Engineering
box bordersare not
electrical wires
Instruction Types Imply the Datapath
6 5 5 5 5 6
R op rs rt rd shamt funct
I (arith) op rs rt 16-bit immediate
I (ld/st) op rs rt 16-bit immediate
I (branch) op rs rt 16-bit immediate
J op 26-bit address
Simple Datapath : Program Counter $pc
6 5 5 5 5 6
R op rs rt rd shamt funct
I op rs rt 16-bit immediate
J op 26-bit address
• Default action:$pc += 4 (bytes)
• Instruction memory “separate from”data memory
MIPS Memory Layout
Registers
MemorySegments
(layout)
directives
Memory
.data
$pc
$ra
$t0 – $t9
$s0 – $s7user
Bit storage
instructions
address
0x0040 0000
0x1001 0000
0x8000 0180
0xFFFF 0000
.text
value
.data
.text
.kernel
0x7FFF EFFC stacklocals $sp
…
MIPS Segments and Directives
0x0040 0000
0x1001 0000
.data
.text
.dataA: .word 0B: .byte ‘b’
.textnop…
.dataQ: .word 0
.textsw $sp, Q # save……
.data…
.text……
In your .asm :• Interleave freely
In the .exe:• Compiler
rearranges (automatically)
• “Next available address”
• Contiguous(with alignment)
your.asm
MIPS Segments and Memory
6 5 5 5 5 6
R op rs rt rd shamt funct
I op rs rt 16-bit immediate
J op 26-bit address
.data
.text
.kernel
stack
Program Counter $pc (Is a Pointer!)
$pc
if (t1 == t2)++t2;
else--t1;
nop;
bne $t1, $t2, Elseaddi $t2, $t2, 1j Eh
Else:addi $t1, $t1, –1
Eh:nop
bne0000
0x0040:
addi0004
j0008
000c
0x0040 0010
$t1 $t2 +0xc (bytes)
$t2$t2 0x0001
addi $t1$t1 0xffff
0010 nop
0x0040 0008
32 bits
• Changing $pc is � a jump! (goto)• And vice versa
.text
Munging $pc: Jump and Branch
bne0000
addi0004
j0008
000c
0x0040 0010
$t1 $t2 +0xc (bytes)
$t2$t2 0x0001
addi $t1$t1 0xffff
0010 nop
• default $pc += 4 bytes• jump $pc = 26-bit address
• branch $pc += 16-bit offset .text
R-type: 3 registers
6 5 5 5 5 6
R op rs rt rd shamt funct
I op rs rt 16-bit immediate
J op 26-bit address
• 2 ALU operands• 1 dest. register
• funct field determines ALU operation
1000
001
control line must be ‘1’to set multiplexor
rsrt
rd
funct
I-type: Arithmetic
• addi rt, rs, imm
6 5 5 5 5 6
R op rs rt rd shamt funct
I op rs rt 16-bit immediate
J op 26-bit address
(shown in class!)
I-type: Load/Store
lw $ rt , imm ($rs)• rt �Write register• MemRead• MemToReg, RegWrite
sw $ rt , imm ($rs)• rt � Read register 2• Read data 2 � DM• MemWrite
6 5 5 5 5 6
R op rs rt rd shamt funct
I op rs rt 16-bit immediate
J op 26-bit address
00
1/01/0
0/11
1/0
rsrt
large dots are electrical junctions
(choice points)
16-bit offset(2nd operand)
no dot meansdisconnected
lwsw
I-type: Branch
beq rs, rt, LABEL• same for b, ble/bge,
blt/bgt, beqz/bnez, etc.
• LABEL is 16-bit offset relative to ($pc + 4)� branch limited to16-bit range
6 5 5 5 5 6
R op rs rt rd shamt funct
I op rs rt 16-bit immediate
J op 26-bit address
0100
000
rsrt
16-bit LABEL
( )
( )
Simple Implementation Scheme:ALU Control
• [P&H14]§4.4 A Simple Implementation Scheme
6 5 5 5 5 6
R op rs rt rd shamt funct
I op rs rt 16-bit immediate
J op 26-bit address
ALUcontrol Function
0000 AND
0001 OR
0010 add
0110 subtract
0111 set on less than
1100 NOR
else “not in book”
6 5 5 5 5 6
R op rs rt rd shamt funct
I op rs rt 16-bit immediate
J op 26-bit address
Simple Implementation Scheme:Main Control
op ALUop funct ALU ALU ctrl
R add 10 100000 + 0010
R (arith.) 10 (A-54) … (p.259)
I (arith.) ? … (p.259)
I load 00 + 0010
I store 00 + 0010
I branch 01 – 0110
J jump p.270–271 Fig. 4.24funct
op
