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LOW-POWER ADCS FOR MASSIVE MIMO SYSTEMSJAN CRANINCKX

MASSIVE HARDWARE NEEDS FOR MASSIVE MIMO

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High data rates and

many users enabled by a

massive amount of

antennas

Some extra hardware

needed...

ENERGY-EFFICIENT WIRELESS ADCS

Performance requirements

>10 ENOB

100’s MS/s

Low power consumption (mW)

Architecture choice

SAR: successive approximation

N comparisons needed for an N-bit ADC

Nanoscale CMOS offers enough speed to reach required sampling rates

3

OUTLINE

ADC Architecture

Channel implementation

Calibration methods

Implementations and measurements

Conclusions

Slide 4

START FROM SAR ADC FOR EFFICIENCY

Slide 5

clk

...in+

in-

clk

...

SAR

controller

PIPELINE FOR SPEED

Slide 6

Aresidue

digital output

Coarse SAR Fine SAR

digital output

input input

INTERLEAVE FOR MORE SPEED

Slide 7

Aresidue

output

Coarse SAR Fine SAR

output

input input

MUX

input

output

Channel 1

Channel 2

ADC CHANNEL (1):

6 cycle binary scaled SAR

1b redundancy in backend

robust to comparator errors

Slide 7

COARSE SAR SAMPLES AND GENERATES RESIDUE

Aresidue

digital output

Coarse SAR Fine SAR

digital output

input input

SINGLE-ENDED DAC SWITCHING SCHEME

Slide 8

FOR LOW ENERGY, GOOD SPEED

...

...

clk

in+

clk

in-

10

01

0

10

01

01

SAR

controller

1

CM

V

t

Modified from [Van der Plas ISSCC 2008] and [Liu VLSI 2009]

DAC LINEARITY IS CRITICAL

Total capacitance = 3.5 pF

Approx. 13b noise

Calibration for 3 MSBs

Programmable capacitance

Digital coefficients binary scaled

LSBs sufficiently matched

Slide 9

...

...

clk

in+

clk

in-

10

01

0

10

01

01

SAR

controller

1

CONTROLLER REPLACED BY COMPARATORS + DELAYS

Each comparator activated at specific

common-mode

Calibrate offset at this common-mode

Reduces power consumption

Slide 10

clk

...

...in+

in-

10

01

01

clk

...10

01

01

[Van der Plas ISSCC 2008]

ADC CHANNEL (2):

Amplify and sample residue

Small output swing relaxed linearity

Uncertain gain match coarse SAR LSB to fine SAR MSB in calibration

Fast amplification with low noise at low power

Slide 12

DYNAMIC RESIDUE AMPLIFICATION

Aresidue

digital output

Coarse SAR Fine SAR

digital output

input input

DYNAMIC AMPLIFIER = INTEGRATION DURING CERTAIN TIME

Slide 13

C

tint

vout = gmtintvin

C

gmvin vn,out = 2kTggmtint

C

2

2

vn,in = 2kTg

gmtint

2

E = Vdd.ID.tint

Low noise requires high gm

or long integration time

INVERTER IS GOOD TRANSCONDUCTOR

PMOS and NMOS contribute gm

Shared bias current efficiency

Slide 14

VDD

in out

DIFFERENTIALLY, COMMON MODE FEEDBACK, START/END

INTEGRATION

Slide 15

VDD

in+ in-

out+ out-

clkA

clkR

clkA

clkA

clkA

ADC CHANNEL (3):

8 cycle binary SAR w/ intermediate noise

400 mV r.m.s.

2 cycle binary SAR w/ low noise

200 mV r.m.s.

1b redundancy between

Similar implementation to coarse SAR

Slide 16

FINE SAR QUANTIZES RESIDUE

Aresidue

digital output

Coarse SAR Fine SAR

digital output

input input

Aresidue

dig. out

Fine SARinput input

Clock

GenerationAddition

and MUX

Aresidue

dig. outCoarse SAR Fine SAR

input input

ADC

inputADC

outputclock

dig. out

dig. out

Coarse SAR

POWER EFFICIENCY ENABLED BY CALIBRATION

Calibration corrects

DAC mismatch

Comparator thresholds: 6 coarse stage, 7 fine stage

Residue amplifier gain

Channel gain

Slide 17

COMPARATOR OFFSET CALIBRATION

Short ADC input

Use DAC to generate correct

common-mode

Change comparator thresholds to

average Dout = 0.5

In second stage: Also cancels amplifier

offset

Sensitive to PVT

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OFF-LINE

VDD

clka

clkb

Cs

...

...10

10

10

VDD

clka

clkb

Cs

...10

10

VCM,in

10

Dout

INTER-STAGE GAIN CALIBRATION

Short ADC input

Use coarse DAC to generate +0.5/-0.5 coarse LSB amplifier input

Change gain to obtain Dout1-Dout2 = 1 fine MSB

Sensitive to PVT

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OFF-LINE

Aresidue

digital output

Coarse SAR Fine SAR

digital output

input input+0.5 LSB

Dout1-0.5 LSB

Dout2

0

MSB CAPACITANCE CALIBRATION

Short ADC input

MSB comparator noise 2 residue values

Use second stage to measure MSB – S(LSBs)

Change MSB size to obtain Dout1-Dout2 = 1 fine MSB

Insensitive to PVT

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OFF-LINE

Aresidue

digital output

Coarse SAR Fine SAR

digital output

input inputDout1

Dout2

0MSB-SLSBs

2

SLSBs-MSB2

DMSB

OUTLINE

ADC Architecture

Channel implementation

Calibration methods

Implementations and measurements

Conclusions

Slide 21

1.7mW 11b 250MS/s in 40nm

22

10 100

8

8.5

9

9.5

10

Fclk [MHz]

ENOB [-]

ENOB @ 11 MHz

ENOB @ Nyquist frequency

390 x 170µm2

CH1 CH2

2.1mW 11b 410MS/s in 28nm

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WITH BACKGROUND ON-CHIP CALIBRATION ENGINE

310 mm

35

0 m

m

0 2 4 6 8 10

x 105

50

52

54

56

58

60

62

FFT start index [-]

SNDR in 16384 point FFT[dB]

divider ratio=1

divider ratio=1/2

divider ratio=1/4

divider ratio=1/8

2.3mW 14b 200 MS/s in 28nm

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CH1 CH20 5000 10000 15000

-1

0

1

2

code

DNL [LSB] CH1

0 5000 10000 15000-1

0

1

2

code

DNL [LSB] CH2

0 5000 10000 15000

-2

0

2

code

INL [LSB]

0 5000 10000 15000

-2

0

2

code

INL [LSB]

CONCLUSIONS

SAR architecture and its improvements enable power-efficient data conversion for

wireless systems

Dynamic and asynchronous controller

Pipelined

Time-interleaved

Nanoscale digital CMOS for SoC integration

1 to 2mW power consumption

Negligible in the overall system power

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REFERENCES

B. Verbruggen, M. Iriguchi and J. Craninckx, "A 1.7mW 11b 250MS/s 2× interleaved fully dynamic pipelined SAR ADC in 40nm digital CMOS," 2012 IEEE International Solid-State Circuits Conference, San Francisco, CA, 2012, pp. 466-468.

B. Verbruggen, M. Iriguchi and J. Craninckx, "A 1.7 mW 11b 250 MS/s 2-Times Interleaved Fully Dynamic Pipelined SAR ADC in 40 nm Digital CMOS," in IEEE Journal of Solid-State Circuits, vol. 47, no. 12, pp. 2880-2887, Dec. 2012.

B. Verbruggen et al., "A 2.1 mW 11b 410 MS/s dynamic pipelined SAR ADC with background calibration in 28nm digital CMOS," 2013 Symposium on VLSI Circuits, Kyoto, 2013, pp. C268-C269.

B. Verbruggen, K. Deguchi, B. Malki and J. Craninckx, "A 70 dB SNDR 200 MS/s 2.3 mW dynamic pipelined SAR ADC in 28nm digital CMOS," 2014 Symposium on VLSI Circuits Digest of Technical Papers, Honolulu, HI, 2014, pp. 1-2.

B. Malki, B. Verbruggen, P. Wambacq, K. Deguchi, M. Iriguchi and J. Craninckx, "A complementary dynamic residue amplifier for a 67 dB SNDR 1.36 mW 170 MS/s pipelined SAR ADC," European Solid State Circuits Conference (ESSCIRC), ESSCIRC 2014 - 40th, Venice Lido, 2014, pp. 215-218.

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