© Copyright 2014 Xilinx .

Linux PL330 Mainline

Driver Usage

John Linn 10/17/2014 Based on Linux kernel 3.14

© Copyright 2014 Xilinx .

About the PL330 Hardware

The Zynq Technical Reference Manual (TRM) provides a good

description of the device

There are some known restrictions when using the device which are

documented in section 9.5 of the Zynq TRM

It is a complex device which uses microcode to perform the DMA

transactions

ARM does not license the microcode assembler to end customers

There is no debug/trace capability for the microcode

Memory to memory transfers which are shorter can likely be done

with the CPU easier if the CPU is available

See the references at the end for a complete list of documents

© Copyright 2014 Xilinx .

PL330 Linux Device Drivers

Xilinx Linux Device Driver

– There was a device driver in the Xilinx kernel tree (not mainline) which

provided some simple prebuilt transactions and did not plug into the Linux DMA

Engine

– It was removed from the Xilinx tree in the past year

Mainline (kernel.org) Linux Device Driver

– This driver is the subject of this presentation, it was written by Samsung

– It plugs into the Linux DMA Engine framework such that an application that is

used AXI DMA can work with it easily

– There is a test in the kernel that can be enabled

– It provides basic functionality and could be useful to customers with some

limitations

– There are several threads on the Xilinx Embedded Linux forum where others

have done the work described in this document (and further)

© Copyright 2014 Xilinx .

Mainline PL330 Device Driver Details

The driver generates microcode for memory to memory, memory to

peripheral, and peripheral to memory on the fly

The microcode for the peripheral transfers expect the peripherals to

use peripheral handshaking with the CPU

– It will not work without that handshaking as it locks up waiting for it

The driver uses a burst length of 1 for peripheral transfers which is

not efficient

The driver assumes a FIFO as a peripheral as keyhole addressing is

used in the microcode (no address increments)

– The driver microcode for memory to memory does address incrementing

© Copyright 2014 Xilinx .

Linux Kernel Configuration

This kernel

configuration

builds the PL330

driver and the test

into the kernel

They also work as

kernel modules

There should be

messages about

the PL330 during

kernel boot

showing the driver

(not the test) is up

and running

© Copyright 2014 Xilinx .

In Kernel Test

In the kernel drivers directory, drivers/dma, there is a test source file,

dmatest.c, that can be built in the kernel

It does memory copies for a basic test, but is useful for a sanity

check

Starting the test from user space (assuming built into the kernel)

– echo 1 > /sys/module/dmatest/parameters/run

– There are other parameters that can be changed easily

• timeout, channel, iterations, verbose

The test runs on all 8 channels by default

The test prints out the results so it’s obvious to the user

The interrupts are shown in /proc/interrupts

– Note that the 1st DMA interrupt (45) is for abort and will not be changing

normally

Note this test cannot be in the kernel when using the test described

later, pl330test.c, in this document

© Copyright 2014 Xilinx .

Patching the PL330 Device Driver

The driver is located in drivers/dma directory of the Linux kernel

A patch file, pl330.c.patch, is provided with a PL330 test kernel

module

Patch the driver to not do peripheral handshaking in the microcode

used for peripheral transfers

– A two line change in _bursts()

– Change the microcode which is generated

– Change the _ldst_devtomem() and _ldst_memtodev() function calls to be

_ldst_memtomem()

Patch the driver to allow the burst length to be specified by the user

– A one line change in pl330_prep_slave_sg()

– It is fixed at a burst length of 1

– Change the following line:

from: desc->rqcfg.brst_len = 1;

to: desc->rqcfg.brst_len = pch->burst_len;

© Copyright 2014 Xilinx .

Test System Hardware Details

An AXI FIFO was connected to the GP0 master port of the PS to allow

the PL330 to read and write to the FIFO

– The FIFO does not support peripheral handshaking and there is no Xilinx IP

that does

This system does have limitations as the FIFO is only 16 Kbytes

– Long transfers (> 16KB) cannot verify the data read from the FIFO matches

data written to the FIFO

Two channels of the PL330 are used in the software system to

simulate a typical customer application

– The transmit channel writes into the FIFO

– The receive channel reads from the FIFO

© Copyright 2014 Xilinx .

Test System Software Details

A kernel driver, pl330test.c, was implemented to use the PL330 kernel

driver thru the Linux DMA Engine framework

– This driver is intended for testing and prototyping

– It is also intended to allow customers to determine if the PL330 is a solution for

their project

Long transfers are only enabled in the test system to allow some

performance data to be observed

The software supports the following functionality which can be

controlled via module parameters:

– DMA transfer length

– full duplex operation (transmit and receive simultaneously)

– burst length

There a number of restrictions in how the software works due to the

limitations of the hardware system (documented in the code)

© Copyright 2014 Xilinx .

PL330 Device Tree Bindings

ps7_dma_s: ps7-dma@f8003000 {

#dma-cells = ;

#dma-channels = ;

#dma-requests = ;

arm,primecell-periphid = ;

clock-names = "apb_pclk";

clocks = ;

compatible = "arm,primecell", "arm,pl330";

interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", "dma4", "dma5", "dma6", "dma7";

interrupt-parent = ;

interrupts = , , , , , , , , ;

reg = ;

} ;

The following device tree snippet is from the Petalinux generated

device tree for the PS from the test system

© Copyright 2014 Xilinx .

ILA AXI Capture (Read)

The following screen capture shows the receive transfer performing

reads with a burst length of 1

The following screen capture shows the receive transfer performing

reads with a burst length of 16 (with the driver patched)

© Copyright 2014 Xilinx .

ILA AXI Capture (Write)

The following screen capture shows the transmit transfer performing

writes with a burst length of 1

The following screen capture shows the receive transfer performing

writes with a burst length of 16 (with the driver patched)

© Copyright 2014 Xilinx .

Conclusions

The PL330 Linux device driver in the mainline kernel (and the Xilinx

kernel tree) is functional

The driver and generated microcode are not optimized for high

performance

Small changes such as the burst length can increase the

performance

Larger changes are more complex and not recommended by Xilinx

Execution times are displayed for DMA transfers by the pl330test.c

driver

– These times were not intended for completeness with respect to benchmarking

– These times can show larger variances that have not been investigated

© Copyright 2014 Xilinx .

References

Zynq TRM, Chapter 9 http://www.xilinx.com/support/documentation/us

er_guides/ug585-Zynq-7000-TRM.pdf

ARM TRM for DMA-330 CoreLink DMA Controller DMA-330 Technical

Reference Manual

ARM AN239 - Example

programs for the CoreLink

DMA Controller DMA-330

ARM AppNote 239: Example programs

ARM AN228 –

Implementing DMA on

ARM SMP Systems

http://infocenter.arm.com/help/index.jsp?topic=/c

om.arm.doc.dai0228a/index.html