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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1

An On-Chip Delay Measurement Technique UsingSignature Registers for Small-Delay Defect Detection

Kentaroh Katoh, Member, IEEE, Kazuteru Namba, Member, IEEE, and Hideo Ito, Member, IEEE

Abstract—This paper presents a delay measurement techniqueusing signature analysis, and a scan design for the proposed delaymeasurement technique to detect small-delay defects. The pro-posed measurement technique measures the delay of the explicitlysensitized paths with the resolution of the on-chip variable clockgenerator. The proposed scan design realizes complete on-chipdelay measurement in short measurement time using the proposeddelay measurement technique and extra latches for storing the testvectors. The evaluation with Rohm 0.18- m process shows thatthe measurement time is 67.8% reduced compared with that ofthe delay measurement with standard scan design on average. Thearea overhead is 23.4% larger than that of the delay measurementarchitecture using standard scan design, and the difference of thearea overhead between enhanced scan design and the proposedmethod is 7.4% on average. The data volume is 2.2 times of that oftest set for normal testing on average.

Index Terms—Delay estimation, design for testability (DFT), in-tegrated circuit measurements, semiconductor device reliability,signature register.

I. INTRODUCTION

W ITH the scaling of semiconductor process technology,performance of modern VLSI chips will improve sig-

nificantly. However, as the scaling increases, small-delay de-fects which are caused by resistive-short, resistive-open, or re-sistive-via become serious problems [1]. If small-delay defectscannot be detected in LSI screening, the chips will behave ab-normally under particular operations in certain applications, andtheir lifetime may become very short due to the vulnerability tothe transistor aging. Therefore to keep the reliability after ship-ping, enhancing the quality of the testing for the small-delaydefect detection is an urgent need.

The delay measurement of paths inside the circuits is usefulfor detection and debugging of small-delay defects [2]. How-ever, it is impossible to measure the small circuit path delaysusing an external tester, even if the resolution is high. Therefore

Manuscript received April 02, 2010; revised August 26, 2010; acceptedFebruary 11, 2011. This work was supported by VLSI Design and EducationCenter (VDEC), the University of Tokyo in collaboration with Rohm Corpora-tion, Toppan Printing Corporation, Mentor Graphics, Inc, and Synopsys, Inc.This work was supported in part by the Grant-in-Aid for Scientific Research(C) 19560335.

K. Katoh was with the Faculty of Engineering, Chiba University, Chiba263-8522, Japan. He is now with the Electrical Engineering Department,Tsuruoka National College of Technology, Tsuruoka 997-8511, Japan (e-mail:[email protected]).

K. Namba and H. Ito are with the Graduate School of Advanced Integra-tion Science, Chiba University, Chiba 263-8522, Japan (e-mail: [email protected]; [email protected]).

Digital Object Identifier 10.1109/TVLSI.2011.2125994

development of the embedded delay measurement technique isrequired.

Some embedded delay measurement techniques have beenproposed. The scan-based delay measurement technique withthe variable clock generator is one of these on-chip delay mea-surement techniques [3]. In this technique, the delay of a pathis measured by continuous sensitization of the path under mea-surement with the test clock width reduced gradually by the res-olution. The main good point of the scan-based delay measure-ment technique is its high accuracy. The reason of the high ac-curacy is that the technique measures just the period betweenthe time when a transition is launched to the measured path andthe time when the transition is captured by the flip flop con-nected to the path, directly. The variation of the measured valuejust depends on the variation of the clock frequency of the clockgenerator. Therefore, if the clock generator is compensated theinfluence of the process variation, the measured value does notdepend on the process variation.

However, it has a drawback. The measurement time of thetechnique depends on the time for the scan operation. Thesedays, the gap between the functional clock and scan clock fre-quency increases. Therefore the measurement time becomes toolong to make it practical. Noguchi et al. proposed the self testingscan-FF. The flip flop reduces the required number of scan oper-ations, which makes the measurement time practical [2]. Theyalso proposed the area reduction technique of the self testingscan-FF [4]. However, the area overhead of these methods isstill expensive compared with the conventional scan designs.

This paper presents a scan-based delay measurement tech-nique using signature registers for small-delay defect detection.The proposed method does not require the expected test vectorbecause the test responses are analyzed by the signature regis-ters. The overall area cost is of the order of conventional scandesigns for design for test (DFT). The measurement time ofthe proposed technique is smaller than conventional scan-baseddelay measurement. The extra signature registers can be reusedfor testing, diagnosis, and silicon debugging.

The rest of this paper is organized as follows. In Section II,preliminaries are discussed. Section III explains the proposedmethod. Section IV shows the experimental results. Finally,Section V concludes this paper.

II. PRELIMINARIES

A. Related Works

These days, various methods for small-delay defect detectionhave been proposed. The path delay fault testing with a normalclock width is the most popular and is widely used [5]. In this

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2 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

method, we choose the longer paths to detect the smaller cu-mulative delay due to the small delay distributed on the paths.The larger the cumulative delays, the higher the probability ofthe detection of the distributed small delay. However, the cov-erage of the small delay defect detection largely depends on thenormal clock width, which is a problem of this method.

On the other hand, to solve the problem, methods with delayfault testing using a variable clock generator have been pro-posed. The delay fault testing with a smaller test clock reducesthe slack of the paths. Therefore the smaller delay defects whichcannot be captured with the normal clock width can be capturedwith the appropriate smaller test clock width.

Liou et al. proposed a small-delay defect detection methodconsisting of two test phases using both a tighter test clock anda normal clock [6]. In this method, the transition delay faulttesting with a tighter test clock width which is calculated basedon the characterized delay distribution is applied in the firstphase. After that, path or transition delay fault testing is ap-plied with a normal clock width in the second phase. The qualityof the method is higher than the conventional one phase testwith normal clock width. Yan et al. proposed a delay testingscheme that identifies small-delay defects in the slack intervalby comparing switching delays of a neighboring die on a wafer[7]. In this method, a fault site is sensitized multiple times con-tinuously with reducing the test clock width by the slack in-terval. The abnormal switching delays are detected by com-parison with the test results in the neighboring die. Anotherwork detects small-delay defects by analyzing the failing fre-quency, which is the minimum frequency that the delay faulttesting fails when the path is sensitized multiple times con-tinuously with increasing the test clock frequency [8]. Gener-ally, the variable clock testing requires a variable on-chip clockgenerator. Various variable on-chip clock generators have beenproposed [9]–[12]. In variable clock testing, the test clock fre-quency should be optimized to each test vector. To improve thetest quality, various optimization methods of the test clock andtest set have been proposed [13]–[15].

These days, small-delay defect detection methods usingon-chip delay measurement techniques have been proposed.The direct measurement of the real delay of each path ofeach chip screens outlier chips robustly even in the presenceof process variation or the gap between real and simulationenvironment. It realizes higher fault coverage of small-delaydefects than the simulation-based ones.

In addition, it can be used not only for the detection of small-delay defects, but also for the debugging [16], [17]. Becausemodern chips are too huge and complex, LSI CAD tools cannot optimize the design enough. Hence, the manufactured firstsilicon chip usually does not meet the specification in spite ofthe tighter release to production (RTP) schedule. Therefore sil-icon debugging and design for debugging (DFD) become muchmore important in modern chips [18]. Various silicon debuggingtechnologies and DFD methods have been proposed [19]–[22].On-chip delay measurement provides accurate information ofthe delay of inside paths for the debugging of small-delay de-fects [23].

Most of the conventional works of on-chip delay measure-ment are classified to either a proposal of an embedded delay

Fig. 1. On-chip variable clock generator [2].

measurement circuit or that of a scan architecture for scan-basedon-chip delay measurement with a variable clock generator.

Some works proposed embedded delay measurement circuitsof modified vernier delay line (VDL). Datta et al. proposed theembedded delay measurement circuit with high resolution [24].It is the first work of an embedded measurement circuit of mod-ified VDL to the best of our knowledge. Tsai et al. proposed thearea efficient and noise-insensitive modified VDL with coarseand fine parts namely BIDM [25]. Pei et al. also proposed thearea efficient modified VDL. The feature of this method is delayrange of each stage of VDL [26]. The delay ranges increase bya factor of two gradually, which reduces the required stages.Therefore the area is smaller than Datta’s work. The modifiedVDLs achieve high resolution. However they require redundantlines to feed the input and output signals of the measured paths,which needs the compensation of the delay effect of the redun-dant lines. Tanabe et al. solved the problem by removing thedelay of the redundant lines from the measured delay usingsome additional embedded circuits [27]. The proposed tech-nique is categorized to the scan-based one.

B. Variable Clock Generator

In the proposed method, the clock width should be reducedcontinuously by a constant interval as explained later. It is diffi-cult for an external tester to control this clock operation. There-fore an on-chip variable clock generator is indispensable forthe proposed method. In this paper, we use the on-chip variableclock generator proposed by Noguchi et al. [2].

Fig. 1 illustrates the circuit. The circuit consists of the phase-interpolator-based clock generator and the 2-pulse generator.The phase-interpolator-based clock generator generates an ar-bitrary clock width. The 2-pulse generator generates 2-pulsetest clocks with arbitrary timing in response to a trigger signal.Some of the specification and the evaluation results are shownin Table I [11].

C. Small-Delay Defect Detection With Delay Measurement ofChips

The proposed method uses the Noguchi’s small-delay defectdetection technique [2]. In this technique, the test clock width

KATOH et al.: ON-CHIP DELAY MEASUREMENT TECHNIQUE USING SIGNATURE REGISTERS 3

TABLE ISPECIFICATION AND MEASUREMENT RESULT [11]

Fig. 2. Decision of test clock width based on path delay distribution obtainedby chip measurement [2].

for delay fault testing of each path is determined with the normalpath-delay distribution of each path.

This strategy has already been applied to various small-delaydetection techniques [13].

But its originality is to obtain the path-delay distributionwith the delay measurement of the paths of the fabricated chips.Fig. 2 shows the path delay distribution of a path obtained bythe delay measurement of the fabricated sample chips. Thehorizontal axis is measured delay. The vertical axis is thenumber of chips. The chips which have delay inside the rangeVariation are normal chips. The chips which have delay outsidethe range Variation, namely , , ,are abnormal chips. The delay is the outside of theclock cycle in normal operation. Therefore it will be detected byconventional delay fault testing with the clock cycle in normalclock operation which is Conventional criteria. The delay

and are within the clock cycle in normaloperation. The conventional delay fault testing regards them asgood chips. However because the delay is outside Variation, itwill cause improper operations under particular operation incertain applications and may cause improper operations aftershipping due to the effect of aging [2]. In Noguchi’s technique,the test clock cycle is set to the upper limit of the distribution ofnormal chips, which is New criteria. Then all the outlier chipsare detected by the delay fault testing.

In small technology, the path-delay distribution calculated bysimulation is different from that of the fabricated chips. There-fore the quality of its strategy is higher than that of simulationbased ones. Because the Noguchi’s technique requires the mea-surement of the explicit paths, the paths should be single-pathsensitizable [5]. The aim of the technique is to screen the chips

Fig. 3. Concept of proposed delay measurement. (a) Basics of proposed mea-surement. (b) Signature table.

which have abnormal delay in gates or wires. Therefore the testset for the measurement should detect all the transition faultswhich are sensitized through single-path sensitizable paths. Theproposed method is a new delay measurement technique for thesmall-delay defect detection technique.

III. DELAY MEASUREMENT TECHNIQUE USING

SIGNATURE REGISTERS

This section explains the proposed measurement method.Section III-A presents the concepts of the proposed method.Section III-B explains the implementation of the proposedmethod. Section III-C describes the measurement sequence.The data volume and area overhead should be realistic comparedwith the conventional scan designs for DFT. Section III-D ex-plains the reduction method of the tester channel. Section III-Edescribes the scheme for the decision of the number of therequired extra latches to keep the cost realistic. To apply theproposed method and realize short measurement time, someconstraints should be put on ATPG. Section III-F explains theATPG constraints. Section III-G describes the measurementtime and data volume. Finally, Section III-H describes the testresponse tracing mode for finding lowest failing frequency ordiagnosis with transition fault test vectors.

A. Basics

This section explains the concept of the proposed delay mea-surement. The target paths of the proposed method are single-path sensitizable [5].

Basically, the proposed method is scan-based delay measure-ment. The difference from the basic one is the usage of the sig-nature registers and the additional latches for the acceleration ofthe delay measurement.

Fig. 3(a) shows the basics of the proposed method.This example has three flip flops , , and . Each

flip flop has the input line (bottom), the output line (upper), andthe clock line . Each flip flop is connected to an extralatch. At first, we assume that each flip flop has its own extralatch. The value of each flip flop is stored in the correspondentlatch, and the value of each latch can be loaded to the correspon-dent flip flops in arbitrary timing. In the proposed measurement,the test vector is stored in these latches after scan-in operation.Once the test vector is stored in the latches, the test vector can be


Fig. 4. Scan flip flops for proposed measurement.

Fig. 5. Four bit Reconfigurable signature register.

loaded from these latches in a clock without scan-in operation.It reduces the time for multiple sensitization of a path drasti-cally. The horizontal line through these flip flops represents thescan path. The symbols and represent the scan input andoutput, respectively.

The rectangle SIG represents the signature register using thelinear feedback shift register as its basic component. The inputof SIG is connected to the output of the last flip flop . Moredetail structures of the flip fops and the signature register areshown in Figs. 4 and 5, respectively.

Here, we measure the delay of . In this example, we assumethat the clock width of normal operation is 10 ns, and the reso-lution of the delay measurement is 2 ns. First, SIG is initializedwith reset operation. Second, the target path is tested continu-ously 5 times with the test clock reduced gradually by the resolu-tion. The multiple clock width testing is realized by the variableclock generator explained in Section II-B. The test clock of the1st testing (#1) is 10 ns. After the test, the test response is sentto SIG through the scan path with two clock shift out operation.The test clock of the second testing (#2) is 8 ns. Similarly, thetest clock width of the third, fourth, and fifth testings (#3, #4,#5) are the difference between 2 ns and the previous test clockwidth. Each test response is sent to SIG with two clocks. Afterthe above 5 times of delay fault testings, the signature value ofSIG is retrieved. To estimate the delay, the retrieved signaturevalue is compared with the expected signature values of the sig-nature table. Fig. 3(b) shows the signature table in this example.The table has four columns. The first column is the cases of themeasurement. The second column is the sequences of the test re-sponses of #1–#5. The third column is the path delay value. Thefourth column is the signature values of each case. Here,and are the signature values for rising and falling transitiontestings, respectively. The delay of each path is decided as morethan 10, 8–10, 6–8, 4–6, 2–4, or 0–2ns, with 2ns resolution. Thesequences of the test responses of the 5 times measurement areshown in Fig. 3(b). The symbols , , , ,

, indicate the cases with path delays, more than 10,

8–10, 6–8, 4–6, 2–4, 0–2 ns, respectively. The symbols andrepresent the pass and fail of a testing, respectively. In case

of rising transition testing, and , and in case offalling transition testing, and . The retrieved sig-nature value is compared with the expected signature values onthe table, and decides the delay value.

When the number of flip flops is , clock width is , themeasurement resolution is , and the continuous testing timeis , the delay measurement sequence of a target path is asfollows. Here, we assume that the test vector is already storedin the latches. The end point of the measured path is

.Step 1: Initializing SIG.Step 2: Test vector is loaded from the latches.Step 3: Test clock width is set to normal clock width.Step 4: Test clock is applied.Step 5: The test response is sent to SIG which is connected

to the output of with clocks.Step 6: If testing time is equal to , go to Step 7 after

the signature value of SIG is retrieved, otherwise goback to Step 2 after the test clock width is updatedto .

Step 7: The delay value is estimated by comparing the re-trieved signature value and the signature table.

B. Implementation

In this subsection, we explain the implementation of the pro-posed measurement system. First we explain the important com-ponents to understand the whole system. After that, the wholesystem is presented.

1) Scan Flip Flop for Measurement: Fig. 4 is the gate leveldescription of the scan flip flop for the proposed measurement.The lines , , and are the input, output, and clock lines,respectively. The line is connected to an extra latch whichprovides the test bit to the flip flop. The lines and are theinput and output for constructing the scan path. The input isconnected to of an adjacent scan flip flop or the scan input.The output is connected to of an adjacent scan flip flop orthe scan output. The flip flop has two multiplexers. The linesand are the inputs of the upper multiplexer controlled by

. The output of the upper multiplexer and are the inputsof the bottom multiplexer controlled by . When , theflip flop is in normal operation mode. When and

, the flip flop is in scan operation mode. When ,, the flip flop loads the value stored in the latch connected to

the latch line.2) Reconfigurable Signature Register: The signature register

for the proposed measurement requires the following functionsto meet the demand of the proposed measurement.

• Capturing the test response in arbitrary timing.• Shifting out the signature data in arbitrary timing.Fig. 5 shows the architecture of the signature register for the

proposed measurement. The length of the signature register inthis example is four bit. Therefore it has four flip flops ,

, , .The signature register can be configured to a shift register.

The line controls the configuration. When , it worksas a signature register. When , it works as a shift register.


Fig. 6. Proposed measurement system.

The line is the input of the signature register. During mea-surement, test responses are sent to . The line is clock line.The clock line is controlled by . When , the signatureregister does not capture the input value. When , the sig-nature register captures the input value synchronizing with thepositive edge of . By controlling , the signature registerscapture only the target test response.

When , this circuit is configure to the shift register.The input is . The output is . As explained later, the mea-surement system requires multiple signature registers generally.The input and output are connected to the output and the inputof adjacent signature registers to construct a long shift registerfor sending all the signature values to the external tester.

3) Whole System: Fig. 6 shows the proposed measurementsystem. The proposed system consists of the low cost tester andthe chip with the variable clock generator (VCG) explained inSection II-B and a BCD decoder. The chip is assumed to havesingle functional clock in the proposed method, and the chip hastwo reset lines for initializing the flip flops and the signatureregisters independently. The reset operations are controlled bythe tester.

The low cost tester controls the whole measurement se-quence. The clock frequency is slower than the functionalclock. The line retrieves the signature data from the signa-ture registers to estimate the measured delay. The line sendsthe test vectors to the scan input of the chip. The line getsthe data of the flip flops from the scan output of the chip. In theproposed measurement sequence, is not used. However, itis used to check the flip flops or the additional latches beforethe measurement. The line is the clock control line. Theproposed measurement uses both the slow tester clock and

the fast double pulse generated by on-chip VCG. The lineselects the slow and fast clock. If is 1, the fast clock is sentto the clock line of the components. Otherwise the slowtester clock is sent. The lines and are the input linesfor VCG. The fast double pulse is launched synchronizing withthe positive edge of . The line controls the width ofthe double pulse. The line controls the scan flip flops. Theline controls the latches for storing test vectors. The lines

are the inputs for the encoded data to controlthe capture operation of the signature registers. The BCDdecoder decodes the encoded input data to the control data ofthe signature registers . As explained later, thedecoder is used to reduce the input lines for the control dataof the signature registers. The is the enable signal for thesignature registers. The flip flops in the chip are classified tothe clusters . Here, we assume that each clusterhas flip flops, and thus the number of the flip flops is .In general, the number of the flip flops of the last cluster is

, where is the number of flip flops, or . Thecoordinate written in the flip flops indicates the location.The number is the cluster id. The number is the order inthe cluster. The output of the flip flop of which isthe tail flip flop of each cluster is connected to the flip flopof which is the head flip flop of . These linesconstruct the scan chain. The output of the tail flip flop of eachcluster is connected to the input of the corresponding signatureregister. The paths whose test response is captured by the flipflops included in is measured by . The control lines ofthe signature registers are connected to the BCD decoder.

C. Measurement Sequence

Here, we explain the measurement sequence. First, the mea-surement sequence of the paths simultaneously sensitized in atest vector is explained in Section III-C1. After that, the wholemeasurement sequence is explained in Section III-C2.

1) Measurement Sequence Per a Test Vector: Whenthe measurement system has signature registers,

paths can be measured in parallelmaximally. To reduce the measurement time, we measuremultiple paths simultaneously.

We explain the measurement strategy using the example de-picted in Fig. 7. In this example, the proposed method is appliedto the circuit with six flip flops . These flip flopsare classified to the two clusters and . The clusterincludes , and includes .The cluster has the signature register . The cluster

has the signature register . The clock line con-trols these flip flops. The control lines controls the cap-ture operation of , and controls the capture opera-tion of . The paths , , , are sensitized simulta-neously by the test vector

. The test response of is captured by . Theexpected test response is

.The paths and are measured by . The paths andare measured by . The combination of the two paths,

one of which is selected from and , the other of which isselected from and , can be measured simultaneously.


Fig. 7. Measurement of paths sensitized in a test vector in parallel. (a) Scan-intest vector and store it to latches. (b) �� —After each testing, send test re-sponses of � and � to �� and �� , respectively. (c) �� —After eachtesting, send test responses of � and � to �� and �� , respectively.

Although the four paths are sensitized by the test vector, twopaths can be measured simultaneously at most. Hence, we mea-sure the four paths divided into two measurement stagesand each of which measures two paths simultaneously.Here, we measure and in . The rest of the pathsand are measured in .

First, the test vector is set to the flip flops with scan-in oper-ation. After that, the values of the flip flops are set to the extralatches (a). Second, the first stage measurement is performed(b). Third, the second stage measurement is performed (c). Ineach stage, the paths under measurement are tested multipletimes with reducing the test clock width. Steps (b) and (c) showthe state just after the test execution. The flip flops hold the testresponse. The latches hold the test vector. After the testing, thetest responses are shifted to the signature registers and

with the clock operation of . The required number ofshift clocks of a stage is the maximum number of the shift clocksamong the paths measured simultaneously in the stage. For ex-ample, in , two clocks are required to send the test re-sponse of to , while one clock is required to send the test

Fig. 8. Timing chart of the sequence of Fig. 7.

response of to . Therefore the shift clocks of aretwo clocks. Similarly the shift clocks of are three clocks.Like this, the number of the required shift clocks varies in eachstage. To capture only the target test response value, the controlbit sequences are sent to and . In , the test re-sponse of is captured to . Therefore should capturethe value two clocks later. This operation is realized by sendingthe bit sequence “01” to synchronizing to the . To cap-ture the test result of , should capture the value one clocklater. This operation is realized by sending the bit sequence “10”to synchronizing to the in . In , the test re-sponse of is captured by sending the bit sequence “100” to

, and the test response of is captured by sending the bitsequence “001” to , respectively.

Fig. 8 shows the timing chart of this operation. The low costtester controls the whole measurement sequence. For the mea-surement both VCG clock and tester clock are used. The clockselection is controlled by . The trigger signal and the con-trol signal is provided to VCG. The control data is up-dated after each testing operation. In , captures thetest response in the second shift-out clock. Therefore turnsto 1 synchronizing with the negative edge of the first clock ofthe shift-out operation. The latch clock captures the valuesof the flip flops just after the scan-in operation is finished. The

, , are controlled as explained previously.2) Whole Measurement Sequence: Here, we assume that

the test set for the measurement has test vectors. The number of the stages of is .

Before measurement, we have to check if the flip flops, thelatches, and the clock generator work correctly by applying testvectors or other checking methods. After that, the followingmeasurement sequence is executed.Step 1: Initialize the variable .Step 2: If is equal to , finish, otherwise initialize the

variable to 0, and set to the flip flops withscan-in operation.

Step 3: Send the values of the flop flops to the latches.Step 4: The paths included in are measured simulta-

neously. After that, is updated to .


Step 5: If is equal to , go to Step 6, otherwise loadthe test vector from the latches to flip flops, and goto Step 4.

Step 6: is updated to , and go to Step 2.

D. Tester Channel Reduction

If of each signature register is directly fed to the inputsof the chip, it requires the same number of the extra inputs asthe number of the signature registers. It increases tester channelwidth. To keep the tester channel width short, we use the BCDdecoder as depicted in Fig. 6. The decoder circuit transforms

bit binary code to the corresponding width decimal code.For example, when , , the correspondingdecimal code is . We explain how toencode the bit sequences to the corresponding binary code

with the example depicted in Fig. 9. This example consistsof three clusters , , and . Each cluster has three flipflops. Consider the case that the test response of the sensitizedpaths are captured in , , . In the shift out oper-ation after a testing, the test response of is captured by

two clocks later. Therefore the bit sequence “010” shouldbe sent to . The test response of is captured byone clock later. Therefore the bit sequence “100” should be sentto . The test response of is captured by threeclock later. Therefore the bit sequence “001” should be sentto . Each bit value of these bit sequences is grouped. Thegroup of the 0th bit values is . Those of thefirst bit values and second bit values are ,

, respectively. We call each group slice.Here, represents the slice of th bit. Finally, these decimalcodes are transformed into the corresponding binary code. The0th slice “010” is transformed to “01”. The 1st slice“100” is transformed to “10”. The second slice “001” istransformed to “11”. As a result, the bit width of the data is re-duced from 3 bit to 2 bit by this transformation. Generally, thewidth of the slice of is , the width of encoded slice ofis . However, for the encoding, each slice is permittedonly 1 bit with the value 1. More than two bits with value 1 isnot permitted. This restriction puts the constrain on ATPG forthe generation of the test set for the measurement.

E. Scheme for Decision of Number of Extra Latches

The proposed method uses extra latches to accelerate themeasurement time. To simplify the explanation, we have as-sumed that each flip flop has an extra latch until the previoussubsection. But adding an extra latch to each flip flop makesthe area overhead unrealistic. To solve the problem, we makemultiple flip flops share an extra latch.

This subsection explains the scheme for the decision of thenumber of the required extra latches. The proposed scheme de-cides the number of the required extra latches, the connectionfrom the outputs of flip flops to the inputs of the latches, andthe connections from the outputs of the latches to the latch linesof the flip flops. The proposed scheme makes the number of therequired extra latches as small as possible considering the testvectors and the routing restriction. We explain the scheme withthe example shown in Fig. 10. This example includes six pro-posed scan flip flops, . The scan input and output are

Fig. 9. Encoding the output data of BCD decoder �� to the input data of BCDdecoder ��.

and , respectively. All the paths are assumed to be mea-sured by three test vectors, . A bit is representedby the symbol . The bit vector is the setof the th bits of the test vectors, where is the th bit of .Routing window is introduced to avoid extraordinary long re-dundant lines. In the process of searching the sets of flip flopssharing a latch, the search space is restricted within the window.In this example, the window width is three.

At first, the latch line of each flip flop is not connected. Inphase (a), the routing window is set on the scan input. The bitvectors, of , , inside the window arechecked if there exists sets of bit vectors which are mergeableeach other. If such a set exists, a latch is assigned to the set. Theinput of the latch is connected to the output of a flip flop of theset. The output of the latch is connected to the latch lines of allthe flip flops of the set. In this example, and are mergeable.A latch is assigned. The merged bit vector is updated to thevalues after merge operation. The routing window is shifted 1 bitalong the scan chain. The above operation is repeated until therouting window reaches the scan output in phases (b), (c), (d).After that, in the final phase (d), each flip flop whose latch line isnot connected yet is assigned a latch, and the input is connectedto the output of the flip flop, and the output is connected to thelatch line.

F. Constraints for ATPG

The test set for the measurement is obtained by the determin-istic test generation with ATPG. The measurement time dependson the sum of the number of the stages of the test vectors. There-fore, to reduce the stages of each test vector, we add the con-straints to as many measure paths as possible.

Normal ATPG tries to sensitize paths in arbitrary order. How-ever when the generated test set is applied to the measurement


Fig. 10. Assignment of the extra latches.

sequence, it leads to the imbalance among the number of pathsmeasured in the signature registers. Therefore the number of thestages may increase.

To reduce the stages, we should keep the balance among thenumber of paths measured in the signature registers. In addition,

the of each signature register should meet the constraintsexplained in the previous subsection. Accordingly, the order ofthe path sensitization is determined by the sequence for the pro-posed measurement.

For the description of the sequence, we define some addi-tional parameters and functions.

The obtained test set.

The maximum number ofpaths measured by a testvector.

The maximum number ofstage in each test vector.

The end point of .

The number of clusters.

If there exists anysensitizable paths leftin the test vector , returntrue, otherwise return false.

During seeking paths forthe th stage, if there existsa path that alreadyassigned to th stage and

and is in thesame cluster, return true,otherwise return false.

During seeking paths forthe th stage, if thereexists a path thatalready assigned to theth stage and the orders

of in eachcluster are same, returntrue, otherwise return false.

The sequence is as follows.Step 1: If all the paths are sensitized, finish, otherwise ini-

tialize .Step 2: If is false, or, is equal

to , or is equal to , push the testvector to , update , and go to Step 1,otherwise go to Step 3.

Step 3: If is equal to , update , initialize, and go to Step 2, otherwise pick up a path

from path list, and go to Step 4.Step 4: If is true, go to Step 2, otherwise

go to Step 5.Step 5: If is true, go to Step 2, other-

wise go to Step 6.Step 6: Try to sensitize . If is sensitized successfully, as-

sign to , and update , .Go to Step 2.

G. Measurement Time and Data Volume

We describe the measurement time and data volume. Weassume that the test set which has test vectors,


, is applied. The number of stage of is.

Here, we define some additional parameters.

The length of scan chain.

The test clock width.

The shift clock of the th stage of the th testvector .

The length of the signature register.

The number of the signature registers.

The maximum number of flip flops inside acluster.

The number of the paths under measurement.

The number of the primary inputs.

The number of the primary outputs.

The whole measurement time is the sum of: 1) the time re-quired for the whole scan-in operations and 2) the time requiredfor the measurement of the whole measurement stages.

The time required for the whole scan-in operation is. Considering that the double pulse for the

testing is triggered by the positive edge of the tester clock andthat the shift-out of the signature data of the last stage andthe scan-in operation of the next test vector are performedin parallel except the measurement with the final test vector,the time required for a measurement with th test vector ex-cept the last test vector is

. Therefore the measure-ment time of the proposed method is calculated by thefollowing formula:

(1)

Let be the number of test vector generated withoutthe extra constraints for the proposed method: then

(2)

where is a constant value larger than 1. The value dependson the circuits and ATPG constrains.

The measurement time with normal scan design is cal-culated by the following formula:

(3)where is the number of the average contin-uous testing time. Unlike the proposed method, the continuoustesting time of each test vector depends on the longest path mea-sured.

The data volume of the proposed method is the sum of:1) the test data volume; 2) the data indicating the polarity ofeach path; 3) the data for the control of the capture timing of

the signature registers; 4) the data for the signature table; and5) the data indicating the number of the measurement stage ofeach test vector.

The amount of the test data volume is .The amount of the data indicating the polarity of the paths is .The amount of data for the control of the capture timing of thesignature registers is

. The amount of the data for the signature table is. The amount of the data indicating the

number of the measurement stages of each test vector is, where is the maximum

number of the stages among . There-fore the is calculated by the following formula:

(4)

whereas the data volume for the measurement with normal scandesign is calculated by the following formula:

(5)

H. Test Response Tracing

The target paths of the proposed measurement are single-pathsensitizable. However, some applications require lowest failingfrequency [28], [29] and trace the test response sequence in acontinuous sensitization of the path under measurement withreducing the test clock frequency.

In single-path sensitizable path measurement, it is guaranteedthat once the test fails, the test with higher frequency than thefailing frequency is fail.

But in single-path unsensitizable path measurement (forexample, multiple reconvergent paths), it is not guaranteed.For example, in case of the example of Fig. 3, only the 6patterns, “ ”, “ ”, “ ”, “ ”,“ ”, and “ ” should be considered.

When a single-path unsensitizable path is measured, we couldhave responses such as “ ”. For such a case, the pro-posed method has the test response tracing mode as an optionalfunction. In this mode, the test response patterns are not com-pacted by signature registers. We get the raw test response pat-tern. This mode is realized by cutting off the feedback loop with

during the measurement.Let be the length of a signature register, then the mea-

surement sequence of a path with the test response tracing modeis described as follows.Step 1: SIG is initialized.Step 2: Test vector is loaded from the latches.Step 3: Test clock width is set to normal clock width.Step 4: Test clock is applied.Step 5: The test response is sent to SIG with scan-out opera-

tion.


Step 6: If testing time is equal to or is multiple numberof , the values of the flip flops of SIG is re-trieved. After that, if testing time is equal to ,go to Step 7, otherwise go back to Step 2 after thetest clock width is updated to .

Step 7: The delay value is estimated by comparing the re-trieved signature value and the signature table.

In this mode, we have to retrieve the values stored in theflip flops of the signature registers every times. Thereforewhole measurement time is longer than normal mode.

IV. EXPERIMENTAL RESULT

In this section, we present the experimental results. InSection IV-A, the proposed method is compared with theconventional methods.

The clock frequencies are the same as that of Noguchi’smethods [2], [4], that is, the normal clock frequency is 100MHz, and the scan clock frequency is 10 MHz. The lengthof the signature register is 8 bit. The test set consists of testvectors which detects all single-path sensitizable transitionfaults. The paths sensitized by these test vectors are measured.In this evaluation, the average delay of signal propagationof the measured paths is assumed to be the half of the clockwidth. Usually the length of the sensitized paths for transitiondelay defect detection is relatively short because ATPG seeksthe paths whose length is as short as possible for the costof test generation. From this point of view, we believe thatthis assumption is valid. In this evaluation, the test set for themeasurement is generated by podem-based ATPG algorithm,which is implemented by C++. The back track limit is 200. Forthe evaluation, relatively larger ISCAS’89 benchmark circuitsare used.

The measurement time using the proposed scan design andstandard scan design is calculated by the (1) and (3), respec-tively. The results of area are obtained by synthesis with Syn-opsys design compiler using Rohm 0.18 m process. The datavolume of these methods are calculated by the (4) and (5), re-spectively.

In this evaluation, area overhead , area overhead in-cluding the area of VCG, and the routing overhead are de-fined as follows.

, where is the area of thecircuits implemented the evaluated method except VCG, and

is the area of the non-scan circuit except clock generator., where is the area of the circuits

implemented the evaluated method including VCG. The area ofVCG is obtained from the paper [11].

Note that , and include the area of the wires., where and are the

routing area of the evaluated circuit and non-scan circuit, re-spectively.

The reduction ratio of measurement time is defined as, where and is the mea-

surement time of the evaluated method and that of standard scan,respectively.

The increase ratio of the data volume is defined as, where and is the data volume

of the evaluated method and that of standard scan, respectively.

A. Comparison With Conventional Scan-Based Measurement

In this section, the proposed method is compared with thedelay measurement with conventional scan designs, namelystandard scan design and enhanced scan design. In this eval-uation, is fixed to 8. The length of cluster isrestricted to 32 or 64.

1) Area Overhead: Table II shows the result of the area androuting overhead. The column shows the name of bench-mark circuits. The column is the number of flip flops in-side the circuit. The column is the area of the non-scancircuit (mm ). The columns , , show the evalua-tion results of the circuits applied standard scan, enhanced scan,and the proposed method, respectively. The subcolumn isthe bit rate, which is defined aswhere is the number of bit and is the number ofthe whole bits of the test set. The subcolumn is the ratio ofthe number of the extra latches against , which is de-fined as . The difference betweenof enhanced scan design and the proposed method is 7.4% onaverage. The difference is negligible considering the area over-head of standard scan design. The area overhead of the proposedmethod tends to decrease as the circuit’s size increases. One ofthe reasons is that tends to decrease as the circuit’s size in-creases. According to the result, tends to decrease as thebit density is higher. The difference of enhanced scan de-sign and the proposed method of the larger circuits s38417 ands38584 are 2.8% and 4.2%, respectively. Because a test set oflarger circuits has higher X bit density in general, the area over-head tends to be smaller as the size of the applied circuit in-creases. The area overhead of s35932 is larger in spite of the low

bit density. It is because the number of the signature registersis larger than those of s38417 and s38584 for the smaller .The same inclination can be seen in although the absolutevalue is larger for the area of VCG. The routing overheadof the proposed method is 12.9% larger than that of enhancedscan design. But the impact to the whole area overhead and

is smaller.2) Measurement Time: The result of the measurement time is

shown in Table III. Here, we show the result whenand , respectively. The subcolumns (ms) and

(ms) are the measurement time of standard scan design andthe proposed method, respectively. According to the result,when and are 67.8% and 71.9%,respectively. The reduction ratio when is4.1% higher than when . It is because theimpact of the time for scan-in operation of each test vector onthe measurement time decreases as increases.

3) Data Volume: Table IV shows the evaluation result ofthe data volume and the reduction ratio whenand . The subcolumns (MBits) and(MBits) are the data volume of standard scan design and the pro-posed method, respectively. The data volume when

and when are 119.2% and 119.3% on av-erage. They are almost the same. The larger is, the larger


TABLE IIDETAIL OF THE AREA OF THE CIRCUITS APPLIED THE PROPOSED METHOD

TABLE IIIMEASUREMENT TIME

TABLE IVDATA VOLUME

the amount data for the signature table. But the evaluation resultshows that the impact on the whole data amount is negligible.

4) Estimation of Measurement Time of Larger Circuits: Weestimate the measurement time of larger circuits. The scan chainlength indicates the size of the circuits. Therefore weinvestigate the relation between and . When we as-sume that the number of the measured paths per a test vector is

and the distribution of the end points of the measuredpaths is uniform, the average of the number of the shift clockper a stage is approximated by the following formula, sta-tistically:

When and , . We assume, which is the average value of Table II, and

.Assuming these values, we calculate when ,

1000, 3000, 5000, 10 000, and plot them. Fig. 11 shows the re-sult. The horizontal axis is . It indicates the size of thecircuit. The vertical axis is . In this condition, when

is negative value. However when is largerthan 5000, it reaches to over 80%. The result shows that the pro-posed method gives better measurement time as the size of thecircuits is larger.

Fig. 11. Relation between � and � .

Fig. 12. Relation between � and � .

Next, we investigate the influence of the variation of thenumber of the test vectors. The number of test vectors dependson the structure of circuits or ATPG algorithm. We plot themeasurement time when is 500, 1000, 1500, 2000 inthe condition that . Fig. 12 shows the result. Thehorizontal axis is . The vertical axis is . As shownin this figure, the increases as increases.

In this estimation, the interval between the adjacent signatureregisters is . Therefore the area overhead is in thesame order of the previous evaluation. As the size of circuitincreases, the influence of the area of the test clock generator onthe area overhead is smaller. Therefore the area overhead willbe convergent to that without the test clock generator.


TABLE VCOMPARISON OF MEASUREMENT TIME WITH THAT OF [21] AND [22] ��s�

TABLE VICOMPARISON OF AREA OVERHEAD WITH [21] AND [22] OF B19 (%)

B. Comparison With Delay Measurement Using Path RingOscillator

First, we compare the measurement time with the delay mea-surement method using path ring oscillator [21], [22]. They arecompared under the condition of the experiment of [22] and re-ferring the experimental result. The test clock frequency and thescan chain length of the target circuit is 100 (ns) and 100, re-spectively. The number of the paths under measurement is 100.The measurement time of both of [21] and [22] are the sum ofthe calibration time and the execution time of the measurement.According to [22], the calibration time of [21] and [22] are 700and 17 s, respectively. Here, the measurement time of the twomethods are approximated with the time required for the scan-inoperations of test vectors. Therefore the execution time of themeasurement is approximated to 0.1 s 1000 s.The number of test vectors is set to the half of the numberof the path considering those of the evaluated circuits ofthe same order. The length of the cluster is set to 10. Theremaining parameters for the proposed methods are set to thesame values of the previous evaluations. Table V shows the re-sult. In this condition, the measurement time of the proposedmethod is 3.4 times of that of [21], 5.7 times of that of [22].

The area overhead is compared with [21] and [22] using b19,which is an ITC’99 benchmark circuit. Here, the area over-head of both for the proposed method is defined as

. It is compared withthe results of [21] and [22] when the number of the path undermeasurement is 50, 100, 200, 500. The set of paths undermeasurement for the proposed method is the one of the longestpaths of randomly selected end points. The length ofcluster is set to 64. The other parameters are the same asthe previous evaluations. Note that in this evaluation, the flipflops which are not assigned care bits are not connected to anyextra latches.

Table VI shows the result. On average, the area overhead is6.508% and 6.072% larger than those of [21] and [22], respec-tively.

C. Comparison With Delay Measurement Using EmbeddedDelay Measurement Circuit

Finally, the proposed method is compared with the delay mea-surement using embedded delay measurement circuits. In thisevaluation, the architecture of the path measurement schemeproposed in [26] depicted in Fig. 13 is assumed. Table VII shows

Fig. 13. Architecture of the path measurement scheme using embedded delaymeasurement circuit [26].

TABLE VIICOMPARISON WITH DELAY MEASUREMENT USING EMBEDDED DELAY

MEASUREMENT CIRCUIT

the result. The subcolumn and shows the evaluationresults of the measurement using the embedded delay measure-ments and the proposed methods, respectively. The subcolumn

is the ratio of the delay measurement time of the proposedmethod against that of the measurement using embedded delaymeasurement. The area overhead of the proposed method is8.2% larger on average. The value is 1.4 on average. It meansthat the measurement time of the proposed method is 1.4 timesof that of the embedded delay measurement approach. Actuallythe area overhead of the embedded delay measurement approachis area efficient. But it requires large-sized two multiplexes. Un-less the layout and routing is performed carefully, it may give se-rious impact on the performance and measurement accuracy. Onthe other hand, the proposed method does not use the large-sizedmultiplexers but use scan chain and limited length extra wires.Therefore it has less probability of degradation of the perfor-mance of normal operation. The embedded delay measurementapproach can measure a path per a test vector. Therefore themeasurement time increases as the number of the measuredpath. In general, the measured path increases as the circuit sizeincreases. Hence in the larger circuits like s38417 and s38584,the measurement time of the proposed method is better.

V. CONCLUSION

The proposals of this paper are as follows.• The proposal of the delay measurement method using sig-

nature analysis and variable clock generator.• The proposal of a scan design for the delay measurement

of internal paths of SoC.The first proposal can be applied not only SoC but also field-

programmable gate array (FPGA) [30]. Because the process ofFPGA is getting extraordinary smaller these days, the small


delay defect becomes serious problem in FPGA, too. In thismeaning, the application of the proposed method to FPGA isalso useful. A future work is the low cost application of the pro-posed measurement to FPGA.

When we measure short paths the measurement error can in-crease for the IR drop induced by higher test clock frequency. Itcan reduce the test quality. Another future work is the reductionand the avoidance of the measurement error caused by the IRdrop.

APPENDIX

The signature value of a rising transition testing can be cal-culated from the corresponding one of falling transition testing,and vice versa. Let be the signature value of the rising tran-sition of , and be that of the falling transition: then

(6)

where is the signature value when the bit bi-nary sequence is sent to the signature register.

The reason is as follows. Linearity of the signature valuegives the following relation between the two bit sequences

and

Substitute for : then

(7)

Let and be the test responsesequences of the rising and falling transition test of , re-spectively: then

(8)

Substitution of (8) into (7) gives (6).Therefore the amount of the data for the signature table of (4)

is not but .

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[30] Xilinx, San Jose, CA, “Virtex-5 user guide,” 2010. [Online]. Available:www.xilinx.com

Kentaroh Katoh (M’04) received the B.E. and M.E.degrees from Nagoya University, Nagoya, Japan, in1997 and 1999, respectively, and the Ph.D. degreefrom Chiba University, Chiba, Japan, in 2009.

In 1999, he joined Fujitsu Limited and engaged inthe development of the embedded control system ofHDD from 1999 to 2001. He joined Chiba Univer-sity, in 2001. Since 2011, he has been a member ofTsuruoka National College of Technology. He is cur-rently an Associate Professor with the Electrical En-gineering Department. His research interests include

testing method and fault-tolerant design of reconfigurable hardware and SoC.He is a member of the IEICE.

Kazuteru Namba (M’03) received the B.E., M.E.,and Ph.D. degrees from the Tokyo Institute of Tech-nology, Tokyo, Japan, in 1997, 1999, and 2002, re-spectively.

He joined Chiba University, Chiba, Japan, in 2002.He is currently an Assistant Professor with the Grad-uate School of Advanced Integration Science, ChibaUniversity. His current research interests include de-pendable computing.

Dr. Namba is a member of the IEICE and the IPSJ.

Hideo Ito (M’01) was born in Chiba, Japan, on June1, 1946. He received the B.E. degree from Chiba Uni-versity, Chiba, Japan, in 1969 and the D.E. degreefrom Tokyo Institute of Technology, Tokyo, Japan, in1984.

He joined Nippon Electric Co. Ltd. in 1969 andKisarazu Technical College in 1971. Since 1973,he has been a member of Chiba University. Heis currently a Professor of Graduate School ofAdvanced Integration Science. His research interestsinclude easily testable VLSI design, defect-tolerant

VLSI design, VLSI architecture, fault-tolerant computing, and dependablecomputing.

He is a fellow of the IEICE and a member of the IPSJ.

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