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SYLLABUS FOR COURSE

)VHDL(ADVANCED DIGITAL SYSTEMS

Lecturer: Dr. Evgeni Perelroyzen Prerequisites for Course 1.Logic Circuits 2.Optimized Implementation of Logic Functions 3.Number Representation 4.Basic Combinational Circuits 5.Basic Sequential Circuits Detailed Teaching Plan

1. DESIGN CONCEPTS 1.1. Digital Hardware

1.1.1. Standard Chips - 7400-Series Standard Chips

1.1.2. Programmable Logic Devices - Programmable Logic Array (PLA) - Programmable Array Logic (PAL) - Programming of PLAs and PALs - Complex Programmable Logic Devices (CPLDs) - Field-Programmable Gate Arrays (FPGA) 1.1.3. Custom-Designed Chips

1.2. The Design Process [1, 5, 6] 1.2.1. Design Methodology. Top-Down Design(Flow) [5, 6, 9] 1.2.2. A Systematic Approach to Logic Design [5] 1.2.3. Verification [6, 9]

- Summary of the different simulation alternatives [6] - Simulation Speed - Formal Verification - Recommendations for Verification

1.3. Design of Digital Hardware-Digital System Design Process [1, 9] 1.3.1. Basic Design Loop 1.3.2. Design of a Digital Hardware Unit 1.3.3. Overview of Digital Logic Design [5] 1.3.4. Overview of Combinational Circuit Design [5]

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1.3.5. Overview of Sequential Circuit Design [5] 2. INTRODUCTION TO CAD TOOLS

2.1. Hardware Design Environments – Design Automation [9] 2.2. The Art of Modeling [9] 2.3. Design Entry 2.4. Hardware Simulation(Modeling Digital Systems) [1, 3, 6, 9]

- Domains and Levels of Simulation(Modeling) [3] - Functional and Timing Simulation [1] - Oblivious Simulation [9] - Event-Driven Simulation [9]

2.5. Hardware Synthesis and Optimization [1, 9] 2.6. Physical Design 2.7. Summary of Design Flow 2.8. Rapid Prototyping [6] 2.8.1. Rapid Prototyping 2.8.2. Real-time Kernel-a Brief Description 2.8.3. The Development System 2.8.4. Development Phases 2.9. Why use Hardware Description Languages (HDL) [4, 6, 9, 7]

- VHSIC(Very High Speed Integrated Circuit) Program - Traditional Schematics - Symbols Versus Entities - Schematics Versus Architecture - A Language for Behavioral Descriptions - A Language for Describing Flow of Data - A Language for Describing Netlist - VHDL(VHSIC Hardware Description Language) as a Standard - VHDL Advantages [7] - New Design Methodology [7]

2.10. What is Logic Synthesis? [7] 2.11. Examples of Circuits Synthesized from VHDL Code 2.12. Development Tools [6]

2.10.1. Synopsys - Design Ware - VHDL Compiler and Design Analyzer - Design Compiler - ATPG Tools - FPGA Compiler - VHDL Simulator

2.13. Test Applications [9] 2.14. Test Bench [6]

2.14.1. VHDL Description of a Simple Test Bench [9]. Simulation 2.14.2. Different Levels of Test Bench

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2.14.3. Pull up/down 2.12.4. Several Components in the same Test Bench 2.12.5. Waveform Generators 2.12.6. TextIO 2.12.7. A Design Case and Test Bench [7]

- Design Description - Writing VHDL Model - Another Test Bench - Synthesizing the Design

2.12. Levels of Abstraction 3. HARDWARE DESCRIPTION LANGUAGES. VHDL [1, 5, 6]

3.1. Introduction to VHDL. Design Methodology Based on VHDL [1, 9]

3.1.1. VHDL Language Abstractions [6] 3.1.2. Design hierarchies-reducing complexity [6] 3.1.3. Basic Concepts in VHDL [3, 4, 9, 7]

- Characterizing Hardware Language Timing : Event Scheduling Concurrency : Statement Concurrency Modeling Hardware

- Objects and Classes - The Concept of the Signal. Signal Assignments - Concurrent and Sequential Assignment - Process Concurrency. Process Activation by a Signal

Event - Delta Time - VHDL Terms

- VHDL Design Entity: ENTITY Declaration, ARCHITECTURE Body - Structural and Behavioral Architectures [1, 6, 3]

- Mixed Structural and Behavioral Models [3] - Signal-Valued andb Signal-Related Attributes [7]

3.1.4. Components of a VHDL Description [1, 5] - Using Sub-circuits: Declaring a COMPONENT

3.1.5. Construction of a VHDL Program [5] 3.1.6. Representation of Digital Signals in VHDL 3.1.7. Transport Versus Inertial Delay [4]

- Inertial Delay Model - Transport Delay Model - Simulation Deltas

3.1.10.Writing Simple VHDL Code 3.1.11.Complete VHDL Examples [5] 3.1.12.How Not to Write VHDL Code 3.1.14.Writing Efficient VHDL Code [7]

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3.1.13.Documentation in VHDL Code 3.1.14.Other Modeling Languages for describing electronics - Verilog HDL [2, 24, 25]

- ABEL [11, 2] - AHPL [9] - ADLIB [37] - CDL [9] - CONLAN [9] - CUPL [2, 12] - HILL [38] - IDL [9] - ISPS [9] - PALASM [2] - SLIDE [39] - TEGAS [9] - TI-HDL [9] - Zeus [9]

3.2. Conventions and VHDL Syntax [1, 3, 9, 7] 3.2.1. Lexical Elements, Separators, and Delimiters 3.2.2. Identifiers 3.2.3. Reserved Words 3.2.4. Literals 3.2.5. Syntax Descriptions [3]

- Design File - Library Unit Declarations - Declarations and Specifications - Type Definitions - Concurrent Statements - Sequential Statements - Interfaces and Associations - Expressions

3.2.6. Differences among VHDL-87, VHDL-93 and VHDL-2001 [3, 7]

- Lexical Differences - Syntactic Differences - Semantic Differences - Differences in the Standard Environment - VHDL-93 Facilities Not in VHDL-87 or VHDL-93 - Features under Consideration for Removal

3.3. Utilities for High-Level Descriptions [1, 3, 4, 9] 3.3.1. Type Declarations and Usage [1, 4]

- Object Types Signal

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Variables Constants

- Data Types Scalar Types Composite Types Incomplete Types File Types

- File Type Caveats - Subtypes

3.3.2. Scalar Data Types and Operations [3] - Constants and Variables - Scalar Types - Type Classification - Attributes of Scalar Types - Expressions and Operators

3.3.3. Composite Data Types and Operations [3] - Arrays - Unconstrained Array Types - Array Operations and Referencing - Records

3.3.4. VHDL Operators 3.3.5. Subprogram Parameter Types and Overloading 3.3.6. Other Types and Type-Related Issues 3.3.7. Access Types and Abstract Data Types [3] 3.3.8. Files and Input/Output [3, 7]

- File Types and File I/O - The Package Textio

Textio Read Operations Textio Write Operations

3.3.9. Predefined Attributes [3, 4] - Value Kind Attributes

Value Type Attributes Value Array Attributes Value Block Attributes

- Function Kind Attributes Function Type Attributes Function Array Attributes Function Block Attributes Attributes ‘EVENT and ‘LAST_VALUE Attribute ‘LAST_EVENT Attributes ‘ACTIVE and ‘LAST_ACTIVE

- Signal Kind Attributes Attribute ‘DELAYED

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Attribute ‘STABLE Attribute ‘QUIET Attribute ‘TRANSACTION

- Type Kind Attributes - Range Kind Attributes

3.3.10. User-Defined Attributes 3.3.11. Packaging Basic Utilities

3.4. Design Organization and Parameterization [1, 9] 3.4.1. Definition and Usage of Subprograms [1, 3, 6, 7, 9]

- Subprogram Declaration - Subprogram Body - Subprogram Overloading - Subprogram Return Values and Types - Type Casting and Type Qualification - Procedures - Procedure Parameters - Concurrent Procedure Call Statement - Functions

Conversion Functions [4] Resolution Functions [4, 7]

- Subprogram Overloading [7] - Visibility of Declarations

3.4.2. Packages : Packaging Parts and Use Clauses(Utilities) [1, 3, 6, 7, 9]

- Package Declarations [3, 7] - Package Bodies [3, 7] - Use Clauses [3] - Deferred Constants [4] - The Predefined Package Standard [3]

- IEEE Standard Packages [3] : Standard Package [9] Textio Package [3, 9] Std_Logic 1164 Multivalue Logic System Package [3, 9] Standard VHDL Mathematical Packages [3] Standard VHDL Synthesis [3]

- Basic Utilities Package [9] 3.4.3. Design Components and Configurations [ 3, 9 ]

- Component Declarations - Component Instantiation - Packaging Components - Configuring Component Instances : Architecture

Selection

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- Configuration Specifications (Configuration Statements)

- Power of Configurations 3.4.4. Design Libraries [1, 6, 7, 9] 3.4.5. Design Parameterization : Defining an Entity with

GENERIC Constants [1, 3, 9] - Parameterizing Behavior - Parameterizing Structure

3.5. Concurrent VHDL - Concurrent Assignment Statements [1, 3, 4, 6, 7]

3.5.1. Simple Signal Assignment 3.5.2. Signal Assignment Versus Variable Assignment [4]

- Incorrect Mux Example - Correct Mux Example

3.5.3. Assigning Signal Values Using OTHERS 3.5.4. Selected Signal Assignment 3.5.5. Conditional Signal Assignment 3.5.6. Component Instantiation Statement 3.5.7. Concurrent PROCEDURE CALL Statement 3.5.8. GENERATE Statement [3]

- Generating Iterative Structures - Conditionally Generating Structures. Recursive

Structures - Configuration of Generate Statements

3.6. Sequential VHDL - Sequential Assignment Statements [1, 4, 6, 7] 3.6.1. PROCESS Statement

- Sensitivity List - Process Declarative Region - Process Statement Part - Process Example - Process Execution

3.6.2. BLOCK Statement 3.6.3. IF Statement 3.6.4. CASE Statement 3.6.5. LOOP Statement 3.6.6. NEXT Statement 3.6.7. EXIT Statement 3.6.8. NULL Statement 3.6.9. RETURN Statement

3.6.10. PROCEDURE CALL Statement 3.6.11. ASSERT Statement

- Assertion BNF 3.6.12. WAIT Statement [4]

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- WAIT ON Signal - WAIT UNTIL Expression - WAIT FOR time_expression - Multiple WAIT Conditions - WAIT Time-Out - Sensitivity List Versus WAIT Statement - Concurrent Assignment Problem - Passive Processes

3.7. Structural Specification of Hardware [9] 3.7.1. Parts Library 3.7.2. Wiring of Primitives

- Logic Design of Comparator - VHDL Description of a 4-bit Comparator

3.7.3. Wiring Iterative Networks - Design of a 4-bit Comparator - VHDL Description of a 4-bit Comparator

3.7.4. Binding Alternative 3.7.5. Top-Down Wiring

- Sequential Comparator - Byte Latch - Byte Comparator

3.8. Behavioral Description of Hardware [9] 3.8.1. Process Statement 3.8.2. Assertion Statement 3.8.3. Sequential WAIT Statement 3.8.4. Formatted ASCII I/O Operations 3.8.5. MSI-Based Design 3.9. Dataflow Descriptions in VHDL [9] 3.9.1. Multiplexing and Data Selection

- General Multiplexing - Guards and Blocks [3, 9, 7] Guarded Signal Assignments and Disconnection [3] Guarded Signal and Null Waveform [7] Disconnection Specification [7] Driver Creation [4] Bad Multiple Driver Model [4] Disconnecting from Drivers Resolving between Several Driving Values The Driving Attribute [3] Guarded Ports [3] Guarded Signal Parameters [3] Blocks and Guarded Signal Assignment [3] Block Declarative Part

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Nesting Guarded Block Explicit Guard Signals [3] Disconnection Specifications [3] Using Blocks for Structural Modularity [3] Generics and Ports in Blocks [3] Configuring Designs with Blocks [3]

- MOS Implementation of Multiplexer - A General Multiplexer - Resolving INOUT Signals [3, 9]

3.9.2. State Machine Description [9, 7] - A Sequence Detector - Allowing Multiple Active States - Outputs of Mealy and Moore Machines - A Generic State Machine

3.9.3. Open Collector Gates 3.9.4. Three-State Bussing

- Std_Logic Bussing 3.9.5. A General Dataflow Circuit 3.9.6. Updating Basic Utilities 3.10. VHDL as a Modeling Language [9]

3.10.1.Bi-direction Component Modeling - Load-dependent Timing

- Models for Controlability Observability 3.10.2.Multimode Component Modeling

- Cone Modeling - Cone Modeling Utilities - Cone Gate Models - Simulation and Cone Identification

3.11. Common design errors in VHDL and how to avoid them [6] 3.11.1. Signals and variables 3.11.2. Logic synthesis and sensitivity lists 3.11.3. Buffers and internal dummy signals 3.11.4. Declaring vectors with downto or to

4. NUMBER REPRESENTATION AND ARITHMETIC CIRCUITS 4.1. Addition of Unsigned Numbers 4.1.1. Decomposed Full-Adder 4.1.2. Ripple-Carry Adder 4.1.3. Design Example Using VHDL 4.2. Signed Numbers. Addition and Subtraction 4.2.1. Adder and Subtractor Unit 4.3. Fast Adders 4.4. Multiplication

4.4.1. Array Multiplier for Unsigned Numbers

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4.4.2. Multiplication of Signed Numbers 4.4.3. Vector multiplication. Resource sharing [6] 4.4.3. Design Example Using VHDL

4.5. Design of Arithmetic Circuits Using CAD Tools 4.5.1. Design of Arithmetic Circuits Using Schematic Capture 4.5.2. Design of Arithmetic Circuits Using VHDL 4.5.3. Representation of Numbers in VHDL Code 5. COMBINATIONAL CIRCUITS

5.1. VHDL for Combinational Circuits 5.1.1. Assignment Statement 5.1.2. Selected Signal Assignment 5.1.3. Conditional Signal Assignment 5.1.4. Generate Statement 5.1.5. Concurrent and Sequential Assignment Statements 5.1.6. Process Statement 5.1.7. Case Statement 5.2. Combinatorial Logic [6, 11] 5.2.1. Multiplexors

- 2 to 1 multiplexor [6] - 8 to 1 multiplexor [6]

5.2.2. Decoders - 3 to 8 decoder [6]

5.2.3. Priority Encoders [11] 5.2.3. Parity Generators [11] 5.2.4. Edge-controlled pulse generator [6]

5.2.5. Adders [6] - 1-bit Adder in VHDL [11] - 1-bit Adder with Carry In [6] - 8-bit Adder with Carry In [6] - Generic Adder with Carry In [6] - 4-bit Vector Adder/ Subtractor [6] - Serial Adder Behavioral Description [9] - General Layout of Serial Adder [9] - Structural Description of Serial Adder [9]

5.2.5. LED Decoder in VHDL [11] 5.2.6. Frequency dividers [6] 5.2.7. Filters [6]

- 4-input Digital Majority-Voting Filter - 4-input Digital Addition Filter

5.2.7. Standard MSI 74LS Parts [9] - 74LS85 4-bit Magnitude Comparator - 74LS157 Quadruple 2-Line to 1-Line Multiplexer - 74LS283 4-bit Binary Full Adder

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6. FLIP-FLOPS, REGISTERS, COUNTERS, AND A SIMPLE PROCESSOR 6.1. Using Storage Elements with CAD Tools 6.2. Including Storage Elements in Schematics 6.3. Using Latches and Flip-Flops in VHDL Code [1, 11]

- Flip-flop with Asynchronous Reset [6] - Flip-flop with Synchronous Reset [6] - 8-bit Register with Enable and Asynchronous Reset [6] - 4-bit Shift Register with Serial Input Data and Parallel Output Data [6] - 4-bit Shift Register with Parallel Load and Serial Output [6]

6.4. Using VHDL Sequential Statements for Storage Elements 6.5. Counters [6] 6.5.1. 3-bit Counter with Enable and Carry Out 6.5.2. 3-bit Up/Down Counter 6.6. Design Examples

6.6.1. Standard MSI 74LS Parts [9] - 74LS163 Synchronous 4-bit Counter - 74LS373 Octal D-type Transparent Latches - 74LS377 Octal D-Type Flip-Flops - 74LS299 Universal Shift-Register - 74LS541 Transceiver

7. SYNCHRONOUS SEQUENTIAL CIRCUITS 7.1. Design of Finite State Machines Using CAD Tools [1, 6, 8, 10, 11,

14] 7.1.1. A Simple Design Example [8] 7.1.2. Moore machine [6] 7.1.3. Mealy machine [6, 8] 7.1.4. Mealy and Moore variants [6] 7.1.5. Output = state machine [6] 7.1.6. FSM Flip-Flop Output Signal [7] 7.1.7. State Machines and Clocking Disciplines [13]

- Outputs of Mealy and Moore Machines [9] - Moore machine with clocked outputs [6]

- Mealy machine with clocked outputs [6] 7.1.8. State Machine Design [13]

- Structural Specification of State Machines [13] - State Transition Graphs and Tables [13] - A Sequence Detector [9] - Controller Description(VHDL Description of 110 detector) [9] - Allowing Multiple Active States [9] - A Generic State Machine [9] - State Assignment(State Coding).Residual States [6, 13] - A Behavioral State Machine [9] - Design Validation [13]

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- Sequential Testing [13] - A Simple Design Example [8] - A Memory Controller [8] - Area, Speed, and Device Resource Utilization [8] - Additional Design Consideration [8]

7.1.9. How to write an optimum state machine in VHDL [6] 7.1.9. Asynchronous state machines [6] 7.1.10. VHDL Code for Moore-Type FSMs 7.1.11. Synthesis of VHDL Code . FSM Synthesis [7] 7.1.11. Simulating and Testing the Circuit 7.1.12. An Alternative Style of VHDL Code 7.1.13. Summary of Design Steps When Using CAD Tools 7.1.14. Specifying the State Assignment in VHDL Code 7.1.15. Specification of Mealy FSMs Using VHDL 7.1.16. FSM Initialization [7]

7.2. Serial Adder Example 7.2.1. Mealy-Type FSM for Serial Adder 7.2.2. Moore-Type FSM for Serial Adder 7.2.3. VHDL Code for the Serial Adder 7.3. Algorithmic State Machine (ASM) Charts 7.4. Formal Model for Sequential Circuits 8. DIGITAL SYSTEM DESIGN

8.1. Overview of the Computer Design Problem [5] 8.2. Modular Designs and Hierarchy [11] 8.3. Interface Design and Modeling [9]

8.3.1. System Overview 8.3.2. CPU Timing 8.3.3. Memory Signals 8.3.4. Complete System

8.4. Sharing System Busses [9] 8.4.1. Arbitration Operation 8.4.2. Wait Operation 8.4.3. Arbiter Model 8.5. DMA Devices [9] 8.5.1. Serial Connection 8.5.2. Interface through Arbiter 8.5.3. Interface to CPU 8.5.4. DMA Controller 8.6. CPU Cache [9]

8.6.1. Cache Structure 8.6.2. Cache Interface 8.6.3. Cache Structure Modeling 8.6.4. Controller Modeling

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8.7. ALU Design [5, 7] 8.7.1. Design of Fast Adder/Subtractors 8.7.2. Multiplication and Division

- Vector Multiplication [6] 8.7.3. ALU Design Requirements [7] 8.7.4. Describing ALU with VHDL [7] 8.7.5. Improving the Design [7] 8.7.6. Simulate the Design with a Test Bench [7]

8.8. Memory System Design [5] 8.8.1.Design of Memory Module [5] 8.8.2.Simple and Specialized Memories [11] 8.8.3.RAM and ROM [6]

8.9. Data Path and Control Logic Design [5] 8.9.1.Pseudocode and ASM Chart 8.9.2.Datapath 8.9.3.Detailed ASM Chart 8.9.4.Control Logic Design

8.10. FPGA Implementation [5] 8.10.1.Implementation of the Computer Design 8.10.2.Mapping the Target Computer into the FPGA 8.10.3.Simulation and Testing

8.11. Pipelining [5] 8.11.1.Simple Instruction Pipelines 8.11.2.General Instruction Pipelines 8.11.3.Pipeline Control

8.12. Queuing Networks Design [3] 8.12.1. Queuing Networks Concepts

8.12.2. Queuing Networks Modules - Random Number Generator - A Package for Token and Arc Types - The Token Source Module - The Token Sink Module - The Queue Module - The Token Server Module - The Fork Module - The Join Module

8.12.3. A Queuing Network for a Disk System 8.13. The DLX Computer System 8.14. The GNOME Microcomputer [11]

8.14.1. GNOME in ABEL 8.14.2. GNOME in VHDL

8.15. The DWARF Microcomputer [11] 8.16. CPU Modeling : Parwan VHDL Description [9]

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8.16.1. Definition a Comprehensive Example 8.16.2. Parwan CPU 8.16.3. Behavioral Description of Parwan 8.16.4. Parwan Bussing Structure 8.16.5. Dataflow Description of Parwan 8.16.6. A Test Bench for the Parwan CPU 8.16.7. A More Realistic Parwan 8.16.8. Complete Parwan Behavioral Description 8.16.9. Complete Parwan Dataflow Description

8.16.10.Top-Level Behavioral Synthesizable Description 8.16.11.Component Based Dataflow Synthesizable Description

8.16.12.A Mnemonic-Based Test Bench for Parwan 8.16.13.PLA-Based Parwan Controller

8.17. A Design Project [7] 8.17.1. Design Requirements 8.17.2. Functional VHDL Implementation 8.17.3. VHDL Test Bench 8.17.4. Synthesis and Layout 8.17.5. Layout Back-annotation and Verification 8.17.6. VHDL Partioning

9. TESTING OF LOGIC CIRCUITS 9.1. Fault Model

9.1.1. Stuck-at Model 9.1.2. Single and Multiple Faults

9.1.3. CMOS Circuits 9.2. Complexity of a Test Set 9.3. Path Sensitizing 9.3.1. Detection of Specific Faults 9.4. Circuits with Tree Structure 9.5. Random Tests 9.6. Testing of Sequential Circuits

9.6.1.Design for Testability 9.7. Built-in-Self-Test

9.7.1. Built-in Logic Block Observer 9.7.2. Signature Analysis

9.7.3. Scan Methodology [6] - Full Scan and Partial Scan [6] - ATPG Design Rules: How to write testable VHDL

code [6] 9.7.4.Boundary Scan [6] 9.7.5.Supplementary test vectors [6]

9.8. Printed Circuit Boards 9.8.1. Testing of PCBs

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9.8.2. Instrumentation 10. WRITING VHDL FOR SYNTHESIS 10.1. General Guidelines of VHDL Synthesis 10.2. Writing VHDL to Infer Flip-Flops

10.3. Writing VHDL to Infer Latches 10.4. Writing VHDL to Infer Tristate Buffers 10.5. Writing VHDL to Generate Combinational Circuits 10.6. Putting Them Together 10.7. Simulation versus Synthesis Differences 10.8. Think About Hardware 10.9. Use of Subprogram

10.10. Synthesis Process

CAD Tools

ModelSim XE/Starter 5.5b (Model Technology Inc) MAX + plus II ver.9.23 (Altera Corporation) OrCAD 9.2 VHDL Simili Shell 1.5 ViewLogic Autologic 2 Synopsys synthesis tool Mentor Graphics VHDL Simulator Active-HDL ver.4.0 XE (ALDEC) CUPL/PAL expert Package (Logical Devices, Inc) (CUPL – Universal Compiler for Programmable Logic (Logical Devices, Inc)

Laboratories “Hands on” for ViewLogic [6] - Lab1:Design, Simulate and Synthesize a Simple Component - Start the development system - Enter VHDL code - Verify the component - Synthesize the component

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“Hands on” for Synopsys synthesis tool and Mentor Graphics VHDL Simulator [6] - Lab1:Design, Simulate and Synthesize a Simple Component - Start the development system - Enter VHDL code - Simulate the component - Synthesize the component Script for Synopsys users Laboratory Assignments [6] - Lab1. Design, Simulate and Synthesize a Simple Component - Lab2. Parallel VHDL - Lab3. Sequential VHDL - Lab4. Subprogram - Lab5. Structural VHDL - Lab6. State machines - Lab7. A complete design example - Lab8. Controlling a stepping motor

Suggested LAB Projects [5]

Lab Equipment Usage and the 74LS181ALU Combinational Logic Design Using an EPROM Combinational Logic Design Using a GAL Sequential Logic Design Using an EPROM

FPGA Software Usage FPGA Configuration Using the Parallel Port ASM Design Computer Project: ALU Module Computer Project: Memory Module Computer Project: Register Module Computer Project: Control Module Integrate Entire Computer

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24. S.Palnitkar Verilog HDL. A Guide to Digital Design and Synthesis.- SunSoft Press, 1996. 25. J.M.Lee Verilog QuickStart.- Kluwer Academic Publishers, 1997. 26. IEEE Design Automation Standards Committee (1991). IEEE Standards Interpreta- tions: IEEE Standard 1076-1987. IEEE, New York. 27. IEEE Design Automation Standards Committee (1993a). IEEE Standard VHDL Language Reference Manual (ANSI): IEEE Std 1076-1993 . IEEE, New York. 28. IEEE Design Automation Standards Committee (1993b). IEEE Standard Multivalue Logic System for VHDL Model Interoperability (Std_logic_1164) (ANSI): IEEE Standard 1164-1993 . IEEE, New York. 29. IEEE Design Automation Standards Committee (1997). IEEE Standard VHDL Synthesis Packages. IEEE, New York. 30. IEEE. IEEE Standard Test Access Port and Boundary-Scan Architecture, IEEE Press, New York, 1993. 31. CFI Standards for Electronic Design Automation Release 1.0. 1992. 32. EDIF is maintained by the EIA, EIA Standards Sales Office, 2001 Pennsylvania Ave., N.W., Washington, DC 20006, (202) 457- 4966. – 355p. 33. EXPRESS Language Reference Manual. ISO TC184/SC4/WG5 Document N14, March 29, 1991.- 370p. 34. Lala P.K. Digital Circuit Testing and Testability.- Academic Press, 1997. 35. Coelho D.R. The VHDL Handbook.- Kluwer Academic, Norwell, MA, 1989. 36. Lipsett R., Schaefer C., Ussery C. VHDL: Hardware Description and Design.- Kluwer Academic, Norwell, MA, 1989. 37. Hill D.D. ADLIB: A modular, strongly-typed computer design language.- Proc. of the 4th International Symposium on Computer Hardware Description Language, IEEE, 1979. 38. Lengauer T., Melhorn K. The HILL System: A design environment for the hierarchical specification, compaction and simulation of integrated circuit layout.- Proceedings MIT Conference on Advanced Research in VLSI, Artech House Company, 1984. 39. Parker A., Wallace J. SLIDE, an I/O Hardware Description Language.- IEEE Transactions on Computers, vol. C-30, 1981. 40. Piloty R., Barbacci M., Borrione D. etc. CONLAN Report.- Springer-Verlag, 1983. 41. Actel FPGA Data Book and Design Guide.- Actel Corp.,1995. 42. Xilinx. The Programmable Logic. Data Book.- San Jose: Xilinx,Inc., 1999. 43. ORCAD Capture for Windows. User’s Guide.- Oregon: OrCAD,Inc., 1998. 44. ORCAD Express for Windows. User’s Guide.- Oregon: OrCAD,Inc., 1998. 45. IEEE Standard 1076-2001. IEEE Standard VHDL Language Reference Manual. 46. IEEE Standard 1076.1-1999. IEEE Standard VHDL Analog and Mixed-Signal Extensions. 47. IEEE Standard 1076.2-1996. IEEE Standard VHDL Mathematical Packages. 48. IEEE Standard 1076.4-1995. IEEE Standard VITAL Application-Specific

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Integrated Circuit (ASIC) Modeling Specification. 49. IEEE 1076.6-1999. IEEE Standard for VHDL Register Transfer Level (RTL) Synthesis. 50. IEEE Standard 1029.1-1998. IEEE Standard for VHDL Waveform and Vector Exchange to Support Design and Test Verification (WAVES) Language Reference Manual. 51. IEEE Standard 1364-1995. IEEE Standard Description Language Based on the Verilog Hardware Description Language. 52. IEEE Standard 1499-1998. IEEE Standard Interface for Hardware Description Models of Electronic Components. 53. IEEE Standard 1481-1999. IEEE Standard for Delay and Power Calculation. 54. Bhasker J. A VHDL Primer (3rd Edition). - Prentice Hall PTR Upper Saddle River, NJ 07458, 1999. 55. Baker L. VHDL Programming with Advanced Topics. - John Wiley and Sons, Inc., 1993. 56. Berge J.-M. et al., VHDL Designer’s Reference. – Kluwer Academic, 1992. 57. Berge J.-M. et al., VHDL’92. – Kluwer Academic, 1993. 58. Leung. ASIC System Design with VHDL.- Boston: Kluwer Academic, 1989. 59. Schoen J.M. Performance and Fault Modeling with VHDL. - Englewood Cliffs, NJ: Prentice Hall, 1988. Internet Resources

www.eda.org/vasg The VHDL Analysis and Standartization Group (VASG) www.eda.org/vhdlpli The VHDL PLI(Programming Language Interface) Task Force www.eda.org/libuti The IEEE P1076.5 VHDL Utility Library Working Group www.eda.org/oovhdl The IEEE P1577 Object-Oriented VHDL Working Group www.eda.org/std The IEEE P1551 System and Interface Description Working Group www.eda.org/vlog-synth/ The IEEE P1364.1 Verilog Synthesis Interoperability Working Group www.eda.org/verilog-ams/ The Verilog-AMS Technical Subcommittee of OVI (Open Verilog International) www.inmet.com/SLDL/ The System Level Design Language(SLDL) Initiative www.ittc.ukans.edu/Projects/SLDG/rosetta/ The SLDL Initiative www.vhdl.org/dcwg/ The OVI Design Constraints Working Group www.vsi.org The Virtual Socket Interface Alliance(VSIA) www.eda.org/sdf The IEEE P1497 Standard Delay Format www.eda.org/alf/ The OVI Advanced Library Format www.si2.org/ola/ The SI2 Open Library Architecture www.si2.org/CHDStd/ The Chip Hierarchical Design System Technical Data Standart (CHDStd) program www.edif.org/ The EIA-682 Electronic Design Interchange Format (EDIF)

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www.edif.org/lpmweb/ The EIA/IS-103 Library of Parameterized Modules(LPM) erm1.u-strasbg.fr/db ftp.amd.com/pub/pld/software/palasm – AMD opensource.ethz.ch/emacs/vhdl-mode.html poppy.snu.ac.kr/VDT rassp.aticorp.org/vhdl rassp.scra.org/vhdl sirio.dit.upm.es/~cdk/inv/euroform/set-vhdl.html splish.ee.byu.edu/tutorials/altera/altera.html standard.ieee.org tech-www.informatik.uni-hamburg.de/vhdl/vhdl.html – The Hamburg VHDL Archive wuarchive.wustl.edu/languages/vhdl www.acc-eda.com/vhdlref www.aldec.com www.altera.com – Altera Corporation www.atmel.com/pub/atmel - Atmel www.arccores.com www.ashenden.com.au www.atl.external.lmco.com/rassp/taxon/rassp_taxon.html www.atl.external.lmco.com/rassp/vgui www.bluepc.com www.capilano.com – Capilano Computing ( DesignWorks, MacABEL) www.cfi.org – CFI www.cs.man.ac.uk/cad – The EDIF Technical Center at the University of Manchester www.cs.ucr.edu/~dalton/i8051 www.data-io.com - home page for Data I/O Corp.(holds the trademark for ABEL) www.doulos.co.uk www.ececs.uc.edu/~paw/savant www.ecsi.org/EARNEST/digests/VHDL_cookbook www.edif.org/edif/workshop.edf – EDIF www.edif.org/lpmweb/more www.ee.byu.edu/ee/class/ee220/abel – a lot of useful information on ABEL www.ee.byu.edu/ee/class/ee220/palasm – a lot of useful information on PALASM www.ee.duke.edu/Research/VHDL_tutorial www.eej.ulst.ac.uk/tutor.html www.eej.ulst.ac.uk/tutor/vhdnotes.notes.html www.eng.auburn.edu/department/cse/research/grasp/grasp_main.shtml www.eng.auburn.edu/department/ee/mgc/vhdl.html www.erc.msstate.edu/~reese/vhdl_synthesis www.erols.com/aaps/x84lab www.estec.esa.nl/wsmwww/leon www.freehdl.seul.org www.gmvhdl.com/VHDL.html

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www.gtcdrom.com www.hamster-ams.com www.iis.ee.ethz.ch/~zimmi/arith_lib.html www.intrinsix.com www.isdmag.com/ic-logic/ABEL/ABEL.html www.mhhe.com/engcs/electrical/brownvranesic/ www.mindspring.com/~tcoonan www.model.com www.optimagic.com/newsgroups.html www.optimagic.com/tutorials.html www.protel.com - Protel www.protel.com/download.htm www.regent.e-technik.tu-muenchen.de/forschung/vhdl www.semichips.org – Semiconductor Industry Association www.symphonyeda.com/products.htm www.syncad.com www.synopsys.com www.synthworks.com www.syssim.ecs.soton.ac.uk www.tetraedre.com www.tkt.cs.tut.fi/~havu/pci/models.html www.v3logic.com www.vhdl.com – VHDL Technology Group www.vhdl.org/comp.lang.vhdl www.vhdl.org/vital – The VITAL packages www.vhdl.org/vhdl_intl – VHDL International www.vhdl-online.de/~vhdl/TUTORIAL www.viewlogic.com – The Viewlogic home page www.v-ms.com www.xilinx.com – Xilinx Corporation www.yordas.demon.co.uk/crypto