# Lecture 4: DC & Transient Response - · PDF fileIntroduction to CMOS VLSI Design Lecture 4: DC & Transient Response David Harris Harvey Mudd College Spring 2004

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• Introduction toCMOS VLSI

Design

Lecture 4: DC & Transient Response

David Harris

Harvey Mudd CollegeSpring 2004

• 4: DC and Transient Response Slide 2CMOS VLSI Design

Outlineq DC Responseq Logic Levels and Noise Marginsq Transient Responseq Delay Estimation

• 4: DC and Transient Response Slide 3CMOS VLSI Design

Activity1) If the width of a transistor increases, the current willincrease decrease not change

2) If the length of a transistor increases, the current willincrease decrease not change

3) If the supply voltage of a chip increases, the maximum transistor current will

increase decrease not change4) If the width of a transistor increases, its gate capacitance willincrease decrease not change

5) If the length of a transistor increases, its gate capacitance willincrease decrease not change

6) If the supply voltage of a chip increases, the gate capacitance of each transistor will

increase decrease not change

• 4: DC and Transient Response Slide 4CMOS VLSI Design

Activity1) If the width of a transistor increases, the current willincrease decrease not change

2) If the length of a transistor increases, the current willincrease decrease not change

3) If the supply voltage of a chip increases, the maximum transistor current will

increase decrease not change4) If the width of a transistor increases, its gate capacitance willincrease decrease not change

5) If the length of a transistor increases, its gate capacitance willincrease decrease not change

6) If the supply voltage of a chip increases, the gate capacitance of each transistor will

increase decrease not change

• 4: DC and Transient Response Slide 5CMOS VLSI Design

DC Responseq DC Response: Vout vs. Vin for a gateq Ex: Inverter

When Vin = 0 -> Vout = VDD When Vin = VDD -> Vout = 0 In between, Vout depends on

transistor size and current By KCL, must settle such that

Idsn = |Idsp| We could solve equations But graphical solution gives more insight

Idsn

Idsp Vout

VDD

Vin

• 4: DC and Transient Response Slide 6CMOS VLSI Design

Transistor Operationq Current depends on region of transistor behaviorq For what Vin and Vout are nMOS and pMOS in

Cutoff? Linear? Saturation?

• 4: DC and Transient Response Slide 7CMOS VLSI Design

nMOS Operation

Vgsn >

Vdsn >

Vgsn >

Vdsn Vgsn Vtn

Vgsn > Vtn

Vdsn < Vgsn Vtn

Vgsn < Vtn

SaturatedLinearCutoff

Idsn

Idsp Vout

VDD

Vin

• 4: DC and Transient Response Slide 9CMOS VLSI Design

nMOS Operation

Vgsn > Vtn

Vdsn > Vgsn Vtn

Vgsn > Vtn

Vdsn < Vgsn Vtn

Vgsn < Vtn

SaturatedLinearCutoff

Idsn

Idsp Vout

VDD

VinVgsn = Vin

Vdsn = Vout

• 4: DC and Transient Response Slide 10CMOS VLSI Design

nMOS Operation

Vgsn > VtnVin > VtnVdsn > Vgsn VtnVout > Vin - Vtn

Vgsn > VtnVin > VtnVdsn < Vgsn VtnVout < Vin - Vtn

Vgsn < VtnVin < Vtn

SaturatedLinearCutoff

Idsn

Idsp Vout

VDD

VinVgsn = Vin

Vdsn = Vout

• 4: DC and Transient Response Slide 11CMOS VLSI Design

pMOS Operation

Vgsp Vgsp Vtp

Vgsp > Vtp

SaturatedLinearCutoff

Idsn

Idsp Vout

VDD

Vin

• 4: DC and Transient Response Slide 13CMOS VLSI Design

pMOS Operation

Vgsp < Vtp

Vdsp < Vgsp Vtp

Vgsp < Vtp

Vdsp > Vgsp Vtp

Vgsp > Vtp

SaturatedLinearCutoff

Idsn

Idsp Vout

VDD

VinVgsp = Vin - VDD

Vdsp = Vout - VDD

Vtp < 0

• 4: DC and Transient Response Slide 14CMOS VLSI Design

pMOS Operation

Vgsp < VtpVin < VDD + VtpVdsp < Vgsp VtpVout < Vin - Vtp

Vgsp < VtpVin < VDD + VtpVdsp > Vgsp VtpVout > Vin - Vtp

Vgsp > VtpVin > VDD + Vtp

SaturatedLinearCutoff

Idsn

Idsp Vout

VDD

VinVgsp = Vin - VDD

Vdsp = Vout - VDD

Vtp < 0

• 4: DC and Transient Response Slide 15CMOS VLSI Design

I-V Characteristicsq Make pMOS is wider than nMOS such that n = p

Vgsn5

Vgsn4

Vgsn3

Vgsn2Vgsn1

Vgsp5

Vgsp4

Vgsp3

Vgsp2

Vgsp1VDD

-VDD

Vdsn

-Vdsp

-Idsp

Idsn

0

• 4: DC and Transient Response Slide 16CMOS VLSI Design

Current vs. Vout, Vin

Vin5

Vin4

Vin3

Vin2Vin1

Vin0

Vin1

Vin2

Vin3Vin4

Idsn, |Idsp|

VoutVDD

• 4: DC and Transient Response Slide 17CMOS VLSI Design

Vin5

Vin4

Vin3

Vin2Vin1

Vin0

Vin1

Vin2

Vin3Vin4

Idsn, |Idsp|

VoutVDD

q For a given Vin: Plot Idsn, Idsp vs. Vout Vout must be where |currents| are equal in

Idsn

Idsp Vout

VDD

Vin

• 4: DC and Transient Response Slide 18CMOS VLSI Design

Vin0

Vin0

Idsn, |Idsp|

VoutVDD

q Vin = 0

• 4: DC and Transient Response Slide 19CMOS VLSI Design

Vin1

Vin1Idsn, |Idsp|

VoutVDD

q Vin = 0.2VDD

• 4: DC and Transient Response Slide 20CMOS VLSI Design

Vin2

Vin2

Idsn, |Idsp|

VoutVDD

q Vin = 0.4VDD

• 4: DC and Transient Response Slide 21CMOS VLSI Design

Vin3

Vin3

Idsn, |Idsp|

VoutVDD

q Vin = 0.6VDD

• 4: DC and Transient Response Slide 22CMOS VLSI Design

Vin4

Vin4

Idsn, |Idsp|

VoutVDD

q Vin = 0.8VDD

• 4: DC and Transient Response Slide 23CMOS VLSI Design

Vin5Vin0

Vin1

Vin2

Vin3Vin4

Idsn, |Idsp|

VoutVDD

q Vin = VDD

• 4: DC and Transient Response Slide 24CMOS VLSI Design

Vin5

Vin4

Vin3

Vin2Vin1

Vin0

Vin1

Vin2

Vin3Vin4

Idsn, |Idsp|

VoutVDD

• 4: DC and Transient Response Slide 25CMOS VLSI Design

DC Transfer Curveq Transcribe points onto Vin vs. Vout plot

Vin5

Vin4

Vin3

Vin2Vin1

Vin0

Vin1

Vin2

Vin3Vin4

VoutVDD

CVout

0

Vin

VDD

VDDA B

DE

Vtn VDD/2 VDD+Vtp

• 4: DC and Transient Response Slide 26CMOS VLSI Design

Operating Regionsq Revisit transistor operating regions

CVout

0

Vin

VDD

VDDA B

DE

Vtn VDD/2 VDD+VtpE

D

C

B

A

pMOSnMOSRegion

• 4: DC and Transient Response Slide 27CMOS VLSI Design

Operating Regionsq Revisit transistor operating regions

CVout

0

Vin

VDD

VDDA B

DE

Vtn VDD/2 VDD+VtpCutoffLinearE

SaturationLinearD

SaturationSaturationC

LinearSaturationB

LinearCutoffA

pMOSnMOSRegion

• 4: DC and Transient Response Slide 28CMOS VLSI Design

Beta Ratioq If p / n 1, switching point will move from VDD/2q Called skewed gateq Other gates: collapse into equivalent inverter

Vout

0

VinVDD

VDD

0.51

2

10pn

=

0.1pn

=

• 4: DC and Transient Response Slide 29CMOS VLSI Design

Noise Marginsq How much noise can a gate input see before it does

not recognize the input?

IndeterminateRegion

NML

NMH

Input CharacteristicsOutput Characteristics

VOH

VDD

VOL

GND

VIH

VIL

Logical HighInput Range

Logical LowInput Range

Logical HighOutput Range

Logical LowOutput Range

• 4: DC and Transient Response Slide 30CMOS VLSI Design

Logic Levelsq To maximize noise margins, select logic levels at

VDD

Vin

Vout

VDD

p/n > 1

Vin Vout

0

• 4: DC and Transient Response Slide 31CMOS VLSI Design

Logic Levelsq To maximize noise margins, select logic levels at

unity gain point of DC transfer characteristic

VDD

Vin

Vout

VOH

VDD

VOL

VIL VIHVtn

Unity Gain PointsSlope = -1

VDD-|Vtp|

p/n > 1

Vin Vout

0

• 4: DC and Transient Response Slide 32CMOS VLSI Design

Transient Responseq DC analysis tells us Vout if Vin is constantq Transient analysis tells us Vout(t) if Vin(t) changes

Requires solving differential equationsq Input is usually considered to be a step or ramp

From 0 to VDD or vice versa

• 4: DC and Transient Response Slide 33CMOS VLSI Design

Inverter Step Responseq Ex: find step response of inverter driving load cap

0( )(

)

)

(o

i

ut

n

out

V t tt

Vt

V

dd

t

=< =

=

Idsn(t)

• 4: DC and Transient Response Slide 34CMOS VLSI Design

Inverter Step Responseq Ex: find step response of inverter driving load cap

0

0

( )

( )

( )

( )

ou

DDin

t

out

u t t V

dd

t

t t

V t

V

V

t

==

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