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Lecture 4: DC and Transient Analysis

•  DC Analysis •  Skewed Gates •  Logic Levels and Noise Margins •  Transient Response •  Delay Estimation

•  Reading: Ch. 2

Load Line Analysis •  For a given Vin:

–  Plot Idsn, Idsp vs. Vout

–  Vout must be where |currents| are equal in

Region nMOS pMOS A B C D E Idsn

Idsp Vout

VDD

VinI dsn , | I dsp | NMOS PMOS

V in5

V in4 V in3 V in2 V in1

V in0

V in1 V in2 V in3 V in4

V out V DD

CVout

0

VinVDD

VDDA B

DE

Vtn VDD/2 VDD+Vtp

2

Beta Ratio •  If βp / βn ≠ 1, switching point will move from VDD/2 •  Called skewed gate

–  HI-skew –  LO-skew

•  Other gates: collapse into equivalent inverter •  VTC depends on how inputs are applied

V DD

A out

W

2W A

B

out 2W

2W 2W

2W

V DD

EX: 2-Nand sized for similar WC delay as INV

V out

0

V in V DD

V DD

VTC of complex gates •  Case 1: one input held HI while other input is switched from Lo-to-HI

–  Assume PMOS device is removed from circuit (Open circuit since it is CUTOFF) –  Assume NMOS is short circuit (Since LIN with small ON resistance)

•  Equivalent to inverter with 2W Pull-up and 2W Pull-down –  VTC shifts to the LEFT (stronger Pull-down)

A=VDD

B=0→VDD out

2W

2W 2W

2W

V DD

V out

0

V in V DD

V DD

βn / βp = 1

3

VTC of complex gates •  Case 2: both inputs are switched from Lo-to-HI •  Equivalent to inverter with 4W Pull-up and W Pull-down

–  VTC shifts to the RIGHT (stronger Pull-up)

B=0→VDD

out 2W

2W 2W

2W

V DD

V out

0

V in V DD

V DD

βn / βp = 1 A=0→VDD

VTC of complex gates •  Case 1: Assume A=0 and B=0→VDD

–  PMOS short circuit (small RON) –  NMOS open circuit

•  Equivalent to inverter with 4W Pull-up and W Pull-down –  VTC shifts to the RIGHT (stronger Pull-up)

B=0→VDD

V out

0

V in V DD

V DD

βn / βp = 1 A=0

Y

4W

4W

W W

4

VTC of complex gates •  Case 2: Assume A=0→VDD and B=0→VDD •  Equivalent to inverter with 2W Pull-up and 2W Pull-down

–  VTC shifts to the LEFT (stronger Pull-down)

B=0→VDD V out

0

V in V DD

V DD

βn / βp = 1

Y

4W

4W

W W

A=0→VDD

Duty Cycle Distortion

•  How do Skewed gates effect duty-cycle? •  Where is this relevant?

V out

0

V in V DD

V DD

βn / βp = 1

V TRIP1 V TRIP2

V in V out

50% duty cycle

Duty cycle increases

50% duty cycle clock is preferred for increased timing margin

5

Noise Margins

•  How much noise can a gate input see before it does not recognize the input? –  NMH=VOHmin-VIHmin

–  NML=VIHmax-VOLmax

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Indeterminate Region

Input Characteristics Output Characteristics

V OH

V DD

V OL

GND

V IH V IL

Logical High Input Range

Logical Low Input Range

Logical High Output Range

Logical Low Output Range

Logic Levels

•  To maximize noise margins, select logic levels at –  unity gain point of DC transfer characteristic

VDD

Vin

Vout

VOH

VDD

VOL

VIL VIHVtn

Unity Gain PointsSlope = -1

VDD-|Vtp|

βp/βn > 1

Vin Vout

0

6

Tradeoff between NMH and NML

•  Increasing NMH decreases NML

VOH1

VOL1

VIL1 VIH1

VIL2

VIH2

VOL2 VOH2

VOUT1

VIN1

VIN2

VOUT2

Delay Definitions •  tpdr (tpLH): rising propagation delay

–  From input 50% to rising output 50% crossing •  tpdf (tpHL): falling propagation delay (tpHL)

–  From input 50% to falling output 50% crossing •  tpd: average propagation delay

–  tpd = (tpdr + tpdf)/2

•  tcdr: rising contamination delay –  Minimum time from input 50% crossing to rising output crossing VDD/2

•  tcdf: falling contamination delay –  Minimum time from input 50% crossing to falling output crossing VDD/2

•  tcd: average contamination delay –  tpd = (tcdr + tcdf)/2

•  tr: rise time (From output crossing 0.2 VDD to 0.8 VDD •  tf: fall time (From output crossing 0.8 VDD to 0.2 VDD) tmin

tmax

t pHL t pLH t

t

V in

V out

50%

50%

t r 20%

80%

t f

7

Delay Estimation •  SPICE simulator solves the equations

numerically –  Solving differential equations by hand is too hard –  We would like to be able to easily estimate delay

•  Use RC delay models to estimate delay –  C = total capacitance on output node –  Use effective resistance R –  So that tpd = RC

•  Characterize transistors by finding their effective R –  Depends on average current as gate switches

(V)

0.0

0.5

1.0

1.5

2.0

t(s)0.0 200p 400p 600p 800p 1n

tpdf = 66ps tpdr = 83psVin Vout

• The step response usually looks like a 1st order RC response with a decaying exponential.

RC Delay Approximation

•  Use equivalent circuits for MOS transistors –  Ideal switch + capacitance and ON resistance –  Unit nMOS has resistance R, capacitance C –  Unit pMOS has resistance 2R, capacitance C

•  Capacitance proportional to width •  Resistance inversely proportional to width

kgs

dg

s

d

kCkC

kCR/k

kgs

dg

s

d

kC

kC

kC

2R/k

8

Capacitance

•  Cg = (εox/tox)WLmin

•  tox and Lmin are both scaled

•  Cg~2fF/um across technologies

•  Assume C~Cg~Cs ~Cd~2fF/um

n+ n+ p-type body

W

L t ox

SiO 2 gate oxide ε ox = 3.9 ε 0

polysilicon gate

The image

On Resistance

•  250nm process –  Rn~4kΩµm –  Rp~8.9kΩµm –  Rp>Rn since µn>

µp

Reqn= Rn Wn

Reqp= Rp Wp

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Inverter Delay Estimation •  Estimate delay of FO1 inverter

C

CR

2C

2C

R

2

1A

Y

C

2C

C

2C

C

2C

RY

2

1

Example: 3-input NAND

•  Sketch a 3-input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R). Assume Rp=2Rn.

10

3-input NAND Caps •  Annotate the 3-input NAND gate with gate and diffusion

capacitance.

2 2 2

3

3

33C

3C

3C

3C

2C

2C

2C

2C

2C

2C

3C

3C

3C

2C 2C 2C

Elmore Delay •  ON transistors look like

resistors •  Pullup or pulldown network

modeled as RC ladder •  Elmore delay of RC ladder

R1 R2 R3 RN

C1 C2 C3 CN

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Example: 2-input NAND

•  Estimate rising and falling propagation delays of a 2-input NAND driving h identical gates.

h copies

2

2

2 2

B

A x

Y

Example: 2-input NAND

•  Estimate rising and falling propagation delays of a 2-input NAND driving h identical gates.

h copies

2

2

2 2

B

A x

Y

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Delay Components

•  Delay has two parts –  Parasitic delay

–  Effort delay

Contamination Delay

•  Best-case (contamination) delay can be substantially less than propagation delay.

•  Ex: If both inputs fall simultaneously

6C

2C2

2

224hC

B

Ax

Y

13

Pin Reordering •  A and B transition High

–  If A arrives earlier than B

6C

2C2

2

224hC

B

Ax

Y

Diffusion Capacitance •  We assumed contacted diffusion on every s / d. •  Good layout minimizes diffusion area •  Ex: NAND3 layout shares one diffusion contact

3C

2C 2C

3C 3C

Isolated Contacted Diffusion Merged

Uncontacted Diffusion

Shared Contacted Diffusion

3

3

3

2 2 2

AVDD

GND

B

Y

AVDD

GND

B

Y

Which Layout is better?