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CMOS VLSI Design4: DC and Transient ResponseSlide 1 EE466: VLSI Design Lecture 05: DC and transient response – CMOS Inverters

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  • Slide 1
  • CMOS VLSI Design4: DC and Transient ResponseSlide 1 EE466: VLSI Design Lecture 05: DC and transient response CMOS Inverters
  • Slide 2
  • CMOS VLSI Design4: DC and Transient ResponseSlide 2 Outline DC Response Logic Levels and Noise Margins Transient Response Delay Estimation
  • Slide 3
  • CMOS VLSI Design4: DC and Transient ResponseSlide 3 Activity 1) If the width of a transistor increases, the current will increasedecreasenot change 2) If the length of a transistor increases, the current will increasedecreasenot change 3) If the supply voltage of a chip increases, the maximum transistor current will increasedecreasenot change 4) If the width of a transistor increases, its gate capacitance will increasedecreasenot change 5) If the length of a transistor increases, its gate capacitance will increasedecreasenot change 6) If the supply voltage of a chip increases, the gate capacitance of each transistor will increasedecreasenot change
  • Slide 4
  • CMOS VLSI Design4: DC and Transient ResponseSlide 4 Activity 1) If the width of a transistor increases, the current will increasedecreasenot change 2) If the length of a transistor increases, the current will increasedecreasenot change 3) If the supply voltage of a chip increases, the maximum transistor current will increasedecreasenot change 4) If the width of a transistor increases, its gate capacitance will increasedecreasenot change 5) If the length of a transistor increases, its gate capacitance will increasedecreasenot change 6) If the supply voltage of a chip increases, the gate capacitance of each transistor will increasedecreasenot change
  • Slide 5
  • CMOS VLSI Design4: DC and Transient ResponseSlide 5 DC Response DC Response: V out vs. V in for a gate Ex: Inverter When V in = 0 -> V out = V DD When V in = V DD -> V out = 0 In between, V out depends on transistor size and current By KCL, must settle such that I dsn = |I dsp | We could solve equations But graphical solution gives more insight
  • Slide 6
  • CMOS VLSI Design4: DC and Transient ResponseSlide 6 Transistor Operation Current depends on region of transistor behavior For what V in and V out are nMOS and pMOS in Cutoff? Linear? Saturation?
  • Slide 7
  • CMOS VLSI Design4: DC and Transient ResponseSlide 7 nMOS Operation CutoffLinearSaturated V gsn V dsn < V gsn > V dsn >
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  • CMOS VLSI Design4: DC and Transient ResponseSlide 8 nMOS Operation CutoffLinearSaturated V gsn < V tn V gsn > V tn V dsn < V gsn V tn V gsn > V tn V dsn > V gsn V tn
  • Slide 9
  • CMOS VLSI Design4: DC and Transient ResponseSlide 9 nMOS Operation CutoffLinearSaturated V gsn < V tn V gsn > V tn V dsn < V gsn V tn V gsn > V tn V dsn > V gsn V tn V gsn = V in V dsn = V out
  • Slide 10
  • CMOS VLSI Design4: DC and Transient ResponseSlide 10 nMOS Operation CutoffLinearSaturated V gsn < V tn V in < V tn V gsn > V tn V in > V tn V dsn < V gsn V tn V out < V in - V tn V gsn > V tn V in > V tn V dsn > V gsn V tn V out > V in - V tn V gsn = V in V dsn = V out
  • Slide 11
  • CMOS VLSI Design4: DC and Transient ResponseSlide 11 pMOS Operation CutoffLinearSaturated V gsp >V gsp < V dsp > V gsp < V dsp
  • CMOS VLSI Design4: DC and Transient ResponseSlide 12 pMOS Operation CutoffLinearSaturated V gsp > V tp V gsp < V tp V dsp > V gsp V tp V gsp < V tp V dsp < V gsp V tp
  • Slide 13
  • CMOS VLSI Design4: DC and Transient ResponseSlide 13 pMOS Operation CutoffLinearSaturated V gsp > V tp V gsp < V tp V dsp > V gsp V tp V gsp < V tp V dsp < V gsp V tp V gsp = V in - V DD V dsp = V out - V DD V tp < 0
  • Slide 14
  • CMOS VLSI Design4: DC and Transient ResponseSlide 14 pMOS Operation CutoffLinearSaturated V gsp > V tp V in > V DD + V tp V gsp < V tp V in < V DD + V tp V dsp > V gsp V tp V out > V in - V tp V gsp < V tp V in < V DD + V tp V dsp < V gsp V tp V out < V in - V tp V gsp = V in - V DD V dsp = V out - V DD V tp < 0
  • Slide 15
  • CMOS VLSI Design4: DC and Transient ResponseSlide 15 I-V Characteristics Make pMOS is wider than nMOS such that n = p
  • Slide 16
  • CMOS VLSI Design4: DC and Transient ResponseSlide 16 Current vs. V out, V in
  • Slide 17
  • CMOS VLSI Design4: DC and Transient ResponseSlide 17 Load Line Analysis For a given V in : Plot I dsn, I dsp vs. V out V out must be where |currents| are equal in
  • Slide 18
  • CMOS VLSI Design4: DC and Transient ResponseSlide 18 Load Line Analysis V in = 0
  • Slide 19
  • CMOS VLSI Design4: DC and Transient ResponseSlide 19 Load Line Analysis V in = 0.2V DD
  • Slide 20
  • CMOS VLSI Design4: DC and Transient ResponseSlide 20 Load Line Analysis V in = 0.4V DD
  • Slide 21
  • CMOS VLSI Design4: DC and Transient ResponseSlide 21 Load Line Analysis V in = 0.6V DD
  • Slide 22
  • CMOS VLSI Design4: DC and Transient ResponseSlide 22 Load Line Analysis V in = 0.8V DD
  • Slide 23
  • CMOS VLSI Design4: DC and Transient ResponseSlide 23 Load Line Analysis V in = V DD
  • Slide 24
  • CMOS VLSI Design4: DC and Transient ResponseSlide 24 Load Line Summary
  • Slide 25
  • CMOS VLSI Design4: DC and Transient ResponseSlide 25 DC Transfer Curve Transcribe points onto V in vs. V out plot
  • Slide 26
  • CMOS VLSI Design4: DC and Transient ResponseSlide 26 Operating Regions Revisit transistor operating regions RegionnMOSpMOS A B C D E
  • Slide 27
  • CMOS VLSI Design4: DC and Transient ResponseSlide 27 Operating Regions Revisit transistor operating regions RegionnMOSpMOS ACutoffLinear BSaturationLinear CSaturation DLinearSaturation ELinearCutoff
  • Slide 28
  • CMOS VLSI Design4: DC and Transient ResponseSlide 28 Beta Ratio If p / n 1, switching point will move from V DD /2 Called skewed gate Other gates: collapse into equivalent inverter
  • Slide 29
  • CMOS VLSI Design4: DC and Transient ResponseSlide 29 Noise Margins How much noise can a gate input see before it does not recognize the input?
  • Slide 30
  • CMOS VLSI Design4: DC and Transient ResponseSlide 30 Logic Levels To maximize noise margins, select logic levels at
  • Slide 31
  • CMOS VLSI Design4: DC and Transient ResponseSlide 31 Logic Levels To maximize noise margins, select logic levels at unity gain point of DC transfer characteristic
  • Slide 32
  • CMOS VLSI Design4: DC and Transient ResponseSlide 32 Transient Response DC analysis tells us V out if V in is constant Transient analysis tells us V out (t) if V in (t) changes Requires solving differential equations Input is usually considered to be a step or ramp From 0 to V DD or vice versa
  • Slide 33
  • CMOS VLSI Design4: DC and Transient ResponseSlide 33 Inverter Step Response Ex: find step response of inverter driving load cap
  • Slide 34
  • CMOS VLSI Design4: DC and Transient ResponseSlide 34 Inverter Step Response Ex: find step response of inverter driving load cap
  • Slide 35
  • CMOS VLSI Design4: DC and Transient ResponseSlide 35 Inverter Step Response Ex: find step response of inverter driving load cap
  • Slide 36
  • CMOS VLSI Design4: DC and Transient ResponseSlide 36 Inverter Step Response Ex: find step response of inverter driving load cap
  • Slide 37
  • CMOS VLSI Design4: DC and Transient ResponseSlide 37 Inverter Step Response Ex: find step response of inverter driving load cap
  • Slide 38
  • CMOS VLSI Design4: DC and Transient ResponseSlide 38 Inverter Step Response Ex: find step response of inverter driving load cap
  • Slide 39
  • CMOS VLSI Design4: DC and Transient ResponseSlide 39 Delay Definitions t pdr : t pdf : t pd : t r : t f : fall time
  • Slide 40
  • CMOS VLSI Design4: DC and Transient ResponseSlide 40 Delay Definitions t pdr : rising propagation delay From input to rising output crossing V DD /2 t pdf : falling propagation delay From input to falling output crossing V DD /2 t pd : average propagation delay t pd = (t pdr + t pdf )/2 t r : rise time From output crossing 0.2 V DD to 0.8 V DD t f : fall time From output crossing 0.8 V DD to 0.2 V DD
  • Slide 41
  • CMOS VLSI Design4: DC and Transient ResponseSlide 41 Delay Definitions t cdr : rising contamination delay From input to rising output crossing V DD /2 t cdf : falling contamination delay From input to falling output crossing V DD /2 t cd : average contamination delay t pd = (t cdr + t cdf )/2
  • Slide 42
  • CMOS VLSI Design4: DC and Transient ResponseSlide 42 Simulated Inverter Delay Solving differential equations by hand is too hard SPICE simulator solves the equations numerically Uses more accurate I-V models too! But simulations take time to write
  • Slide 43
  • CMOS VLSI Design4: DC and Transient ResponseSlide 43 Delay Estimation We would like to be able to easily estimate dela

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