Viterbi Algorithm - Implementation

Lecture 14

6.973 Communication System Design – Spring 2006

Massachusetts Institute of Technology

Vladimir Stojanović

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Convolutional Codes

� Adding redundancy

D D

+

+

di di-1 di-2

Channel

0110

1+D2

1+D+D2

0111

0100

(00, 11, 10, 10)

� Generators:G1 = 101

G2 = 111

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Decisions at Each Step

00

01

10

11

State (path) metrics

Branch metrics

i i+1 i+2 � In Gaussian channel: bm = (yk – sk)2

� In BSC:bm = dH(yk, sk) = |yk –sk|

dH is Hamming distance � If received yk = 10

dH(10, 00) = 1 dH(10, 01) = 2

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Trellis Diagram

� Time-indexed state diagram

i i+1 i+2 i+3 i+4

00

01

10

11

0/00

1/11

0/00

1/11

0/11

1/00

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The Viterbi Algorithm

� Illustrated by 2-state trellis sm1n−1 sm1nbm1

bm2 bm3

sm2n−1 bm4 sm2n

tn−1 tn time

sm1n = min (sm1n−1 + bm1, sm2n−1 + bm3) sm2n = min (sm1n−1 + bm2, sm2n−1 + bm4)

Add Add Select Compare

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Viterbi Decoder� Implements Viterbi algorithm � Three main components

� Branch metric calculation � Path metric accumulation (add-compare-

select recursion) � Survivor path decode

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Viterbi Decoder

D

Branch metrics

unit

Add-Compare-

Select

Survivor path

decode

Inputs Decoded bits

� Branch metrics unit � Calculates the distances between the received signal

and the ideal signals � Add-Compare-Select unit

� Accumulates path metrics � Survivor path decode

� Keeps track of the path through the trellis 6.973 Communication System Design 7

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Calculating Branch Metrics

� Assume G1 and G2 both output a 0 � Soft decoder inputs are 0.1 and 0.25 instead � Branch metrics:

� bm00 = |0 – 0.1| + |0 – 0.25| = 0.35

� bm01 = |0 – 0.1| + |1 – 0.25| = 0.85

� bm10 = |1 – 0.1| + |0 – 0.25| = 1.15

� bm11 = |1 – 0.1| + |1 – 0.25| = 1.65

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Calculating Branch Metrics

� Euclidean distances (AWGN channel) � bmi = (yk – sk)2

� sk are usually integers bmi = yk

2 -2Ciyk + Ci 2

� Since yk terms are common to all branch metrics they drop out in ACS comparison, and can be eliminated.

� Ci 2 are precomputed and 2Ciyk are shifts and

adds.

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Add-Compare-Select Recursion

Eight state trellis Conventional add-compare-select unit

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Add-Compare-Select Recursion

Adder

Adder

Subtractor

2:1 Multiplexer

Register

sm1 sm2

bm1

bm2

MSB

Decision New State Metric

5

5

8 8

8 8

8

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,

Add-Compare-Select Recursion

bm2 sm2

0

bm1 0

sm1 0

0

sm2 1

bm2 1

sm2 2

bm2 2

sm2 3

bm2 3

sm2 4

bm2 4

sm2 5

sm2 6

sm2 7

+

+

+

+

+

+

+

+

+ −

−

−

−

−

−

−

−

+

+

+

+

+

+

+

sm1 4

bm1 1

bm1 2

bm1 3

bm1 4

sm1 5

sm1 6

sm1 7

diff

sm 7

sm 6

sm 5

sm 4

sm 3

sm 2

sm 1

sm 0

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Add-Compare-Select Recursion

Time

Bit

1 2 3 4 5 6 70

Select

Register

Register

Add

C C

C C

C C

C C

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Add-Compare-Select Recursion

Radix-4 applied to an eight-state trellis add-compare-select unit

One step lookahead

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Add-Compare-Select Recursionsm3sm1 sm2 sm4

8 8 88

bm1 Adder

5

bm2

5

bm34-way ACS: 5

2 additions + bm4

6 comparisons 5

6.973 Communication System Design Decision 8New State Metric

Adder

Subtractor

4:1 Multiplexer

Register

MSB

Adder

Subtractor

Subtractor

Sele

ct

MSB

MSB

Adder

Subtractor

Subtractor

Subtractor

MSB

MSB

MSB

Inhi

bit s

m3

Inhi

bit s

m48 8 8 8

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2-state example

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Figure from Fettweis, G., and H. Meyr. "High-speed Parallel Viterbi Decoding: Algorithm and VLSI-architecture."IEEE Communications Magazine 29 (1991): 46-55. Copyright 1991 IEEE. Used with permission.

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Figure from Fettweis, G., and H. Meyr. "High-speed Parallel Viterbi Decoding: Algorithm and VLSI-architecture."IEEE Communications Magazine 29 (1991): 46-55. Copyright 1991 IEEE. Used with permission.

Bit-level view

MSB

LSB

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Figure from Fettweis, G., and H. Meyr. "High-speed Parallel Viterbi Decoding: Algorithm and VLSI-architecture."IEEE Communications Magazine 29 (1991): 46-55. Copyright 1991 IEEE. Used with permission.

Turn into forward path and pipeline

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Figures from Fettweis, G., and H. Meyr. "High-speed Parallel Viterbi Decoding: Algorithm and VLSI-architecture."IEEE Communications Magazine 29 (1991): 46-55. Copyright 1991 IEEE. Used with permission.

Add-Compare-Select Recursion

Parallel compare-select-add unit 6.973 Communication System Design 20

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References

� Slides from Borivoje Nikolic and Bob Brodersen � G. Fettweis and H. Meyr "High-speed parallel

Viterbi decoding: algorithm and VLSI-architecture," Communications Magazine, IEEEvol. 29, no. 5, pp. 46-55, 1991.

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