Sigma Delta Feedback DAC Architectures for High Accuracy and Extremely Low Charge Transfer

Ketan J. Pol, Hans Hegt Mixed-signal Microelectronics, Department of Electrical

Engineering Technische Universiteit Eindhoven

Eindhoven, The Netherlands k.j.pol@tue.nl, j.a.hegt@tue.nl

Sotir Ouzounov Micro systems & Devices

Philips Research Eindhoven, The Netherlands sotir.ouzounov@philips.com

Abstract—Sigma delta ADCs (SD-ADC) are often the preferred ADCs of choice in sensor interfacing applications due to their high achievable absolute accuracy. Constraints such as low power and limited area often dictate minimum front-end hardware, thereby limiting options for pre-processing stages. Processing very small input signals requires that the magnitudes of the signals at the input summing node match. Given that often the sensor output current is of extremely low magnitude, the feedback DAC also has to transfer extremely small charges (order of a few femto-coulombs). Such constraints challenge the limits of existing process technologies. This paper investigates single bit feedback DAC architectures tailored specifically for very low charge transfers.

Switched capacitor DACs are a viable means of transferring discrete charge packets accurately. Various DAC structures are compared using criteria such as absolute charge transfer error, effect of parasitic capacitances and the output referred noise.

Accuracy of the feedback DAC is a major bottle-neck in the overall accuracy of the SD-ADC. The accuracy of the SD-ADC is compared for different feedback DAC structures. DAC structures are individually simulated using Spectre for 0.13um 3.3V standard CMOS technology. Based on circuit simulations, the feedback DAC is modeled in MATLAB as a combination of a ‘gain’ block, ‘offset’ error, additive noise and delay. A 1-bit 2nd order CT-SDM with the DAC model in the feedback path is used as a test vehicle and is simulated in MATLAB for accuracy calculations.

I. INTRODUCTION Sigma delta ADCs operated in an incremental fashion are

extremely well suited for sensor interfacing applications [1, 2]. Some applications, however, have stringent area and power requirements. E.g. wireless sensor nodes powered by energy harvesting circuits have a very limited area and power budget. Consequently, the sensor interfacing circuit has to be minimal and efficient, both, in terms of area and power. Under these circumstances, the sensor is interfaced directly to the ADC without any pre- amplification. In case of the incremental sigma delta ADC, this means that the sensor output is directly connected to the input summing node. As a

consequence, the output of the feedback DAC should produce a signal which is comparable with the maximum signal swing of the sensor output. In case of bio-sensors, image sensors, etc. the output signal can be extremely small, often in the order of a few pico-amperes. These signal requirements are mirrored into the feedback DAC.

Traditional methods such as switched resistor (SR), switched current (SI) are subject to very wide tolerances, mismatch errors and clock jitter. Switched capacitor DACs are the most viable candidates for generating the required output signal in the form of discrete charge packets. Using a ‘SC resistor’-like arrangement, the charge transfer that can be achieved is limited by the value of the capacitance and the voltage applied across it. E.g. to transfer a charge of 1 fC, using a 1 V reference we would need a 1 fF capacitor which is usually not practical to implement. The goal of this paper is to investigate DAC topologies which can achieve the required charge transfer within the limits of a given technology.

Section II of this paper presents some promising DAC architectures and their operation. Section III discusses various non-idealities in the DAC or resulting from it. Section IV discusses the effect of the non-idealities on the SD-ADC accuracy.

II. FEEDBACK DAC ARCHITECTURES Switched-capacitor DACs typically require switches,

capacitors, voltage references and driving clocks. The simplest form of a switched-capacitor feedback DAC is the switched-capacitor resistor. Transferring very low charges accurately is, however, challenging and requires highly accurate components. One of the techniques involves charge redistribution between different sized capacitors. Another technique involves implementation of a very small equivalent capacitance. A third technique involves accurate control of the charging operation of the capacitor. These techniques are discussed in detail below.

This work is supported by STW and Philips Research

978-1-4673-5762-3/13/$31.00 ©2013 IEEE 1813

A. Two Reference Charge Sharing The Two Reference Charge Sharing architecture is based

on the charge redistribution principle. Charge stored on a capacitor is manipulated by connecting proper ratios of parallel capacitances across it. Fig. 1 shows the conceptual circuit diagram. The circuit follows a three phase operation. The duration of each phase is much smaller than the period of the clock. Vdac+ and Vdac- are the DAC inputs and Vcom provides the reference level.

Fig. 1. Two Reference Charge Sharing DAC. The switches can be implemented as single MOS transistors or as complementary transmission gates. Using transmission gates mitigates the effect of charge injection and clock feedthrough. Depending on the comparator feedback ‘bit’ signal, one of the input voltages is connected to the DAC and consequently charge is either dumped or extracted by the DAC. The operation of the circuit can be summarized as follows, Phase1 – Capacitor C1 is charged. Phase2 – Charge on C1 is redistributed among C1, C2 and C3. Phase3 – C3 discharged by dumping/extracting charge from the virtual ground. C2 is discharged. Here C2 acts as a reservoir to take away all the excess charge. If we suppose that ‘C’ is the unit capacitance and C1=K*C, C2=N*C, C3=M*C then the charge stored on C3 and subsequently transferred in Phase3 is given as,

(1)

Choosing K = M = 1 results in the lowest total capacitance,

(2)

If, for example, Vcom =1.25V, Vdac+ = 1.75V, C = 100fC, then to transfer a charge of 1 fC, we need N = 48. A charge transfer of 1 fC is assumed in the rest of the architectures as well.

B. One Reference Charge Sharing The ‘One Reference Charge Sharing DAC’ uses the same

charge redistribution principle. It uses a single DAC input voltage Vdac instead of Vdac+ and Vdac-. The polarity of the charge transfer is controlled using a pair of cross-coupled switches at the output of the DAC. Fig. 2 shows the circuit. Like the previous topology, the only difference lies in the way the output capacitor C3 is connected to the virtual ground. By inverting the connections (using the cross-coupled switches), charge accumulation or charge extraction

can be accomplished.

Fig. 2. One Reference Charge Sharing DAC.

C. Two References with Capacitor Bank Another method to accomplish very low charge transfers is

by implementing a very small capacitance. The most straightforward way to do so is by cascading capacitances in series. The equivalent capacitance of N identical capacitors is 1/N times the individual capacitance. This is necessary because the smallest capacitor available in the technology may not be small enough. A topology which implements such a series capacitor bank is shown in fig. 3.

Fig. 3. Two References with Capacitor Bank DAC. The switches labeled

phase1a and phase2a are turned off slightly earlier than phase1 and phase2 switches respectively.

The operation of the circuit is described as follows;

Phase1 - Capacitor bank charges. Charge held depends on the equivalent capacitance in the bank and the voltage across it. Phase2 - The capacitor bank discharges into the virtual ground. Charge extraction or charge accumulation depends on the comparator feedback ‘bit’ signal which selects an input voltage which is either higher or lower than Vcom.

D. Time Constant Controlled Charge Transfer An alternative approach is to control the levels to which

the capacitor charges. The process of charging of the capacitor can be slowed by using a large series resistor. Fig. 4 shows the circuit. The circuit is identical to the capacitor bank based version, except that a single capacitor can be used instead of a capacitor bank. The capacitor charges slowly through a large resistor. This charging continues for the ON duration of the phase1 clocks. Thus the capacitor is not allowed to charge completely, but, only to the desired charge by carefully controlled timing. The larger the resistor more relaxed the constraints on the accuracy of the phase clocks.

III. NON-IDEALITIES DUE TO FEEDBACK DAC ERRORS

This section considers the various sources of non-idealities in the sigma delta ADC due to the feedback DAC. Some non- idealities such as charge injection are present in the DAC itself, whereas ones such as excess loop delay affect the loop without influencing the charge transfer properties of the DAC

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Fig. 4. Time Constant Controlled Charge Transfer DAC. itself. Most of the non-idealities in the DAC manifest in the form of gain and offset errors. Consequently the feedback DAC can also be modeled, to the first order, as a gain and offset block. Charge sampling delay is represented by transport delay block. Such a model is shown in fig. 5.

Fig. 5. Sigma delta modulator with the DAC model in the feedback path.

A. Charge Injection and Clock Feedthrough

Charge injection and clock feedthrough are the major contributors in charge transfer errors. MOS transistors used as switches inject error charge into the signal path whenever the switches open. Furthermore, overlap capacitances couple the high frequency phase clocks into the signal path. These shortcomings can be alleviated to some extent, although not completely, by using complementary transmission gates, slow rise/fall times of the clock and compensating dummy switches [3, 4].

B. Parasitic Capacitances Parasitic capacitances are major contributors in charge

transfer inaccuracies when extremely small charges are to be transferred. We have considered sandwich, MIM capacitors and overlap capacitances. Sandwich capacitors use lower metal layers and have larger parasitics compared to MIM. However, MIM capacitors have a larger process spread.

All intrinsic parasitic capacitances are referred to ground. Layouts for single transistors and capacitors were extracted for parasitics. Parasitics due to circuit interconnects however are not accounted for. Interconnect parasitics would be dependent on the layout of the DAC as a whole and can be minimized to some extent by proper layout design. Having extracted the parasitics, the circuit can be remodeled by using ideal components and adding the parasitic components separately. An example of the Two Reference Capacitor Bank DAC with added parasitics is shown in fig. 6.

C. Voltage Reference Variation Any inaccuracy in the implementation of the voltage

references directly affects the accuracy of the charge being sampled and subsequently transferred. For architectures

which use more than one voltage reference, the matching between the references is also important.

Fig. 6. Two Reference Capacitor Bank DAC with parasitic capacitances

added to the schematic.

D. Noise Noise invariably limits the accuracy of the sigma delta

ADC. kT/C noise generated by the switched capacitor DAC appears at the input of the sigma delta ADC. Most sigma delta modulators are designed to have a signal transfer function (STF) of unity in the signal bandwidth. Thus, the noise passes through the ADC unfiltered. It is important to consider this source of non-ideality and minimize it by proper circuit design. The results of the simulations on the DAC architectures are plotted in fig. 7.

Fig. 7. Output referred RMS noise curves for the four DAC

architectures.

E. Excess Loop Delay Excess loop delay is determined by the phase timing

properties. SC-DACs transfer charges in discrete time instants. If the DAC uses the same clock duty ratio as the ADC clock, the resulting delay in the loop is significant. To minimize the delay, the duty cycle ratio of each clock phase should be as small as possible without affecting the charge transfer properties.

F. Clock Jitter Switched capacitor DACs are relatively resistant to clock

jitter [5]. Jitter however becomes a problem in case of the Time Constant Control based DAC.

IV. EFFECT OF NON-IDEALITIES ON SDM PERFORMANCE The main goal of our comparison is to study the effects of

feedback DAC non-idealities on the overall sigma delta ADC performance. The model shown in fig. 5 is used for this purpose. Simulation results from Spectre are imported into this model. The sigma delta ADC accuracy will be measured using normalized error plots for DC input amplitude sweeps. Fig. 8a plots the normalized error with an ideal DAC, i.e.,

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without gain/offset errors and noise. The figure shows that the errors are bounded below 0.001 over approximately 80% of the input dynamic range. This corresponds to 10-bit accuracy. The effect of each non-ideality is introduced one at a time, starting with charge injection and clock feedthrough errors due to non-ideal switches in fig. 8b. Next, the effect of parasitic capacitances is considered in fig. 9a. (Ideal switches are used to eliminate charge injection and clock feedthrough errors). Finally we consider the effect of noise and excess loop delay due to the DAC in fig. 9b.

The Two reference charge share based DAC is relatively less sensitive to parasitics if the bottom plates of the capacitors are connected to Vref. It also exhibits low gain and

(a) (b)

Fig. 8. Normalized error plot for a sigma delta modulator (a) Using an ideal feedback DAC. (b) Only charge injection and clock feedthrough errors are considered

offset errors as a result. It, however, requires a larger area to implement the larger middle capacitor. It also requires a 3 phase clock which might introduce extra delay in the sigma delta loop.

(a) (b)

Fig. 9. Normalized error plot for a sigma delta modulator (a) Only parasitic capacitances are considered. (b) Only noise and delay is considered.

Tab. 1. highlights the pros and cons of each architecture.

2 Reference Charge Sharing

1 Reference Charge Sharing

Capacitor Bank Based

Time Constant Controlled

Pros • Less Sensitive to Parasitics

• Low charge injection and feedthrough errors

• Only 1 input reference source required

• Low charge injection and feedthrough errors

• Least Noise

• Low charge injection and feedthrough errors

• Less Noise • Least Area

Cons • Large Area • Requires 3

phase clock • High Noise

• Large Offset Error

• High Noise • Requires 3

phase clock

• Most sensitive to parasitics

• Requires complex clocking

• Very sensitive to clock jitter

Tab. 1. Comparison of the pros and cons of the four DAC architectures

The One reference charge sharing based DAC requires only one reference source. This eliminates the issue of

matching between the references. The cross-coupled switches connect the outer DAC capacitor to the virtual ground input of the summing node. This connection is data-dependent, i.e., dependent on comparator signal providing the feedback. Due to this, the bottom plate parasitic of the outer capacitor is not always connected to a fixed voltage. This results in a large offset error. The Capacitor bank based DAC has very low charge injection and clock feedthrough errors. It also generates the least noise. However, due to the series capacitor bank, bottom plate parasitics severely degrade the performance. The Time constant controlled DAC is similar to the Capacitor bank based DAC and further requires very less area as it uses only a single capacitor. However, it requires complex clocking with very finely controlled clock pulses. Any clock jitter severely degrades the accuracy of charge transfer.

V. CONCLUSIONS

In this paper, four feedback DAC architectures were analyzed. The impact of DAC non-idealities on the SDM performance was analyzed in the form of a normalized error plot. For DACs in which the accuracy is limited by gain and offset errors; their errors can be easily corrected as long as they do not lead to clipping or adversely affect the operation of the loop. This makes the One Reference, Two Reference Charge Sharing based DACs quite attractive. If the sigma delta ADC is required to convert signals belonging to different dynamic ranges, a DAC with programmable charge transfer characteristics is required. This is most easily accomplished by using a programmable capacitor bank in the Capacitor Bank based DAC. For designs with severely constrained area requirements, the Time Constant Control based DAC can be used.

It should be noted that all the discussed architectures can be combined in one form or another to get the best compromise as per requirements. E.g. Two Reference Charge Sharing based DAC can use a capacitor bank instead of a single capacitor C2 for programmability.

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[5] van Veldhoven, R.H.M., "A triple-mode continuous-time ΣΔ modulator with switched-capacitor feedback DAC for a GSM-EDGE/CDMA2000/UMTS receiver," Solid-State Circuits, IEEE Journal of , vol.38, no.12, pp. 2069- 2076, Dec. 2003

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