Novel Scarce-State-Transition Syndrome-Former Erros Convolutional Codes

L. H. Charles Lee*, David J. Tail**, Patrick G. Farre!l*'K, and Paul S. C. Leung***

School of Mathematics, Physics, Computing and Electronics, Macquarie University, Sydney, NSW 2109, Australia

Department of Electrical Engineering, The University, Dover St., Manchester, MI 3 9PL, United Kingdom

School of Computer and Information Science, University of South Australia, Whyalla, SA 5608, Australia

* ** ***

Abstract - A novel maximum-likelihood hard- and 8- levell soft-decision scarce-state-transition (SST) type syndrome-former error-trellis decoding system of (n, EL-I) convolutional codes with coherent BPSK signals for additive white Gaussian noise channels is proposed. The proposed system retains the same number of binary comparisons as the syndrome-former trellis decoding method of Yamada et al. [a]. Like the original SST-type register-exchange Viterbi decoding system [4], the proposed system also has the same advantage of drawing less power when implemented on CMOS LSI chips. A combination of the two tech:niques results a less complex and low power consumption decoding system.

SUMMARY

In Viterbi algorithm decoding of ( n , k ) convolutional code:s, the decoder carries out (Zk- 1)-ary comparisons at each node of the encoder trellis [I] . The implementation of the Viterbi decoder becomes impractical for high-rate, powerful codes as the number of operations and memory path histories increase. In a 1983 paper, Yamada et al. [2] proposed a maximum-likelihood decoding system for rate- (n- 1)ln convolutional codes, and the system performance was studied by Lee and Farrell [ 3 ] . The decoding system applies the Viterbi algorithm to the syndrome-former trellis of the code. Apparently, the number of trellis states is dorubled, but the number of comparisons at each node is reduced to a binary comparison. Recently, Kubota et al. [4] proposed scarce-state-transition (SST) register- exchange (information bits are associated with surviving paths) Viterbi decoding system of reduced states, implemented on CMOS VLSI chips and consumed less powe,r in the low bit-error-rate (BER) operating region when compared with a hypothetical register-exchange type of Vjterbi decoder. A power consumption reduction of 40% at a bit error rate of 0.0001 can be achieved when opera.ting at an information rate of 25 Mbit/s [4], and the measured power consumption with increasing channel noise was also reported in [4]. In this paper, we proposed a new maximum-likelihood SST-type trellis decoding systejm for rate-(n- 1)ln convolutional codes, called the SST-type syndrome-former error-trellis decoding system. Our decoding system differs from the error-trellis syndrome decoding technique proposed by Reed et al. [SI. In their paper, the trellis is constrained and drawn from a k-input, (n-k)-output regulator circuit of a rate-kln convolutional code and is only applicable to the class of systematic codes whereas our syndrome-former error-trellis is drawn from the n-input, single-output syndrome-former circuit of a rate- (n- 1)h systematic or non-systematic convolutional code. The new system is similar to the SST-type Viterbi decoding system [4] in that it has the advantage of drawing less power when implemented on CMOS chips and operated in a low BER condition. Like the Yamada

decoding systeim [2], the new system has also retained a binary comparison at each trellis node and significantly reduces the decoding complexity. A combination of the two techniques results a less complex and low power consumption decoding system.

The simulated bit error probability performance of the proposed hard- and &level soft-decision decoding system, shown in Figure 1, for additive white Gaussian channels is presented. Furthermore, the implementation complexity of the new decoding system is compared with the SST-type register-exchange Viterbi decoding system.

Fig. 1 Model of an eight-level soft-decision SST-type syndrome-former error-trellis decoding system

REFERENCES

A. J. Viterbi, "Error bounds for convolutional codes and an asymptotically optimum decoding algorithm", IEEE Trans., vol. IT-13, pp. 260-269, 1967.

T. Yamada, H. Harashima, and H. Miyakawa, "A new maximum likelihood decoding of high rate convolutional codes using a trellis", Trans. Inst. Electron. & Commun. Eng. Japan, 66A, pp. 11-16, 1983.

L. H. C. Lee, and P. 6. Farrell, "Error performance of maximum-likelihood trellis decoding of (n, n- 1) convolutional codes : A simulation study", ZEE Proc.-F, vol. 134, no. 7, pp. 1673-680, 1987.

S. Kubota, S. Kato, and T. Ishitanil "Novel Viterbi dccoder VLSI implementation and its performance", ZEEE Trans., vol. COM-41, pp. 1170-1178, 1993.

I. S. Reed, and T. I(. Turong, "Error-trellis syndrome decoding techniques for convolutional codes", IEE Proc-F, vol. 123, no. 2, pp. 77-83, 1985.