Ch.9 - Exercises Solutions

Q.1Briefly state the main steps of the high-level design process of a CT ΣΔ-converters.

Solution:Typically, the bandwidth of operation of the ADC to be designed is known (i.e. or at least its application from which the bandwidth can be derived) as well as the target resolution or SNR. Therefore, the steps to follow in a design include:

To identify the resolution/SNR to be achieved. Important to consider is to keep a tolerance of approximately 10-20 dB from minimum SNR specification(i.e. depending on the order of the converter. Due to stability issues, high-order modulators tends to require higher tolerances, etc.) in order to have some margin for non-idealities and thermal noise budget.

Choose the NTF approximation type. Note that in this book only Butterworth is considered.

Considering stability considerations (i.e. Lee's criterion) and minimum tolerances, identify the order of the modulator, the OSR and sampling ratio of the converter.

Identify the number of bits of the quantizer, considering possible requirements of stable input range. If a multi-bit quantizer is implemented, consider the DEM technique to implement to counteract DAC mismatches.

According to the choices made, identify a suitable loop filter topology.

According to power, area, and costs, as well as the harmonic distortion and bandwidth (i.e. CIFF architectures may be difficult to implement at very high bandwidths due to the peak at high-frequency, pre-filtering of the input signal may be necessary, etc.) requirements of the ADC, identify a suitable architecture. This may include the use of resonators or techniques such as quantization noise coupling. Important to consider at this point is if ELD compensation could be required.

According to the architecture selected, identify the OBG to be used and estimate the achievable SNR/Resolution. Important to consider at this point are the tolerances of the resistors/capacitors. Further, the use of dither should also be considered at this point in order to set an appropriate SNR estimate.

Using the Schreier's Toolbox synthesize the NTF. Consider ELD if required from the design.

Develop the Simulink® model of the modulator designed.

Check, approximately, correct modulator behavior (e.g. input sinewave = output sinewave, 2-bit quantization of the output signal, etc. Note that, obviously, the input

signal should have an amplitude and frequency not too high nor too low, in order to avoid instability, etc.).

Investigate that dynamic range scaling has been performed satisfactorily.

Identify the stable input range from simulation of the Simulink® model and through calculations.

Verify, through simulation, that the achievable SQNR and spectral properties of the modulator meet the theoretical design (SQNR value, notch in the spectrum, flattened NTF, etc.).

Perform DC behavior simulations and ensure the ability of the modulator to convert signals, without the use of dither. Assess if tones are present and, if dither is required, find the minimum value of dither to be used.

Assess the stability and tonal behavior of the modulator with slow varying signals such as sine waves. Define the dither value required to eliminate tones in relation to the achievable SQNR and stable input range.

Assess the stability of the modulator for difficult input signals such as ramp, step and chirp.

Assess the ability of the modulator to perform satisfactorily when integrators finite gain and saturation is introduced in the Simulink® model.

Assess the ability of the modulator to perform satisfactorily when DAC mismatches are introduced in the Simulink® model.

Assess the ability of the modulator to perform satisfactorily when coefficients mismatches are introduced in the Simulink® model.

Assess the ISI, ELD and Jitter effects on the modulator.

Assess the ability of the modulator to perform satisfactorily when as many non-idealities as possible are introduced, simultaneously, in the Simulink® model.

Q.2For the design example considered in this chapter, list at least other 3 different theoretical designs. Support your answer with some minimum analysis.

Solution:Obviously, many solutions are possible. Some of these may include:

4-bit, 3rd order CIFF modulator with an OSR of 64. The advantage would be not having the resonator. The main disadvantage would be a larger are due to the higher number of bits required.

2-bit, 3rd order with an OSR of 128. Simpler architecture and lower number of bits, but OSR might be too high depending on the implementation technology to be used and available clock.

3-bit, 2nd order CIFF modulator with an OSR of 256. The advantage would be a smaller modulator order, hence a system which is less difficult to stabilize but the OSR may result too high for the technology available.

Q.3Design the NTF of an audio, single-bit, fifth-order CT ΣΔ-modulator with OSR = 32, NRZ DAC pulse and OBG = 1.5 in the case of a CRFB architecture. Note to set the input feedforward coefficients b2 , b3 , b4 and b5 to zero. Plot the pole-zero graphs.

Solution:

Q.4Map, in Simulink®, the synthesized NTF in Q.3 to a CRFB topology. Simulate the modulator and estimate the in-band SQNR and the MSA. Briefly analyze your results.

Hint: If the Schreier's Toolbox is used to compute the coefficients, make sure the Simulink® model refers to the same coefficients nomenclature. Therefore, check the Schreier's Toolbox Manual for the appropriate nomenclature.

Solution:According to Fig.A1, appendix A, it is seen that the SQNR found is what expected. Important to note is the very high reduction from the theoretical SQNR predicted in Table A1 due to the reduction in OBG required to make the system stable. Moreover, note the small input range allowed, which also influence the achievable SQNR. Therefore, it results that very high order modulators with a low number of bits are very ineffective when compared to their theoretical potential.

MSA = 0.5833

Q.5Calculate the maximum asymmetry allowed for the feedback DAC pulse in order to retain the SQNR found in Q.4 of 83 dB.

Solution:

τ ≤4T s√OSRSN Rdesired

=4∗( 1

24000 ∙2∙32 ) ∙√3210

( 8320 )≈1ns

Q.6What changes would you make to the Simulink® schematic if the modulator in Q.3 would require some sort of ELD compensation?

Solution:Use of an additional feedback path directly connected to the quantizer input, often called 0th Order path, in order to cancel the extra coefficient introduced by ELD in the NTF. The main disadvantage is that another feedback DAC would be required. Note that in the case of CIFB/CRFB modulators, which already need a feedback DAC in every of the feedback paths, the addition of ELD compensation is particularly disadvantageous in terms of area and power consumption.

Q.7List some of the reasons to convince your Manager that a DAC pulse different from the NRZ would be beneficial in a CT modulator. How would you mitigate the errors arising due to the non-linearity in the multi-bit feedback DAC?

Solution:In CT modulators both the shape and timing information of the feedback DAC pulses are significant as these directly affects the system performance. Note that, since the DAC pulses are continuously being integrated they cannot be treated as digital signals as in the case of DT modulators, where the actual shape of the feedback pulse does not affect the overall system performance and only the final settling accuracy of the voltage in the first integrator is of interest.

NRZ pulses allow for a greater charge to be fed back at each cycle compared to the RZ and‐ HRZ type, resulting in a greater input signal dynamic range and a more power efficient DAC implementation, while being more robust towards jitter. For RZ and HRZ implementations the input signal needs to be scaled down in order to maintain modulator stability and this results in a reduction of the dynamic range. However, the advantage of using RZ or HRZ pulses is that they allow to partially solve some of the timing related non idealities affecting NRZ‐ ‐ pulses. Additionally, RZ pulses allow to be pulse shaped which is useful in order to reduce‐ jitter noise. Therefore, although NRZ pulses may perform better than RZ and HRZ ones, it should be noted that these do not allow for pulse shaping techniques to be applied, making‐ the modulator jitter performance entirely dependent on the quality of the clock. If a high quality clock is required and if the modulator designed is particularly sensitive to timing and jitter errors, using different feedback DAC pulses technique could result in the cheapest and more effective option.