Ch.6 - Exercises Solutions

Q.1Sketch the block diagram of the 1+1+1 MASH ΣΔ-modulator and find the output transfer function for V (z ).

Solution:

V 1 (z )=ST F1U ( z )+NT F1 ( z )E1(z )

V 2 ( z )=ST F2 E1 ( z )+NT F2 ( z )E2(z )

V 3 ( z )=ST F3 E2 (z )+NT F3 ( z )E3(z)

V ( z )=H 1 ( z )V 1 ( z )−H 2 ( z )V 2 ( z )+H3 ( z )V 3(z)

V ( z )=H1 ( z )ST F1 ( z )U ( z )+ [H1 ( z )NT F1 ( z )−H 2 ( z )ST F2 ( z ) ] E1 ( z )− [H2 ( z )NT F2 ( z )−H 3 ( z )ST F3 ( z ) ] E2 ( z )+H 3 ( z )NT F3(z)E3 (z )

So we require:

H 1 (z ) NT F1 ( z )−H2 ( z )ST F2 ( z )=0

H 2 (z ) NT F2 ( z )−H 3 (z )ST F3 ( z )=0Choose:

H 1 (z )=ST F1 (z )ST F2 ( z )ST F3( z)

H 2 (z )=NT F1 (z )ST F1 ( z )ST F3(z )

H 3 ( z )=ST F1 ( z )NT F2 ( z )NT F1(z )

First order modulators with NT Fi ( z )=(1−z−1) and ST Fi(z )=z−1:

H 1 (z )=z−3

H 2 (z )=z−2 (1−z−1 )

H 3 ( z )=z−1 (1−z−1 )2

So:

V ( z )=z−3U ( z )+(1−z−1 )3

Q.2Find the output transfer function for V (z ) of the MASH ΣΔ-modulator shown in Fig.6.6 and determine its order. What is the delay, in terms of STF(z ), at the output?

Solution:

V 1 (z )=(1−z−1 ) E1 ( z )+z−1U (z )

U2 ( z )=( z−1

1−z−1 )∙ (U ( z )−V 1(z ))=( z−1

1−z−1 )U ( z )−( z−1

1−z−1 ) ∙ [ (1−z−1 ) E1 ( z )+z−1U (z) ]

V 2 ( z)=(1−z−1 ) E2 ( z )+z−1U 2 ( z )=(1−z−1 ) E2 ( z )+( z−2

1−z−1 )U ( z )−Z−2 E1 ( z )−( z−2

1−z−1 )U ( z )=(1−z−1 )E2 ( z )−z−2 E1(z)

V ( z )=V 2 (z )−z−1V 2 ( z )+z−2V 1 (z )=(1−z−1 )V 2 ( z )+z−2V 1 ( z )=(1−z−1 )2E2 ( z )−(1−z−1 ) z−2E1 ( z )+(1−z−1 ) z−2E1 ( z )+ z−3U ( z )

V ( z )=(1−z−1 )2E2 ( z )+z−3U (z )

The STF is delayed by z−3, while the NTF is a second order (1−z−1)2.

Q.3Sketch a block diagram of a fourth order MASH ΣΔ-modulator. Carefully choose the modulator architectures of the different stages and explain your choices (Note: Do not worry about achievable SNR, etc. but solve the exercise solely from a theoretical point of view).

Solution:Many solutions are possible provided thoughtful reasoning of the choices made. However, the most intuitive answer is probably to cascade a second order Silva-Steensgaard multi-bit modulator into another MOD2. This because the Silva-Steensgaard MOD2 already provides the input in analog form for the second stage of a MASH modulator. The multi-bit choice of the first stage would be to increase the tolerance of the sensitive first stage to non-idealities. The second stage would be another second order modulator in order to reduce the number of quantizers, summing circuits and digital filters that would be required if MOD1 were used. Note that the second stage may use a single-bit quantizer in order to reduce complexity, area and power consumption.

Q.4Explain the practical implementation difficulties faced by MASH ΣΔ-modulator structures.

Solution:The main problem affecting MASH modulators is that if perfect cancellation of the analog and digital terms is not easily achieved, due to imperfections in the realization of the analog transfer functions (e.g. capacitor matching, finite opamp gain, non-unity quantizer gain, Signal path gain, etc.), then the error E1 of the first stage will appear at the output multiplied by ST F2d ( z ) NT F1a (z )−ST F2a(z )NT F1d ( z ) - where subscript a denotes the actual value of the analog transfer function and d the digital terms. This may result in a serious degradation of the SQNR performance of the modulator.

Q.5Consider a 2+2 MASH ΣΔ-modulator. Discuss if you would require DEM logic to mitigate the effects of feedback DAC non-linearity in any of the stages.

Solution:Assuming the first stage provides enough suppression of the noise, MASH structures often allow the use of a multi-bit quantizer in the second or further stages without any DEM or other correction of the DAC non-linearity [6]. In the case of the 2+2 MASH modulator this is true since the non-linearity error of the second stage DAC (as part of V 2) is multiplied by H 2 (z )before being added into the output signal V . Therefore, H 2(z ) contains the NTF of the first stage. Since thisNT F1(z ) is a high-pass filter function, the non-linearity error of the second stage DAC is suppressed in the baseband [2].

Q.6Sketch the first stage of a 2+1 MASH ΣΔ-modulator using the simplest MOD2 architecture, demonstrating how the input to the second stage could be obtained if it was not already available as in the case of Silva-Steensgaard architectures.

Solution:

Q.7Assume that a 2+1 MASH architecture is used with a first stage in-band SQNR of 60 dB. What reduction is expected in order to cancel E1 to negligible levels, considering a 100 dB SQNR target? What consideration should be taken into account regarding the cancellation accuracy, signal path gain errors and limits of CMOS technology?

Solution:Cancelling E1 to negligible levels requires reducing it by more than 40 dB - cancelling to >99% accuracy, such as:

10( 4020 )=100

1100

≈0.01→0.01∗100=1→99%

Therefore, the gain path errors should results << 1%. This is just enuough tolerance for any modern CMOS technology, assuming typical mismatches of 0.25% (e.g. a total error of 1% should be easily achievable, but this would give almost no margin below the target SQNR).

Q.8Briefly state the main differences between single-loop and MASH ΣΔ-converters.

Solution:

Single-Loop MASH

Stability Low High

Input Range Small Large

Sensitivity to Finite DC Integrator Gains

Low High

Sensitivity to Signal Path Gain Errors

Low High

Sensitivity to Mismatches Low High

Sensitivity to Limit Cycle High Low

Area Small Large

Design Complexity High Low