309

2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA)

978-1-7281-4661-4/20/$31.00 ©2020 IEEEDOI 10.1109/ISCA45697.2020.00035

Plasticine

PMU

PCU

PCUPMU

Mem. Ctrl. Interconnect

PMU

PCU

SRAM

ba

nk

ing

log

ic

reconf. scratchpadinput bu ers

scalar

control

vector

input bu ers

vector

control

scalar

FPU/ALUPipeline Reg.

database processing new in Gorgon

SRAM

SRAM

•

•

310

311

Partition

Merge sort

Tile sort

Reduce

Reduce

Partition

Merge sort

Tile sort

Part. sort

Join

Merge

Tile sort

Merge sort

Partition Par. partition

Tile sort

PMU

PCU

Group

Merge

Par. merge sort Par. partition sort

Par. joinPar. group-by Filter

Filter

Pred. gen.

Record mux Record demux

Merge

312

Record bu er

Record bu er

Se

lect

or

Co

mp

act

or

Shu le network

data A

shi A

data B

shi B

Op

era

nd

co

nfi

g

popcountshi A

popcountshi B

Selector

Record bu er

Shu le networkFIFO

Ba

rre

l sh

ie

r

FIFO

Control logicshi

shi

data

enable

swap

opcode

lane 0

lane 1

>

opcode

merge swap

partition swap

filter swap

tim

e

space

4 lanes

1 c

ycle

4 c

ycle

s

1 lane

record 0 record 1 record 2 record 3

record 4 record 5 record 6 record 7

reco

rd 0

reco

rd 1

reco

rd 2

reco

rd 1

5

reco

rd 1

6

reco

rd 1

7

reco

rd 1

8

reco

rd 3

1

Layout in-space

field B field C

32 bits 64 bits 32 bits

field A

Layout in-time

313

1

2

3

4

1

2

3

4

3

34

4

4 3

Records in-spaceRecords in-timeb

an

k

field

lan

e

o set

1

2

3

4

1

1

1

2

2

2

1

1

1

2

2

2

3

3

3

4

4

4

shi

Compactor

valid lanes [6:0]

Record bu er

wrap around

write enable [31:16] write enable [15:0]

314

315

316

317

318

. . . .

319

320

321