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Embedded Systems 1: OnChip Bus
Davide Zoni PhDemail: [email protected]
webpage: home.deib.polimi.it/zoni
October 2017
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Embedded Systems 1 Davide Zoni
Pipelined Bus Architecture with Fixed Memory Latency
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Embedded Systems 1 Davide Zoni
Cycle 1
ARW(64,1)
R(64,1)
R(64,1)
W(64,1)
W(64,1)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1
2
3
4
5
● Data/Address Bus is Shared, width = 64 bit● Pipelined Bus Architecture● Arbiter grants READ first FIFO order. Responses have precedence over request (Split Opt)● Transaction Shape (cycles):
➔ READ Transaction: |AR|A|G|Ba|M|Br|➔ WRITE Transaction: |AR|A|G|Ba|Bd|M|Bk|
● Notation & Symbols: AR arb req; A – arb stage; G – grant; Ba – bus address; Bd – bus data; M – Memory; Br – response; Bk ack
Bus Usage
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Embedded Systems 1 Davide Zoni
Cycle 2
AR A
AR
W(64,1)
R(64,1)
R(64,1)
W(64,1)
W(64,1)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1
2
3
4
5
Bus Usage
● Arbiter➔ No grant Bus usage mask (cycles: );➔ Evaluate
➢ 1 W(64,1) – Bus usage mask (cycles: 4,5,7);
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Embedded Systems 1 Davide Zoni
Cycle 3
AR A G
AR A
AR
W(64,1)
R(64,1)
R(64,1)
W(64,1)
W(64,1)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1
2
3
4
5
● Arbiter➔ Grant 1 W(64,1) – Bus usage mask (cycles: 4,5,7);➔ Evaluate R(64,1) in A stage for the next grant: FAILED mask (cycles: 5,7)
Bus Usage
READ Transaction: |AR|A|G|Ba|M|Br| WRITE Transaction: |AR|A|G|Ba|Bd|M|Bk|
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Embedded Systems 1 Davide Zoni
Cycle 4
AR A G Ba
AR A
AR A
AR
W(64,1)
R(64,1)
R(64,1)
W(64,1)
W(64,1)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1
2
3
4
5
Bus Usage
● Arbiter➔ No grant Bus usage mask (cycles: 5,7);➔ Evaluate
➢ 2 R(64,1): PASS bus mask (cycles: 6,8)● Bus is in use
READ Transaction: |AR|A|G|Ba|M|Br| WRITE Transaction: |AR|A|G|Ba|Bd|M|Bk|
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Embedded Systems 1 Davide Zoni
Cycle 5
AR A G Ba Bd
AR A G
AR A
AR A
AR
W(64,1)
R(64,1)
R(64,1)
W(64,1)
W(64,1)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1
2
3
4
5
Bus Usage
● Arbiter➔ Grant 2 R(64,1) Bus usage mask (cycles: 6,7,8)➔ Evaluate
➢ 3 R(64,1): FAILED bus mask is (cycles: 7,9)➢ 4 W(64,1): FAILED bus mask is (cycles: 7,8,10)
READ Transaction: |AR|A|G|Ba|M|Br| WRITE Transaction: |AR|A|G|Ba|Bd|M|Bk|
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Embedded Systems 1 Davide Zoni
Cycle 6
AR A G Ba Bd M
AR A G Ba
AR A
AR A
AR A
W(64,1)
R(64,1)
R(64,1)
W(64,1)
W(64,1)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1
2
3
4
5
Bus Usage
● Arbiter➔ No grants Bus usage mask (cycles: 7,8)➔ Evaluate all the pending transaction that fail at least at cycle 8
READ Transaction: |AR|A|G|Ba|M|Br| WRITE Transaction: |AR|A|G|Ba|Bd|M|Bk|
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Embedded Systems 1 Davide Zoni
Cycle 7
AR A G Ba Bd M Bk
AR A G Ba M
AR A
AR A
AR A
W(64,1)
R(64,1)
R(64,1)
W(64,1)
W(64,1)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1
2
3
4
5
Bus Usage
● Arbiter➔ No grants Bus usage mask (cycles: 8)➔ Evaluate:
➢ 3 R(64,1): PASS bus mask (cycles:9,11)
READ Transaction: |AR|A|G|Ba|M|Br| WRITE Transaction: |AR|A|G|Ba|Bd|M|Bk|
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Embedded Systems 1 Davide Zoni
Cycle 8
AR A G Ba Bd M Bk
AR A G Ba M Br
AR A G
AR A
AR A
W(64,1)
R(64,1)
R(64,1)
W(64,1)
W(64,1)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1
2
3
4
5
Bus Usage
● Arbiter➔ Grant 3 R(64,1) Bus usage mask (cycles: 9,11)➔ Evaluate:
➢ 4 W(64,1) and 5 W(64,1): both FAIL bus mask (cycles: 10,11,13)
READ Transaction: |AR|A|G|Ba|M|Br| WRITE Transaction: |AR|A|G|Ba|Bd|M|Bk|
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Embedded Systems 1 Davide Zoni
Cycle 9
AR A G Ba Bd M Bk
AR A G Ba M Br
AR A G Ba
AR A
AR A
W(64,1)
R(64,1)
R(64,1)
W(64,1)
W(64,1)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1
2
3
4
5
Bus Usage
● Arbiter➔ No grant Bus usage mask (cycles: 11)➔ Evaluate:
➢ 4 W(64,1) and 5 W(64,1): both FAIL bus mask (cycles: 11,12,14)
READ Transaction: |AR|A|G|Ba|M|Br| WRITE Transaction: |AR|A|G|Ba|Bd|M|Bk|
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Embedded Systems 1 Davide Zoni
Cycle 10
AR A G Ba Bd M Bk
AR A G Ba M Br
AR A G Ba M
AR A
AR A
W(64,1)
R(64,1)
R(64,1)
W(64,1)
W(64,1)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1
2
3
4
5
Bus Usage
● Arbiter➔ No grant Bus usage mask (cycles: 11)➔ Evaluate:
➢ 4 W(64,1) : PASS bus mask (cycles: 12,13,15)
READ Transaction: |AR|A|G|Ba|M|Br| WRITE Transaction: |AR|A|G|Ba|Bd|M|Bk|
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Embedded Systems 1 Davide Zoni
Cycle 11
AR A G Ba Bd M Bk
AR A G Ba M Br
AR A G Ba M Br
AR A G
AR A
W(64,1)
R(64,1)
R(64,1)
W(64,1)
W(64,1)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1
2
3
4
5
Bus Usage
● Arbiter➔ Grant 4 W(64,1) Bus usage mask (cycles: 12,13,15)➔ Evaluate:
➢ 5 W(64,1) : FAILED bus mask (cycles: 13,14,16)
READ Transaction: |AR|A|G|Ba|M|Br| WRITE Transaction: |AR|A|G|Ba|Bd|M|Bk|
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Embedded Systems 1 Davide Zoni
Cycle 12
AR A G Ba Bd M Bk
AR A G Ba M Br
AR A G Ba M Br
AR A G Ba
AR A
W(64,1)
R(64,1)
R(64,1)
W(64,1)
W(64,1)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1
2
3
4
5
Bus Usage
● Arbiter➔ No Grant Bus usage mask (cycles: 13,15)➔ Evaluate:
➢ 5 W(64,1) : FAILED bus mask (cycles: 14,15,17)
READ Transaction: |AR|A|G|Ba|M|Br| WRITE Transaction: |AR|A|G|Ba|Bd|M|Bk|
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Embedded Systems 1 Davide Zoni
Cycle 13
AR A G Ba Bd M Bk
AR A G Ba M Br
AR A G Ba M Br
AR A G Ba Bd
AR A
W(64,1)
R(64,1)
R(64,1)
W(64,1)
W(64,1)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1
2
3
4
5
Bus Usage
● Arbiter➔ No Grant Bus usage mask (cycles: 15)➔ Evaluate:
➢ 5 W(64,1) : FAILED bus mask (cycles: 15,16,18)
READ Transaction: |AR|A|G|Ba|M|Br| WRITE Transaction: |AR|A|G|Ba|Bd|M|Bk|
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Embedded Systems 1 Davide Zoni
Cycle 14
AR A G Ba Bd M Bk
AR A G Ba M Br
AR A G Ba M Br
AR A G Ba Bd M
AR A
W(64,1)
R(64,1)
R(64,1)
W(64,1)
W(64,1)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1
2
3
4
5
Bus Usage
● Arbiter➔ No Grant Bus usage mask (cycles: )➔ Evaluate:
➢ 5 W(64,1) : PASS bus mask (cycles: 16,17,19)
READ Transaction: |AR|A|G|Ba|M|Br| WRITE Transaction: |AR|A|G|Ba|Bd|M|Bk|
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Embedded Systems 1 Davide Zoni
Cycle 15
AR A G Ba Bd M Bk
AR A G Ba M Br
AR A G Ba M Br
AR A G Ba Bd M Bk
AR A G
W(64,1)
R(64,1)
R(64,1)
W(64,1)
W(64,1)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1
2
3
4
5
Bus Usage
● Arbiter➔ Grant 5 W(64,1) Bus usage mask (cycles: 16,17,19)➔ Nothing to be evaluated:
READ Transaction: |AR|A|G|Ba|M|Br| WRITE Transaction: |AR|A|G|Ba|Bd|M|Bk|
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Embedded Systems 1 Davide Zoni
Cycle 16
AR A G Ba Bd M Bk
AR A G Ba M Br
AR A G Ba M Br
AR A G Ba Bd M Bk
AR A G Ba
W(64,1)
R(64,1)
R(64,1)
W(64,1)
W(64,1)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1
2
3
4
5
Bus Usage
● Arbiter➔ No Grant Bus usage mask (cycles: 17,19)➔ Nothing to be evaluated:
READ Transaction: |AR|A|G|Ba|M|Br| WRITE Transaction: |AR|A|G|Ba|Bd|M|Bk|
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Embedded Systems 1 Davide Zoni
Cycle 17
AR A G Ba Bd M Bk
AR A G Ba M Br
AR A G Ba M Br
AR A G Ba Bd M Bk
AR A G Ba Bd
W(64,1)
R(64,1)
R(64,1)
W(64,1)
W(64,1)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1
2
3
4
5
Bus Usage
● Arbiter➔ No Grant Bus usage mask (cycles: 19)➔ Nothing to be evaluated:
READ Transaction: |AR|A|G|Ba|M|Br| WRITE Transaction: |AR|A|G|Ba|Bd|M|Bk|
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Embedded Systems 1 Davide Zoni
Cycle 18
AR A G Ba Bd M Bk
AR A G Ba M Br
AR A G Ba M Br
AR A G Ba Bd M Bk
AR A G Ba Bd M
W(64,1)
R(64,1)
R(64,1)
W(64,1)
W(64,1)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1
2
3
4
5
Bus Usage
● Arbiter➔ No Grant Bus usage mask (cycles: 19)➔ Nothing to be evaluated:
READ Transaction: |AR|A|G|Ba|M|Br| WRITE Transaction: |AR|A|G|Ba|Bd|M|Bk|
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Embedded Systems 1 Davide Zoni
Cycle 19
AR A G Ba Bd M Bk
AR A G Ba M Br
AR A G Ba M Br
AR A G Ba Bd M Bk
AR A G Ba Bd M Bk
W(64,1)
R(64,1)
R(64,1)
W(64,1)
W(64,1)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1
2
3
4
5
Bus Usage
● Arbiter➔ No grants Bus usage mask (cycles:)➔ Nothing to be evaluated:
● Bus utilization is: 13/19 ~68%→
READ Transaction: |AR|A|G|Ba|M|Br| WRITE Transaction: |AR|A|G|Ba|Bd|M|Bk|
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Embedded Systems 1 Davide Zoni
Pipelined Bus with Variable Memory Latency
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Embedded Systems 1 Davide Zoni
Cycle 1
AR
AR
W(64,1)
R(64,1)
R(64,1)
W(64,2)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1
1
2
3
● Data/Address Bus is Split, width = 64 bit● Pipelined Bus Architecture + Variable memory Latency● Arbiter grants WRITE first FIFO order. Responses have precedence over request (Split Opt)● Transaction Shape (cycles) [NOTE memory latency is >= 1]:
➔ READ Transaction: |AR|A|G|Ba|M+|Br|➔ WRITE Transaction: |AR|A|G|Bad|M+|Bk|
● Notation & Symbols: AR arb req; A – arb stage; G – grant; Ba – bus address; Bd – bus data; M – Memory; Br – response; Bk – ack; Bad data+address
Bus Usage
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Embedded Systems 1 Davide Zoni
Cycle 2
AR A
AR A
AR
W(64,1)
R(64,1)
R(64,1)
W(64,2)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1
1
2
3
Bus Usage
● Arbiter➔ No grants Bus usage mask (cycles: )➔ Evaluate
➢ 1 W(64,1): PASS mask (cycles: >3)➢ The arbiter cannot set the complete mask since the memory latency is unknown➢ Wait for the end of the active transaction before activating the next one
READ Transaction: |AR|A|G|Ba|M+|Br| WRITE Transaction: |AR|A|G|Bad|M+|Bk|
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Embedded Systems 1 Davide Zoni
Cycle 3
AR A G
AR A
AR A
AR
W(64,1)
R(64,1)
R(64,1)
W(64,2)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1
1
2
3
Bus Usage
READ Transaction: |AR|A|G|Ba|M+|Br| WRITE Transaction: |AR|A|G|Bad|M+|Bk|
● Arbiter➔ Grant 1 W(64,1) Bus usage mask (cycles: > 3)➔ Evaluate all the pending transaction fails since they ask the bus after cycle 4
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Embedded Systems 1 Davide Zoni
Cycle 4
AR A G Bad
AR A
AR A
AR A
W(64,1)
R(64,1)
R(64,1)
W(64,2)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1
1
2
3
Bus Usage
READ Transaction: |AR|A|G|Ba|M+|Br| WRITE Transaction: |AR|A|G|Bad|M+|Bk|
● Arbiter➔ No grants Bus usage mask (cycles: > 4)➔ Evaluate all the pending transaction fails since they ask the bus after cycle 5
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Embedded Systems 1 Davide Zoni
Cycle 5
AR A G Bad M
AR A
AR A
AR A
W(64,1)
R(64,1)
R(64,1)
W(64,2)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1
1
2
3
Bus Usage
READ Transaction: |AR|A|G|Ba|M+|Br| WRITE Transaction: |AR|A|G|Bad|M+|Bk|
● Arbiter➔ No grants Bus usage mask (cycles: > 5)➔ Evaluate all the pending transaction fails since they ask the bus after cycle 6
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Embedded Systems 1 Davide Zoni
Cycle 6
AR A G Bad M Bk
AR A
AR A
AR A
W(64,1)
R(64,1)
R(64,1)
W(64,2)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1
1
2
3
Bus Usage
READ Transaction: |AR|A|G|Ba|M+|Br| WRITE Transaction: |AR|A|G|Bad|M+|Bk|
● Arbiter➔ No grants Bus usage mask (cycles:) [Arbiter observes the Bk that frees the bus]➔ Evaluate
➢ 3 W(64,2): PASS bus mask (cycles: >7)
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Embedded Systems 1 Davide Zoni
Cycle 7
AR A G Bad M Bk
AR A
AR A
AR A G
W(64,1)
R(64,1)
R(64,1)
W(64,2)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1
1
2
3
Bus Usage
READ Transaction: |AR|A|G|Ba|M+|Br| WRITE Transaction: |AR|A|G|Bad|M+|Bk|
● Arbiter➔ Grant 3 W(64,2) Bus usage mask (cycles: > 7)➔ Evaluate all the pending transaction fails since they ask the bus after cycle 8
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Embedded Systems 1 Davide Zoni
Cycle 8
AR A G Bad M Bk
AR A
AR A
AR A G Bad
W(64,1)
R(64,1)
R(64,1)
W(64,2)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1
1
2
3
Bus Usage
READ Transaction: |AR|A|G|Ba|M+|Br| WRITE Transaction: |AR|A|G|Bad|M+|Bk|
● Arbiter➔ No grants Bus usage mask (cycles: > 8)➔ Evaluate all the pending transaction fails since they ask the bus after cycle 9
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Embedded Systems 1 Davide Zoni
Cycle 9
AR A G Bad M Bk
AR A
AR A
AR A G Bad M
W(64,1)
R(64,1)
R(64,1)
W(64,2)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1
1
2
3
Bus Usage
READ Transaction: |AR|A|G|Ba|M+|Br| WRITE Transaction: |AR|A|G|Bad|M+|Bk|
● Arbiter➔ No grants Bus usage mask (cycles: > 9)➔ Evaluate all the pending transaction fails since they ask the bus after cycle 10
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Embedded Systems 1 Davide Zoni
Cycle 10
AR A G Bad M Bk
AR A
AR A
AR A G Bad M M
W(64,1)
R(64,1)
R(64,1)
W(64,2)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1
1
2
3
Bus Usage
READ Transaction: |AR|A|G|Ba|M+|Br| WRITE Transaction: |AR|A|G|Bad|M+|Bk|
● Arbiter➔ No grants Bus usage mask (cycles: > 10)➔ Evaluate all the pending transaction fails since they ask the bus after cycle 11
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Embedded Systems 1 Davide Zoni
Cycle 11
AR A G Bad M Bk
AR A
AR A
AR A G Bad M M Bk
W(64,1)
R(64,1)
R(64,1)
W(64,2)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1
1
2
3
Bus Usage
READ Transaction: |AR|A|G|Ba|M+|Br| WRITE Transaction: |AR|A|G|Bad|M+|Bk|
● Arbiter➔ No grants Bus usage mask (cycles:) [Arbiter observes the Bk that frees the bus]➔ Evaluate
➢ 1 R(64,1): PASS bus mask (cycles: >12)
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Embedded Systems 1 Davide Zoni
Cycle 12
AR A G Bad M Bk
AR A G
AR A
AR A G Bad M M Bk
W(64,1)
R(64,1)
R(64,1)
W(64,2)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1
1
2
3
Bus Usage
READ Transaction: |AR|A|G|Ba|M+|Br| WRITE Transaction: |AR|A|G|Bad|M+|Bk|
● Arbiter➔ Grant 1 R(64,1) Bus usage mask (cycles: >12)➔ Evaluate
➢ 2 R(64,1): FAIL bus mask (cycles: >13)
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Embedded Systems 1 Davide Zoni
Cycle 13
AR A G Bad M Bk
AR A G Ba
AR A
AR A G Bad M M Bk
W(64,1)
R(64,1)
R(64,1)
W(64,2)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1
1
2
3
Bus Usage
READ Transaction: |AR|A|G|Ba|M+|Br| WRITE Transaction: |AR|A|G|Bad|M+|Bk|
● Arbiter➔ No Grant Bus usage mask (cycles: >13)➔ Evaluate
➢ 2 R(64,1): FAIL bus mask (cycles: >14)
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Embedded Systems 1 Davide Zoni
Cycle 14
AR A G Bad M Bk
AR A G Ba M
AR A
AR A G Bad M M Bk
W(64,1)
R(64,1)
R(64,1)
W(64,2)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1
1
2
3
Bus Usage
READ Transaction: |AR|A|G|Ba|M+|Br| WRITE Transaction: |AR|A|G|Bad|M+|Bk|
● Arbiter➔ No Grant Bus usage mask (cycles: >14)➔ Evaluate
➢ 2 R(64,1): FAIL bus mask (cycles: >15)
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Embedded Systems 1 Davide Zoni
Cycle 15
AR A G Bad M Bk
AR A G Ba M Br
AR A
AR A G Bad M M Bk
W(64,1)
R(64,1)
R(64,1)
W(64,2)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1
1
2
3
Bus Usage
READ Transaction: |AR|A|G|Ba|M+|Br| WRITE Transaction: |AR|A|G|Bad|M+|Bk|
● Arbiter➔ No Grant Bus usage mask (cycles:) [Arbiter observes Br on the bus that ends the read tx]➔ Evaluate
➢ 2 R(64,1): PASS bus mask (cycles: >16)
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Embedded Systems 1 Davide Zoni
Cycle 16
AR A G Bad M Bk
AR A G Ba M Br
AR A G
AR A G Bad M M Bk
W(64,1)
R(64,1)
R(64,1)
W(64,2)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1
1
2
3
Bus Usage
● Arbiter➔ Grant 2 R(64,1) Bus usage mask (cycles: >16)➔ No pending transaction to be evaluated
READ Transaction: |AR|A|G|Ba|M+|Br| WRITE Transaction: |AR|A|G|Bad|M+|Bk|
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Embedded Systems 1 Davide Zoni
Cycle 17
AR A G Bad M Bk
AR A G Ba M Br
AR A G Ba
AR A G Bad M M Bk
W(64,1)
R(64,1)
R(64,1)
W(64,2)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1
1
2
3
Bus Usage
● Arbiter➔ No grants Bus usage mask (cycles: >17)
READ Transaction: |AR|A|G|Ba|M+|Br| WRITE Transaction: |AR|A|G|Bad|M+|Bk|
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Embedded Systems 1 Davide Zoni
Cycle 18
AR A G Bad M Bk
AR A G Ba M Br
AR A G Ba M
AR A G Bad M M Bk
W(64,1)
R(64,1)
R(64,1)
W(64,2)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1
1
2
3
Bus Usage
● Arbiter➔ No grants Bus usage mask (cycles: >18)
READ Transaction: |AR|A|G|Ba|M+|Br| WRITE Transaction: |AR|A|G|Bad|M+|Bk|
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Embedded Systems 1 Davide Zoni
Cycle 19
AR A G Bad M Bk
AR A G Ba M Br
AR A G Ba M Bd
AR A G Bad M M Bk
W(64,1)
R(64,1)
R(64,1)
W(64,2)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1
1
2
3
Bus Usage
● Arbiter➔ No grants Bus usage mask (cycles: )➔ Nothing to be Evaluated
● Bus utilization: 8/19 <50%→● Not determinism of the memory latency strongly affect the overall system performance● Not the memory delay but the determinism is essential
READ Transaction: |AR|A|G|Ba|M+|Br| WRITE Transaction: |AR|A|G|Bad|M+|Bk|
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Embedded Systems 1 Davide Zoni
Split Transaction, Pipelined Bus with Variable Memory Latency
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Embedded Systems 1 Davide Zoni
Cycle 1
AR
AR
W(64,1)
R(64,1)
R(64,1)
W(64,2)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1
1
2
3
● Data/Address Bus is Split, width = 64 bit● Pipelined+Split Bus Architecture + Variable memory Latency● Arbiter grants WRITE first FIFO order. Responses have precedence over request (Split Opt)● Transaction Shape (cycles) [NOTE mem latency is >=1 and each transaction has a req&resp part]:
➔ READ Transaction: |AR|A|G|Ba| M+ |AR|A|G|Br|➔ WRITE Transaction: |AR|A|G|Bad| M+ |AR|A|G|Bk|
● Notation & Symbols: AR arb req; A – arb stage; G – grant; Ba – bus address; Bd – bus data; M – Memory; Br – response; Bk – ack; Bad data+address
Bus Usage
44
Embedded Systems 1 Davide Zoni
Cycle 2
AR A
AR A
AR
W(64,1)
R(64,1)
R(64,1)
W(64,2)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1
1
2
3
Bus Usage
● Arbiter➔ No grant Bus usage mask (cycles: )➔ Evaluate:
➢ 1 W(64,1) : PASS bus mask (cycles: 4)
READ Transaction: |AR|A|G|Ba|M+|AR|A|G|Br|
WRITE Transaction: |AR|A|G|Bad|M+|AR|A|Bk|
45
Embedded Systems 1 Davide Zoni
Cycle 3
AR A G
AR A
AR A
AR
W(64,1)
R(64,1)
R(64,1)
W(64,2)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1
1
2
3
Bus Usage
● Arbiter➔ Grant 1 W(64,1) Bus usage mask (cycles: 4)➔ Evaluate:
➢ 1 R(64,1) : PASS bus mask (cycles: 5)
READ Transaction: |AR|A|G|Ba|M+|AR|A|G|Br|
WRITE Transaction: |AR|A|G|Bad|M+|AR|A|Bk|
46
Embedded Systems 1 Davide Zoni
Cycle 4
AR A G Bad
AR A G
AR A
AR A
W(64,1)
R(64,1)
R(64,1)
W(64,2)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1
1
2
3
Bus Usage
● Arbiter➔ Grant 1 R(64,1) Bus usage mask (cycles: 5)➔ Evaluate:
➢ 3 W(64,2) : PASS bus mask (cycles: 6)
READ Transaction: |AR|A|G|Ba|M+|AR|A|G|Br|
WRITE Transaction: |AR|A|G|Bad|M+|AR|A|Bk|
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Embedded Systems 1 Davide Zoni
Cycle 5
AR A G Bad M
AR A G Ba
AR A
AR A G
W(64,1)
R(64,1)
R(64,1)
W(64,2)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1
1
2
3
Bus Usage
● Arbiter➔ Grant 3 W(64,1) Bus usage mask (cycles: 6)➔ Evaluate:
➢ 2 R(64,1) : PASS bus mask (cycles: 7)
READ Transaction: |AR|A|G|Ba|M+|AR|A|G|Br|
WRITE Transaction: |AR|A|G|Bad|M+|AR|A|Bk|
48
Embedded Systems 1 Davide Zoni
Cycle 6
AR A G Bad M AR
AR A G Ba M
AR A G
AR A G Bad
W(64,1)
R(64,1)
R(64,1)
W(64,2)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1
1
2
3
Bus Usage
● Arbiter➔ Grant 2 R(64,1) Bus usage mask (cycles: 7)➔ Nothing to evaluate
READ Transaction: |AR|A|G|Ba|M+|AR|A|G|Br|
WRITE Transaction: |AR|A|G|Bad|M+|AR|A|Bk|
49
Embedded Systems 1 Davide Zoni
Cycle 7
AR A G Bad M AR A
AR A G Ba M AR
AR A G Ba
AR A G Bad M
W(64,1)
R(64,1)
R(64,1)
W(64,2)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1
1
2
3
Bus Usage
● Arbiter➔ No Grants Bus usage mask (cycles:)➔ Evaluate:
➢ Resp 1 W(64,1) : PASS bus mask (cycles: 9)
READ Transaction: |AR|A|G|Ba|M+|AR|A|G|Br|
WRITE Transaction: |AR|A|G|Bad|M+|AR|A|Bk|
50
Embedded Systems 1 Davide Zoni
Cycle 8
AR A G Bad M AR A G
AR A G Ba M AR A
AR A G Ba M
AR A G Bad M M
W(64,1)
R(64,1)
R(64,1)
W(64,2)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1
1
2
3
Bus Usage
● Arbiter➔ Grant resp 1 W(64,1) Bus usage mask (cycles: 9)➔ Evaluate:
➢ Resp 1 R(64,1) : PASS bus mask (cycles: 10)
READ Transaction: |AR|A|G|Ba|M+|AR|A|G|Br|
WRITE Transaction: |AR|A|G|Bad|M+|AR|A|Bk|
51
Embedded Systems 1 Davide Zoni
Cycle 9
AR A G Bad M AR A G Bk
AR A G Ba M AR A G
AR A G Ba M AR
AR A G Bad M M AR
W(64,1)
R(64,1)
R(64,1)
W(64,2)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1
1
2
3
Bus Usage
● Arbiter➔ Grant resp 1 R(64,1) Bus usage mask (cycles: 10)➔ Nothing to evaluate
READ Transaction: |AR|A|G|Ba|M+|AR|A|G|Br|
WRITE Transaction: |AR|A|G|Bad|M+|AR|A|Bk|
52
Embedded Systems 1 Davide Zoni
Cycle 10
AR A G Bad M AR A G Bk
AR A G Ba M AR A G Br
AR A G Ba M AR A
AR A G Bad M M AR A
W(64,1)
R(64,1)
R(64,1)
W(64,2)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1
1
2
3
Bus Usage
● Arbiter➔ No Grants Bus usage mask (cycles:)➔ Evaluate:
➢ Resp 3 W(64,2) : PASS bus mask (cycles: 12)
READ Transaction: |AR|A|G|Ba|M+|AR|A|G|Br|
WRITE Transaction: |AR|A|G|Bad|M+|AR|A|Bk|
53
Embedded Systems 1 Davide Zoni
Cycle 11
AR A G Bad M AR A G Bk
AR A G Ba M AR A G Br
AR A G Ba M AR A
AR A G Bad M M AR A G
W(64,1)
R(64,1)
R(64,1)
W(64,2)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1
1
2
3
Bus Usage
● Arbiter➔ Grant resp 3 W(64,2) Bus usage mask (cycles: 12)➔ Evaluate:
➢ Resp 2 R(64,1) : PASS bus mask (cycles: 13)
READ Transaction: |AR|A|G|Ba|M+|AR|A|G|Br|
WRITE Transaction: |AR|A|G|Bad|M+|AR|A|Bk|
54
Embedded Systems 1 Davide Zoni
Cycle 12
AR A G Bad M AR A G Bk
AR A G Ba M AR A G Br
AR A G Ba M AR A G
AR A G Bad M M AR A G Bk
W(64,1)
R(64,1)
R(64,1)
W(64,2)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1
1
2
3
Bus Usage
● Arbiter➔ Grant resp 2 R(64,1) Bus usage mask (cycles: 13)➔ Nothing to evaluate
READ Transaction: |AR|A|G|Ba|M+|AR|A|G|Br|
WRITE Transaction: |AR|A|G|Bad|M+|AR|A|Bk|
55
Embedded Systems 1 Davide Zoni
Cycle 13
AR A G Bad M AR A G Bk
AR A G Ba M AR A G Br
AR A G Ba M AR A G Br
AR A G Bad M M AR A G Bk
W(64,1)
R(64,1)
R(64,1)
W(64,2)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1
1
2
3
Bus Usage
● Arbiter➔ No Grant Bus usage mask (cycles:)
● Bus utilization: 8/13 ~61%→● Cut the memory non deterministic behavior away from the bus arbitration stage
READ Transaction: |AR|A|G|Ba|M+|AR|A|G|Br|
WRITE Transaction: |AR|A|G|Bad|M+|AR|A|Bk|
56
Embedded Systems 1 Davide Zoni
Pipelined Bus with Burst and Split Transaction Support
Variable Memory Latency
57
Embedded Systems 1 Davide Zoni
Cycle 1
AR
AR
W(128,2)
R(64,3)
R(128,3)
W(64,1)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1
1
2
3
● Data/Address Bus is Split, width = 64 bit● Pipelined+ Burst Mode + Split Bus Architecture + Variable memory Latency● Arbiter grants WRITE first FIFO order. Responses have precedence over request (Split Opt)● Transaction Shape (cycles) [NOTE mem latency is >=1 and each transaction has a req&resp part]:
➔ READ Transaction: |AR|A|G|Ba| M+ |AR|A|G|Br+|➔ WRITE Transaction: |AR|A|G|Bad+| M+ |AR|A|G|Bk|
● Notation & Symbols: AR arb req; A – arb stage; G – grant; Ba – bus address; Bd – bus data; M – Memory; Br – response; Bk – ack; Bad data+address
Bus Usage
58
Embedded Systems 1 Davide Zoni
Cycle 2
AR A
AR A
AR
W(128,2)
R(64,3)
R(128,3)
W(64,1)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1
1
2
3
Bus Usage
READ Transaction: |AR|A|G|Ba|M+|AR|A|G|Br+|
WRITE Transaction: |AR|A|G|Bad+|M+|AR|A|Bk|
● Arbiter➔ No grants Bus usage mask (cycles:)➔ Evaluate:
➢ 1 W(128,2): PASS bus mask (cycles: 4,5) [two cycles to write 128bit bus width 64bit]
59
Embedded Systems 1 Davide Zoni
Cycle 3
AR A G
AR A
AR A
AR
W(128,2)
R(64,3)
R(128,3)
W(64,1)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1
1
2
3
Bus Usage
READ Transaction: |AR|A|G|Ba|M+|AR|A|G|Br+|
WRITE Transaction: |AR|A|G|Bad+|M+|AR|A|Bk|
● Arbiter➔ Grant 1 W(128,2) Bus usage mask (cycles: 4,5)➔ Evaluate both read: FAIL due to a bus collision an cycle 5
60
Embedded Systems 1 Davide Zoni
Cycle 4
AR A G Bad
AR A
AR A
AR A
W(128,2)
R(64,3)
R(128,3)
W(64,1)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1
1
2
3
Bus Usage
READ Transaction: |AR|A|G|Ba|M+|AR|A|G|Br+|
WRITE Transaction: |AR|A|G|Bad+|M+|AR|A|Bk|
● Arbiter➔ No grants Bus usage mask (cycles: 5)➔ Evaluate:
➢ 3 W(64,1): PASS bus mask (cycles: 6)➢ The read transactions are eventually arbitrated later
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Embedded Systems 1 Davide Zoni
Cycle 5
AR A G Bad Bad
AR A
AR A
AR A G
W(128,2)
R(64,3)
R(128,3)
W(64,1)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1
1
2
3
Bus Usage
READ Transaction: |AR|A|G|Ba|M+|AR|A|G|Br+|
WRITE Transaction: |AR|A|G|Bad+|M+|AR|A|Bk|
● Arbiter➔ Grant 3 W(64,1) Bus usage mask (cycles: 6)➔ Evaluate:
➢ 1 R(64,3): PASS bus mask (cycles: 7)
62
Embedded Systems 1 Davide Zoni
Cycle 6
AR A G Bad Bad M
AR A G
AR A
AR A G Bad
W(128,2)
R(64,3)
R(128,3)
W(64,1)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1
1
2
3
Bus Usage
READ Transaction: |AR|A|G|Ba|M+|AR|A|G|Br+|
WRITE Transaction: |AR|A|G|Bad+|M+|AR|A|Bk|
● Arbiter➔ Grant 1 R(64,3) Bus usage mask (cycles: 7)➔ Evaluate:
➢ 2 R(128,3): PASS bus mask (cycles: 8)
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Embedded Systems 1 Davide Zoni
Cycle 7
AR A G Bad Bad M M
AR A G Ba
AR A G
AR A G Bad M
W(128,2)
R(64,3)
R(128,3)
W(64,1)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1
1
2
3
Bus Usage
READ Transaction: |AR|A|G|Ba|M+|AR|A|G|Br+|
WRITE Transaction: |AR|A|G|Bad+|M+|AR|A|Bk|
● Arbiter➔ Grant Bus usage mask (cycles: 8)➔ Nothing to evaluate
64
Embedded Systems 1 Davide Zoni
Cycle 8
AR A G Bad Bad M M AR
AR A G Ba M
AR A G Ba
AR A G Bad M AR
W(128,2)
R(64,3)
R(128,3)
W(64,1)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1
1
2
3
Bus Usage
READ Transaction: |AR|A|G|Ba|M+|AR|A|G|Br+|
WRITE Transaction: |AR|A|G|Bad+|M+|AR|A|Bk|
● Arbiter➔ No grants Bus usage mask (cycles:)➔ Nothing to evaluate:
65
Embedded Systems 1 Davide Zoni
Cycle 9
AR A G Bad Bad M M AR A
AR A G Ba M M
AR A G Ba M
AR A G Bad M AR A
W(128,2)
R(64,3)
R(128,3)
W(64,1)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1
1
2
3
Bus Usage
READ Transaction: |AR|A|G|Ba|M+|AR|A|G|Br+|
WRITE Transaction: |AR|A|G|Bad+|M+|AR|A|Bk|
● Arbiter➔ No grants Bus usage mask (cycles:)➔ Evaluate:
➢ Resp 1 W(128,2): PASS actual bus mask is empty
66
Embedded Systems 1 Davide Zoni
Cycle 10
AR A G Bad Bad M M AR A G
AR A G Ba M M M
AR A G Ba M M
AR A G Bad M AR A
W(128,2)
R(64,3)
R(128,3)
W(64,1)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1
1
2
3
Bus Usage
READ Transaction: |AR|A|G|Ba|M+|AR|A|G|Br+|
WRITE Transaction: |AR|A|G|Bad+|M+|AR|A|Bk|
● Arbiter➔ Grant resp 1 W(128,2) Bus usage mask (cycles: 11)➔ Evaluate:
➢ Resp 3 W(64,1): PASS bus mask (cycles: 12)
67
Embedded Systems 1 Davide Zoni
Cycle 11
AR A G Bad Bad M M AR A G Bk
AR A G Ba M M M AR
AR A G Ba M M M
AR A G Bad M AR A G
W(128,2)
R(64,3)
R(128,3)
W(64,1)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1
1
2
3
Bus Usage
READ Transaction: |AR|A|G|Ba|M+|AR|A|G|Br+|
WRITE Transaction: |AR|A|G|Bad+|M+|AR|A|Bk|
● Arbiter➔ Grants resp 3 W(64,1) Bus usage mask (cycles: 12)➔ Nothing to evaluate:
68
Embedded Systems 1 Davide Zoni
Cycle 12
AR A G Bad Bad M M AR A G Bk
AR A G Ba M M M AR A
AR A G Ba M M M AR
AR A G Bad M AR A G Bk
W(128,2)
R(64,3)
R(128,3)
W(64,1)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1
1
2
3
Bus Usage
READ Transaction: |AR|A|G|Ba|M+|AR|A|G|Br+|
WRITE Transaction: |AR|A|G|Bad+|M+|AR|A|Bk|
● Arbiter➔ No grants Bus usage mask (cycles:)➔ Evaluate:
➢ Resp 1 R(64,3): PASS used bus mask is empty
69
Embedded Systems 1 Davide Zoni
Cycle 13
AR A G Bad Bad M M AR A G Bk
AR A G Ba M M M AR A G
AR A G Ba M M M AR A
AR A G Bad M AR A G Bk
W(128,2)
R(64,3)
R(128,3)
W(64,1)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1
1
2
3
Bus Usage
READ Transaction: |AR|A|G|Ba|M+|AR|A|G|Br+|
WRITE Transaction: |AR|A|G|Bad+|M+|AR|A|Bk|
● Arbiter➔ Grant resp 1 R(64,3) Bus usage mask (cycles: 14)➔ Evaluate:
➢ Resp 2 R(128,3): PASS bus mask (cycles: 15,16)
70
Embedded Systems 1 Davide Zoni
Cycle 14
AR A G Bad Bad M M AR A G Bk
AR A G Ba M M M AR A G Br
AR A G Ba M M M AR A G
AR A G Bad M AR A G Bk
W(128,2)
R(64,3)
R(128,3)
W(64,1)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1
1
2
3
Bus Usage
READ Transaction: |AR|A|G|Ba|M+|AR|A|G|Br+|
WRITE Transaction: |AR|A|G|Bad+|M+|AR|A|Bk|
● Arbiter➔ Grant resp 2 R(128,3) Bus usage mask (cycles:15,16)➔ Nothing to evaluate
71
Embedded Systems 1 Davide Zoni
Cycle 15
AR A G Bad Bad M M AR A G Bk
AR A G Ba M M M AR A G Br
AR A G Ba M M M AR A G Br
AR A G Bad M AR A G Bk
W(128,2)
R(64,3)
R(128,3)
W(64,1)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1
1
2
3
Bus Usage
READ Transaction: |AR|A|G|Ba|M+|AR|A|G|Br+|
WRITE Transaction: |AR|A|G|Bad+|M+|AR|A|Bk|
● Arbiter➔ No grants Bus usage mask (cycles: 16)➔ Nothing to evaluate:
72
Embedded Systems 1 Davide Zoni
Cycle 16
AR A G Bad Bad M M AR A G Bk
AR A G Ba M M M AR A G Br
AR A G Ba M M M AR A G Br Br
AR A G Bad M AR A G Bk
W(128,2)
R(64,3)
R(128,3)
W(64,1)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1
1
2
3
Bus Usage
READ Transaction: |AR|A|G|Ba|M+|AR|A|G|Br+|
WRITE Transaction: |AR|A|G|Bad+|M+|AR|A|Bk|
● Arbiter➔ No grants Bus usage mask (cycles:)➔ Nothing to evaluate:
● Bus utilization: 10/16 62.5%→● The bus is not used at cycles 9 and 10:
➔ high memory latency ➔ no one is waiting for the bus
