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Embedded SystemsSerial Peripheral Interface Bus

Ian McCrumSchool of

Engineering

From Wikipedia, the free encyclopedia

The Serial Peripheral Interface or SPI bus is a synchronous serial data link, a de facto standard, named by Motorola, that operates in full duplex mode. It is used for short distance, single master communication, for example in embedded systems, sensors, and SD cards.Devices communicate in master/slave mode where the master device initiates the data frame. Multiple slave devices are allowed with individual slave select lines. Sometimes SPI is called a four-wire serial bus, contrasting with three-, two-, and one-wire serial buses. SPI is often referred to as SSI (Synchronous Serial Interface).

• Full duplex• Unidirectional lines• Fast, much faster than I2C• Completely flexible – you write your own

protocol• Very simple hardware – 3 or 4 pins (or less)• Low power• Useful micro-micro links

Typical devices• Most microcontrollers, and it can be

bitbanged if not built-in• Sensors; temperature, pressure, gyros,

accelerometers, (see www.sparkfun.com or www.adafruit.com )

• ADCs, DACs, audio codecs, ethernet, usb, Wifi and other communication systems.

• Memory: MMC and SD cards use SPI

Manufacturer List with thanks to Martin Schwerdtfeger at http://www.mct.net/faq/spi.html#device

Note the Master generates the clock, it also assert the Slave Select, on ordinary SPI peripherals that acts as a chip select so one way of having multiple devices is to have separate chip selects for each one.

Each slave not selected must ignore SCLK and MOSI (Master Out,Slave In) and not drive MISO which is usally tristate. Note that names differ, microchip use SDO and SDI for serial data out and in. (Microchip processors can be either masters or slaves so these names are better)

Alternatively daisychain them all together into a single SPI super-peripheral.

If using SPI to link controllers together where each can be master or slave then any controller receiving SSBAR (i.e low means “select-slave”) will accept an external clock.

From Wikipedia, the free encyclopedia

From Wikipedia, the free encyclopedia

A typical setup for 8 bit devices, you can have bigger device shift registers. 12 and 16 are common. (PIC16 allows 8 bits, PIC32 has 8,16 or 32 and a continuous stream)

Real devices can use the clock in different ways, they can ignore extra clocks, they can send back more bits than they receive, read the datasheets carefully.

Sometimes a device will have an extra output that can be used to interrupt the master to signal they need attention, or an alarm has occurred (real time clock or a temperature sensor for instance)

The PIC32 has up to 32 bits internally, but is buffered with a FIFO and can seamlessly concatenate queued words together. It uses the same hardware for Streaming audio using the I2S protocol and can also generate continous streams of PCM bits whereas the PIC16F has a single 8 bit shift register.

From Wikipedia, the free encyclopedia

• As well as shift register length, the previous diagram implies what goes in, comes out. A real peripheral will accept one n bit word and simultaneously generate another, different n bit word.

• An ADC for instance will accept a command byte while sending an ADC result. The result is the PREVIOUS conversion since these takes time.

• Receiving a previous word means you often discard the very first word so that you can get in sync. Be careful!

From Wikipedia, the free encyclopedia

If a slave is not selected must ignore SCLK and SDO / MOSI (Master Out Slave In) and not drive SDI / MISO which is usually tristate

Microchip as an SS but you can repurpose it for general i/o. PIC32 allows either SDO or SDI or neither to be reallocated to general i/o

Here the shift registers are joined in a long snake, whilst the hardware is simple the software is complex – imagine if everything is 8 bit. The master sends out 8 bits to slave 1, but gets an answer from slave 3! If the master is 32 bits it gets bit easier…

Other protocols use this idea, e.g JTAG

SPI using daisy

chaining

SPI with individual Slave(chip)

selectsFrom http://www.mct.net/faq/spi.html 6/11/14 From http://www.mct.net/faq/spi.html 6/11/14

Clock Polarity and phase• There are 4 variation of the SDO and SCLK. SS can be active low

(typically) or high, some devices require a falling edge; be carefull!• The polarity determines the initial, resting, state of the SCLK• The phase determines if the data is stable and valid on the rising

edge, or the falling edge of the clock.• The PIC32 has control bits called CKE to set the edge and CKP to set

the polarity. See SPIxCON and SPIxCON2• CKP = 1 means idle state is high, active state is low• CKE = 1 means serial output data changes on the transition from

active clock state to idle clock state.• In other words, data leaving the master is stable on the rising edge

of the clock, incoming data will be sampled on the falling edge.• Other manufacturers use different names, e.g CPOL and CPHA.

http://www.byteparadigm.com/applications/introduction-to-i2c-and-spi-protocols/?/article/AA-00255/22/Introduction-to-SPI-and-IC-protocols.html on 6/11/14

Real PIC32MX hardware

Real PIC32MX hardware

Real PIC32MX hardware

PIC32MX1xx/2xx SFRs

Reference manual states;23.3.3.1MASTER MODE OPERATION (interrupts disabled after reset)Perform the following steps to set up the SPI module for the Master mode operation:1.Disable the SPI interrupts in the respective IECx register.2.Stop and reset the SPI module by clearing the ON bit. SPI1CONbits.ON=03.Clear the receive buffer. Dummy=SPI1BUF4.Clear the ENHBUF bit (SPIxCON<16>) if using Standard Buffer mode or set the bit if using Enhanced Buffer mode.5.If SPI interrupts are not going to be used, skip this step and continue to step 5. Otherwise the following additional steps are performed:a) Clear the SPIx interrupt flags/events in the respective IFSx register.b) Write the SPIx interrupt priority and subpriority bits in the respective IPCx register.c) Set the SPIx interrupt enable bits in the respective IECx register.6.Write the Baud Rate register, SPIxBRG. (9bits) SPI1BRG=0xxx7.Clear the SPIROV bit (SPIxSTAT<6>). SPI1STATbits.SPIOV=08.Write the desired settings to the SPIxCON register with MSTEN (SPIxCON<5>) = 1. (SPI1CONbits.MSTEN=1; SPI1CONbits.SMP=1; SPI1CONbits.CKE=?; SPI1CONbits.CKP=?)9.Enable SPI operation by setting the ON bit (SPIxCON<15>). SPI1CONbits.ON=1

10.Write the data to be transmitted to the SPIxBUF register. Transmission (and reception) will start as soon as data is written to the SPIxBUF register.

Hence

char SPI1_transfer( char b){ // this a “GET-PUT” routine.// write to shift register to begin transmission

SPI1BUF = b; // wait for transfer to completewhile( !SPI1STATbits.SPIRBF);

return SPI1BUF; // read the shift register value}

void SPI1_initialise( void){ // assumes just after a reset ..0000uint32_t dummy;SPI1CONbits.ON=0;dummy = SPI1BUF;SPI1BRG=1;// 13 bits, formula is PBCLK/(2*(SPI1BRG+1)), // so if PBCLK = 40Mhz, this is 10MHzSPI1STATbits.SPIOV=0;SPI1CONbits.MSTEN=1;SPI1CONbits.SMP=1;SPI1CONbits.CKE=?; SPI1CONbits.CKP=?SPI1CONbits.ON=1;}

Driving shift registers from SPIThe 74HC595 is a cheap 8 bit serial in and parallel out shift register, it will work off 3.3 volts and suits the PIC32MX nicely. It can be driven by bit-banging, or by using SPI.

The Dual in line plastic package (DIP or DIL) is 36p, the small outline soic package costs 26p ( http://www.Farnell.co.uk )

It is buffered, i.e. there is an 8 bit shift register and an 8 bit output latch so you can hold a steady pattern in the output latch while you shift in the new byte, then with one fell swoop update all 8 outputs at once, or bypass one chip and pass data to another, down the chain.

This 16 pin chip can be cascaded, it has 4 control signals to worry about (and Din & Dout) It is made by several manufacturers who often name pins differently.

Data is shifted on the positive-going transitions of the shift register clock input The data in each register is transferred to the storage register on a positive-going transition of the storage register clock input – we can use the cessation of a “chip select” to cause this. So the “chip select goes low whilst we do an 8 bit clock of new data.

The output enable and clear are not needed here, keep OEBAR low and SRCLR high so that the output is enabled but the shift register is not cleared.

If you have more than one device you can choose how to

drive each

http://www.gammon.com.au/forum/?id=11518 (10/11/14)

From http://www.mct.net/faq/spi.html 6/11/14 From http://www.mct.net/faq/spi.html 6/11/14

SDO

SCLKCSBAR

Note: the shift register clock SRCLK is called SH here, and the Register clock RCLK is called ST (strobe).

Data is shifted on the positive-going transitions of the shift register clock input

Hence we want the data to be shifted out of the PIC on the negative going edge so that it is stable for the positive edge to enter the shift register.

Working out clock polarity and Phase

The data in each register is transferred to the storage register on a positive-going transition of the storage register clock input – we can use the cessation of a “chip select” to cause this. So the “chip select goes low whilst we do an 8 bit clock of new data.

We will need a spare pin to drive the “chip select” (RCLK or STROBE), low and then going high once 8 bits have been shifted in. It is convenient to go low prior to the SPI transfer and then go high once the SPIRBF indicates 8 clocks have happened

a 11b 7c 4d 2e 1f 10g 5

Wiring up 4 seven segment displays to a SPI PORT (a bad design – but pedagogical…)

SDO

SCLK

CSBAR

3.3V

GND

NB, wire pin 16 to 3.3V and pin 8 to Ground on both chips

P1

P16

P8

P9

12 9 8 6

I²C

http://www.byteparadigm.com/applications/introduction-to-i2c-and-spi-protocols/?/article/AA-00255/22/Introduction-to-SPI-and-IC-protocols.html

I²C is a multi-master protocol that uses 2 signal lines. The two I²C signals are called ‘serial data’ (SDA) and ‘serial clock’ (SCL). There is no need of chip select (slave select) or arbitration logic. Virtually any number of slaves and any number of masters can be connected onto these 2 signal lines and communicate between each other using a protocol that defines:– 7-bits slave addresses: each device connected to the bus has got such a unique address;– data divided into 8-bit bytes– a few control bits for controlling the communication start, end, direction and for an acknowledgment mechanism.The data rate has to be chosen between 100 kbps, 400 kbps and 3.4 Mbps, respectively called standard mode, fast mode and high speed mode. Some I²C variants include 10 kbps (low speed mode) and 1 Mbps (fast mode +) as valid speeds.Physically, the I²C bus consists of the 2 active wires SDA and SCL and a ground connection (refer to figure 4). The active wires are both bi-directional. The I2C protocol specification states that the IC that initiates a data transfer on the bus is considered the Bus Master. Consequently, at that time, all the other ICs are regarded to be Bus Slaves

http://www.byteparadigm.com/applications/introduction-to-i2c-and-spi-protocols/?/article/AA-00255/22/Introduction-to-SPI-and-IC-protocols.html

http://www.byteparadigm.com/applications/introduction-to-i2c-and-spi-protocols/?/article/AA-00255/22/Introduction-to-SPI-and-IC-protocols.html

First, the master will issue a START condition. This acts as an ‘Attention’ signal to all of the connected devices. All ICs on the bus will listen to the bus for incoming data.Then the master sends the ADDRESS of the device it wants to access, along with an indication whether the access is a Read or Write operation (Write in our example). Having received the address, all IC’s will compare it with their own address. If it doesn’t match, they simply wait until the bus is released by the stop condition (see below). If the address matches, however, the chip will produce a response called the ACKNOWLEDGE signal.Once the master receives the acknowledge, it can start transmitting or receiving DATA. In our case, the master will transmit data. When all is done, the master will issue the STOP condition. This is a signal that states the bus has been released and that the connected ICs may expect another transmission to start any moment.When a master wants to receive data from a slave, it proceeds the same way, but sets the RD/nWR bit at a logical one. Once the slave has acknowledged the address, it starts sending the requested data, byte by byte. After each data byte, it is up to the master to acknowledge the received data

http://www.byteparadigm.com/applications/introduction-to-i2c-and-spi-protocols/?/article/AA-00255/22/Introduction-to-SPI-and-IC-protocols.html

http://www.byteparadigm.com/applications/introduction-to-i2c-and-spi-protocols/?/article/AA-00255/22/Introduction-to-SPI-and-IC-protocols.html

http://www.byteparadigm.com/applications/introduction-to-i2c-and-spi-protocols/?/article/AA-00255/22/Introduction-to-SPI-and-IC-protocols.html

At the physical layer, both SCL and SDA lines are open-drain I/Os with pull-up resistors (refer to figure 4). Pulling such a line to ground is decoded as a logical zero, while releasing the line and letting it flow is a logical one. Actually, a device on a I²C bus ‘only drives zeros’.Here we come to where I²C is truly elegant. Associating the physical layer and the protocol described above allow flawless communication between any number of devices, on just 2 physical wires.For example, what happens if 2 devices are simultaneously trying to put information on the SDA and / or SCL lines?At electrical level, there is actually no conflict at all if multiple devices try to put any logic level on the I²C bus lines simultaneously. If one of the drivers tries to write a logical zero and the other a logical one, then the open-drain and pull-up structure ensures that there will be no shortcut and the bus will actually see a logical zero transiting on the bus. In other words, in any conflict, a logic zero always ‘wins’.The bus physical implementation also allows the master devices to simultaneously write and listen to the bus lines. This way, any device is able to detect collisions. In case of a conflict between two masters (one of them trying to write a zero and the other one a one), the master that gains the arbitration on the bus will even not be aware there has been a conflict: only the master that looses will know – since it intends to write a logic one and reads a logic zero. As a result, a master that looses arbitration on a I²C will stop trying to access the bus. In most cases, it will just delay its access and try the same access later.

http://www.byteparadigm.com/applications/introduction-to-i2c-and-spi-protocols/?/article/AA-00255/22/Introduction-to-SPI-and-IC-protocols.html

Moreover, the I²C protocol also helps at dealing with communication problems. Any device present on the I²C listens to it permanently. Potential masters on the I²C detecting a START condition will wait until a STOP is detected to attempt a new bus access. Slaves on the I²C bus will decode the device address that follows the START condition and check if it matches theirs. All the slaves that are not addressed will wait until a STOP condition is issued before listening again to the bus. Similarly, since the I²C protocol foresees active-low acknowledge bit after each byte, the master / slave couple is able to detect their counterpart presence. Ultimately, if anything else goes wrong, this would mean that the device ‘talking on the bus’ (master or slave) would know it by simply comparing what it sends with what is seen on the bus. If a difference is detected, a STOP condition must be issued, which releases the bus.Additionally, I²C has got some advanced features, like extended bus addressing, clock stretching and the very specific 3.4 Mbps high speed mode