Modelling Networked Embedded Systems: From … WS at DATE06...2 ARTIST2ARTIST2 Embedded Systems DesignSoftware/Hardware architecture Bus RTOS CPU I/O Int Bus-CTRL Timer Timer drivers

1

ARTIST2ARTIST2 Embedded Systems Design

Modelling Networked Embedded Systems: Modelling Networked Embedded Systems:

From From MPSoCMPSoC to Sensor Networksto Sensor Networks

Jan MadsenJan MadsenTechnical University of DenmarkTechnical University of Denmark

http://www.artist-embedded.org/FP6/

ARTIST Workshop at DATE’06W4: “Design Issues in Distributed,

Communication-Centric Systems”


Multiprocessor System-on-Chip��

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2


Software/Hardware architecture

Bus

RTOS

CPU

I/O Int Bus-CTRL

TimerTimer

drivers

RTOS-APIs

Periphery

Cache

mem

private

private

private

private

shar

edHardware

SoftwareHW/SW

Plattform

application

ce1

application

pe1

��


Platform-based design

1

34

2

a b c

1 2 os

3

4

a b cos os mapping

L1 L2

L3

R1 R2 R3

3


Outline

�The �� framework� basic model

�Modelling multiprocessor System-on-Chip� Simple multi media terminal

�Modelling wirekess sensor networks� Simple examples

�Summary


�� objectives

�System-level modeling framework�Bridging,

� Application� RTOS � Execution platform

Processing elementsNoC

�Supporting� System-level analysis� Early design space exploration

��

4


System-level analysis

�Consequences of� RTOS selection

scheduling, synchronization and resource allocation policies� Processor selection

General purpose, semicustom or dedicated hardware� Network selection

topologies and communication protocols.� Task mapping to processors

software or hardware�On

� Performance� Area� Memory profile� Power� …


Basic �� model

rtosa

rtosb

rtosc

rtosd

network

5


Uni-processor ...

rtosa

Framework to experiment withdifferent RTOS strategiesFocus on analysis of timingand resource sharing

Abstract software model, i.e. no behavior/functionalityEasy to create tasks and implement RTOS modelsBased on SystemC


System model

�Task messages:� ready

� finished

�RTOS commands:� run

� preempt

� Resume

rtos

6


Cp>0 !run

!resume& Cr>0

!preempt

Task model

idle

running preempt

ready

run

Cp==0 ready

preempt

resume

Cr==0finish


Scheduling model�Aim: Simple way to describe the

scheduling algorithm�Scheduler should only handle one

message at a time�Schedulers:

� RM� DM� EDF� static

rtosscheduler

7


Data dependencies

synchronizer

scheduler


Resource sharing

synchronizer

scheduler

allocator

8


Multi-processors

synchronizer

allocatorallocator

schedulerscheduler

Communication latency?


Communication modelling

1 2

a b 1

2

a

b

Fully interconnected or point-to-pointAllows concurrent communication

9



1 2

a b1

2

a

b

��

mx

Bus-basedShared resource

bus



1 2

a b

1

2

a

b

�� R1

L1

R2

L2

R3

Torus networkConcurrent, shared and multi-hop

L1 L2

L3

R1 R2 R3

10


�� Framework

� �� Simulation framework based on SystemC� �� PE module:

� Application� OS� IO ports (OCP 2.0 interface)� IO device drivers

� �� Communication module:� Network topology and protocol� Network adapters� IO ports (OCP 2.0 interface)

� Applications of ��:� MPSoC (NoC exploration)� Wireless sensor networks� Automotive systems (TT vs. ET)� Dynamic reconfiguration

IO a

dapt

or m

odel

IO a

dapt

or m

odel

IO a

dapt

or m

odel

App

licat

ion

RTO

S

App

licat

ion

RTO

S

App

licat

ion

RTO

S

ττττIO

Master

OCP IO device

Slave

HWmodel

Synchronnizer

ResourceAllocator

Scheduler

τ1

τn

. . .

App

licat

ion

RTO

S

SoC communication interface (OCP)

Intermediate adapter1

Intermediate adapter2

Intermediate adapterN

SoC allocator

SoC scheduler

SoCresource usage

buffer

IO port1 IO port2 IO portN

SoC communication interface (i.e. OCP 2.0)

. . .

SoC communication layer model

IO a

dapt

or m

odel

IO a

dapt

or m

odel

IO a

dapt

or m

odel


Outline




�Summary

11


Design of a hand-held multimedia terminal

0

1

2

3

4

5

JPEG Decoder

20 ms34GSM Decoder

20 ms53GSM Encoder

25 ms16MP3 Decoder

500 ms6JPEG Decoder

250 ms5JPEG Encoder

Deadline# tasksApplication

[Application from Marcus Schmitz, TU Linkoping]


Case study: Execution platform

10

GPP1

6.6

GPP2

2.5

FPGA

2.525Frequency (MHz)

ASICGPP0PE

os

t

t

PE1

os

t

t

os

t

t

t

PE2 PE3 PE4

t

PE5 PE6

EDF (Early Deadline First)RM (Rate Monotonic)OS

t

t

12


Case study: Architectures

Arch2

Arch1

GPP0ASICASICASICASICASICIP Type

RM-----OS

321318151521Tasks

EDF-EDF-EDF-OS

GPP0ASICGPP0ASICFPGAASICIP Type

RM-RM-RM-OS

321918151515Tasks

Arch4

GPP0ASICGPP0ASICFPGAASICIP Type

321918151515Tasks

Arch3

241818211518Tasks

-RMRM-RMRMOS

ASICFPGAFPGAASICFPGAGPP0IP Type

PE6PE5PE4PE3PE2PE1


Processor UtilizationArch1 Arch2 Arch3 Arch4

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Bus Contention


Memory Profile of Arch3

Time (µµµµs)

32-b

it W

ords

(Ins

truc

tion

+ D

ynam

ic M

emor

y)

14


Simple memory model 1 2 3

1 2 3

Mem

ory

@P

E1

PM( 2)PM( 1)

PM( 3)

PDM( 1)PDM( 2) PDM( 3)

X

Y

X Y

PE

1

X Y

PM( 1)

PM( 3)

PDM( 1) PDM( 3)x

y

1 3

Mem

ory

@P

E1

2

io

io

io

X Y

PE1

bus

PE2 io

io io

time

time

time

time

(a)

(b)

(c)

ττ τX Y


Memory Profile

Arch1 Arch2

Time (µµµµs) Time (µµµµs)

32-b

it W

ords

(Ins

truc

tion

+ D

ynam

ic M

emor

y)

~ 40%

15


Outline




�Summary


Modelling wireless sensor networks

rtosa

rtosb

rtosc

rtosd

network

16


Sensor network model


Sensor node model

17


Energy modeling


Communication example

τ1

sτ2

τ4

rτ3

Send node

Receive node

synch.

allocator

scheduler

synch.

allocator

scheduler

WirelessNetwork

τ5

18


Modeling radio communication

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CSMA Protocol for sending

idlebackoff

carriersense

Tx pre-amble

Txdata

send

!sendbo_counter>0

bo_counter==0

!channel clearchannel clear &cs_counter==0

cs_counter>0

pr_counter>0

pr_counter==0

data_counter>0

data_counter==0

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Modeling radio communication

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Sensor network example

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0us 100us 200us 300us 400us 500us 600us 700us 800us 900us

Node1_Processing_Task

Node1_Receive_Protocol

Node1_Receive_Task

Node1_Send_Protocol

Node1_Send_Task


Node2_Receive_Task


Node3_Receive_Task

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

11 0 1 0 1 0 1 0 1 0 1 0 1 0

00 0 0 0 0 0 0 0

2 1 3 4 0

4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 0

11 0 1 0 1 0 1 0 1 2 3 0 1 0 1 0 1 0 1 0 1 0 1 0

00 0 0 0 0 4 4 4 4 4 0 0 0 0 0 0 0

11 0 1 0 1 0 1 0 1 2 3 0 1 0 1 0 1 0 1 0 1 0 1 0

00 0 0 0 0 4 4 4 4 4 0 0 0 0 0 0 0

Example 1: Simple broadcast��

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Example 2: Radio interference

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Node1_Receive_Task

Node1_Send_Protocol

Node1_Send_Task


Node2_Receive_Task

Node2_Send_Protocol

Node2_Send_Task


Node3_Receive_Task


Node4_Receive_Task


Node5_Receive_Task

11 0 1 0 1 0 1 0 1 2 3 0

00 0 0 0 0 4 4 4 4 4 4 4 4 0

2 1 3 4 0

4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 0

11

00

2 1 2 1 2 1 3 4 0

4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 0

11 0 1 0 1 0 1 0 1 2 3 0 1 0 1 0 1 0 1 0 1 2 3 0

00 0 0 0 0 4 4 4 4 4 0 0 0 0 0 4 4 4 4 4 0

11 0 1 0 1 0 1 0 1 2 3 0 1 0 1 0 1 0 1 0 1 2 3 0

00 0 0 0 0 4 4 4 4 4 0 0 0 0 0 4 4 4 4 4 0

11 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2 3 0

00 0 0 0 0 0 0 0 0 0 0 4 4 4 4 4 4 0

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Example 3: Network routing


Example 3: Routing��

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0 300 us 601 us 901 us

1 0 1 0 1 2 3 0 1 0 1 0 1 0 1 0

0 0 0 4 4 4 4 4 4 4 0 0 0 0 0

0 0

0

0

1 3 4 0

4 4 4 4 4 4 4 4 4 4 4 4 4 4 0

1 0 1 0 1 2 3 0 1 0 1 0 1 0 1 0 1 0

0 0 0 4 4 4 4 4 0 0 0 0 0 0

0 0

0 2 1 3 4 0

0 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 0

1 0 1 0 1 2 3 0 1 0 1 2 3 0 1 0 1 0 1 0 1 0

0 0 0 4 4 4 4 4 0 0 4 4 4 4 4 4 4 4 0 0 0 0 0

TimeNode3_Receive_Protocol=1

Node3_Receive_Task=0

Node3_Routing_Task=0

Node3_Forward_Protocol=0

Node3_Forward_Task=0

Node3_Send_Protocol=1

Node3_Send_Task=2

Node2_Receive_Protocol=0







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Example 3: Battery shortage��

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Node 2 runs out of battery

0 321 us 643 us 965 us

1 0 1 0 1 2 0 1 0 1 0 1 0 1 0 1 0 1

0 0 0 4 4 0 0 0 0 0 0

0

0

0

1 3 4 0

4 4 4 4 4 4 4 4 4 4 4 4 4 4 0

1 0 1 0 1 2 3 0 1

0 0 0 4 4 4 4 4 0 5

0 0 5

0 2 1 3 4

0 4 4 4 4 4 4 4 4 4 4 + 5

1 0 1 0 1 2 3 0 1 0 1 2 0 1 0 1 0 1 0 1 0 1 0 1

0 0 0 4 4 4 4 4 0 0 4 4 4 0 0 0 0 0 0

imeNode3_Receive_Protocol=1





Node3_Send_Protocol=2

Node3_Send_Task=2









Summary �System-level modeling framework�Bridging,

� Application� RTOS � Execution platform

Processing elementsNoC

�Supporting� System-level analysis� Early design space exploration

�Applications� MPSoC� Wireless Sensor Networks

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Summary

�Work in progress� Mixed-level simulation together with MPARM from

University of Bologna (Luca Benini)� Linking to formal modelling based on UppAal from

University of Aalborg (Kim G. Larsen)� Mixed TT and ET communication models and hierarchical

schedulers together with Technical University of Linkoping(Petru Eles)

�To be used in the Hogthrob project� Thursdays Keynote on Wireless Sensor Networks


Acknowledgements

�ARTS� Shankar Mahadevan (PhD student)� Kashif Virk (PhD student)� Michael Storgaard (MSc. student)� Knud Hansen (MSc. student)� Mercury Gonzalez (MSc. student)

Documents

Modelling Networked Embedded Systems: From … WS at DATE06...2 ARTIST2ARTIST2 Embedded Systems DesignSoftware/Hardware architecture Bus RTOS CPU I/O Int Bus-CTRL Timer Timer drivers