EE 5900 Advanced Algorithms for Robust VLSI CAD , Spring 2009

EE 5900 Advanced Algorithms for Robust VLSI CAD, Spring 2009

Static Timing Analysis and Gate Sizing

Circuit Delay

* PJF- *Circuit DelayDelay Evaluation1. Gate delay2. Interconnect delay

Circuit Delay

* PJF- *Circuit Delay1. Problem DescriptionGiven a pair of pins, compute pin-to-pin delay and possibly output waveform

CellCellDelayInterconnectCell

Circuit Delay

* PJF- *Circuit DelayCircuit ModelFor an inverterCsinkCsink

Circuit Delay

* PJF- *Circuit DelaySink CapacitanceGate capacitance, input capacitanceGiven for standard cellsCan be found using SPICEApply an AC voltage and measure currentAverage over a range of frequencyI

Circuit Delay

* PJF- *Circuit DelayCapacitance ModelCtotalRdRdRC

Circuit Delay

* PJF- *Circuit DelayInterconnect Delay: Elmore DelayElmore is used as the delay on interconnectEasy to compute

Circuit Delay

* PJF- *Circuit DelayExample111111114231m1_1= 4, m1_2= 7, m1_3= 8, m1_4= 8

Circuit Delay

* PJF- *Circuit DelayApplication of Elmore DelayGoodClosed form expression, easy to computeUseful in circuit design such as gate sizing and buffering.BadInaccurateNot useful for timing verification

Circuit Delay

* PJF- *Circuit DelayCircuit Delay Evaluation - Two ComponentsCell delay + interconnect delayCell delay is computed using RC or K-factorInterconnect delay is computed using Elmore delayCellCellInterconnect

Circuit Delay

* PJF- *Circuit DelayStatic vs. Dynamic Timing AnalysisStatic timing analysisFastConsider all pathsPessimism by considering false paths which are never exercised

Dynamic timing analysis ( simulation )Depends on input stimulus vectorsDo not report timing on false pathsWith large number of testing vectorsAccurateSlow

Circuit Delay

*Wire and Gate Models

Circuit Delay

Step by Step* PJF- *Circuit DelayModel combinational circuit using the previous slideStarting from primary input gates, compute the arrival time (AT) at each gate, i.e., compute gate delay and interconnect delayIn order to compute the AT at a gate, the ATs of all its input gates need to be computedRepeat the above process until the ATs at all primary output gates are computed

Circuit Delay

* PJF- *Circuit DelayExample of Static Timing AnalysisArrival time (AT): input -> output, take max

13245

Circuit Delay

C=1,R=1

C=5,R=2

C=5,R=2

C=4,R=2

C=10,R=5

unit wire resistance=1unit wire capacitance=1

10

2

2

12

2

AT=0

AT=267

AT=75

AT=145

AT=22

AT=31

AT=0

AT=121

AT=21

AT=167

AT=267

AT=12

Take the Max

AT=31

* PJF- *Circuit DelayTiming OptimizationArrival time (AT): input -> output, take max Should we size up this gate to improve timing?

Circuit Delay

C=1,R=1

C=5,R=2

C=5,R=2

C=4,R=2

C=10,R=5

unit wire resistance=1unit wire capacitance=1

10

2

2

12

2

AT=0

AT=267

AT=75

AT=145

AT=22

AT=31

AT=0

AT=121

AT=21

AT=167

AT=267

AT=12

Take the Max

AT=31

* PJF- *Circuit DelayTiming Optimization- IISuppose that we have a gate (with same gate type) doubling its width. We roughly have C=10, R=1.If we change the gate with this new one, what is the new delay? Does not change

Circuit Delay

C=1,R=1

C=10,R=1

C=5,R=2

C=4,R=2

C=10,R=5

unit wire resistance=1unit wire capacitance=1

10

2

2

12

2

AT=0

AT=267

AT=75

AT=145

AT=16

AT=31

AT=0

AT=121

AT=21

AT=167

AT=267

AT=6

Take the Max

AT=31

* PJF- *Circuit DelayTiming Optimization- IIISuppose that we have a gate (with same gate type) doubling its width. We roughly have C=8, R=1.If we change the gate with this new one, what is the new delay?

Circuit Delay

C=1,R=1

C=5,R=2

C=5,R=2

C=8,R=1

C=10,R=5

unit wire resistance=1unit wire capacitance=1

10

2

2

12

2

AT=0

AT=257

AT=65

AT=149

AT=38

AT=43

AT=0

AT=125

AT=25

AT=171

AT=257

AT=20

Take the Max

AT=43

* PJF- *Circuit DelayTiming Optimization- IVThis optimization is called gate sizing. Change the gate size (width) in optimization.1. Given multiple choices (implementations) per gate type, find a gate implementation at each gate such that the circuit timing is minimized.2. Given multiple choices per gate type, find a gate implementation at each gate such that the circuit timing satisfies the target and the total gate area/power is minimized

Circuit Delay

Problem Definition of Gate SizingGiven a timing (delay) target, use smallest power/area gates to meet the timing targetIn general, smaller power -> larger timing, smaller timing -> larger power.*

Circuit Delay

*Delay due to Gate SizingSuppose that unit width gate capacitance is c and unit width gate resistance is r. Given gate size wi,Gate size wi: R r/wi, C cwiDelay is a function of RCDelay RiCj wi/wj

Circuit Delay

*Wire and Gate Models

Circuit Delay

*Combinatorial Circuit ModelGate size variables x1, x2, x3Delay on each gate depends on xDriversLoadsx2x3x1a3a4a5a1a2D1D3D2D5D4D7D6D9D8D10a6a7

Circuit Delay

*Path DelayExpress path delay in terms of component delayA component can be a gate or a wireDelay D for each componentArrival time a for some components

Circuit Delay

*Gate SizingPower/area minimization under delay constraints:

This can be solved efficiently using gpsolve

Circuit Delay

Gate Sizing using GPSOLVEFollow the steps in gatesizing.m*

Circuit Delay

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