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Rob
ust
Low
Power
VLSI
Robust
LowPower
VLSI
Low-Power BIST (Built-In Self Test) Overview
10/31/2014 Harsh N. Patel
Rob
ust
Low
Power
VLSI 2
Motivation
Source:herculsecyborg.blogspot.com
⇒ Leads to energy constraint design
Rob
ust
Low
Power
VLSI 3
Source: N. Verma, IEEE TED 2008
Motivation
Sub-threshold region
Rob
ust
Low
Power
VLSI 4
⇒ Higher occupancy of the memory leads higher energy dissipation at SoC level
⇒ SRAM required to be operated in the sub-threshold region for energy constrained design.
Source: M.H. Abu-Rahma, Springer 2013
Motivation
Rob
ust
Low
Power
VLSI 5
MotivationBut lowering supply voltage leads to cell write failures.
⇒ Failures at lower supply necessitate the requirement of some kind of assist technique to “help” SRAM cell in writing in to it.
Rob
ust
Low
Power
VLSI 6
SRAM overview Conventional SRAM cell
Write Operation
Write Assist Techniques
Choice of Evaluation Metrics
Results
Conclusion
Outline
Rob
ust
Low
Power
VLSI 7
• Static Random Access Memory• Data stored on cross-coupled inverters and being accessed
by pass transistors.• Data storage is Static in nature, i.e. nodes are connected to
VDD/GND through PMOS/NMOS as switch.
SRAM: Overview
n2n1
BL BLBWL WL
n2n1
VDD
VSS
IN OUT
Rob
ust
Low
Power
VLSI 8
Conventional 6 Transistors Cell
BL BLBWL WL
n1
VSS
VDD
PG1 PG2
PD1 PD2
PU1 PU2
n2
SRAM: Overview
Rob
ust
Low
Power
VLSI 9
BL= 0 BLB= ’1'WL WL
‘1’
VSS
VDD
‘OFF’ ‘ON’
‘ON’ ‘OFF’
‘0’
SRAM Cell- Write OperationPerforming write-0 operation to the cell holding ‘1’
Write 0 Operation for a 6T cell holding ‘1’
BL= 0 BLB= ’1'WL WL
‘0’
VSS
VDD
‘ON’ ‘OFF’
‘OFF’ ‘ON’
‘1’
Rob
ust
Low
Power
VLSI 10
BL= 0 BLB= ’1'WL WL
‘1’
VSS
VDD
‘ON’ ‘ON’
‘OFF’ ‘ON’
‘ON’ ‘OFF’
‘0’
Performing write-0 operation to the cell holding ‘1’
Write-Assist Techniques
Weakening the PMOS:- VDD Lower (↓ VS)- VSS Raise (↑ VG)
Strengthening the NMOS:- WL Boosting (↑ VG)- Negative BL (↓ VS)
Write Assist: Theory
𝑰 𝑫∝𝑾𝑳𝒆
𝑽 𝑮𝑺
𝒏𝑽 𝒕𝒉𝒆𝒓𝒎𝒂𝒍
Rob
ust
Low
Power
VLSI 11
Write Assist Techniques
Write Assist Techniquesa) VDD Lowering b) VSS Raising c) WL Boosting d) Negative Bitline
VSS Raise0 + Δ
0 - Δ Neg BL
VDD
VSSBLB
BL
WL
VDD
VSS
BLB
BL
WL
VDD
VSS
BLB ‘1’
0BL
WL
0‘1’
0‘1’
‘1’‘1’ - Δ VDD Lower
(a) (b)
0‘1’
0
WL BoostWL + Δ
(c) (d)
‘1’ VDD
VSSBLB
BL
0‘1’
‘1’
‘1’
‘1’WL
Rob
ust
Low
Power
VLSI 12
Choice of Assist Evaluation MetricsDynamic (time dependent ) - Static (time independent ) write ability:
Dynamic Write-Ability :The time by which write operation should be completed; speed of the operation is main concern.
Critical wordline pulse (WLcrit): minimum width of word-line(WL) pulse during which the bitcell changes state.
BL= 0
WL
‘1’
VDD
‘ON’
‘ON’
< WLcrit ≥ WLcrit
Source: [1]
Rob
ust
Low
Power
VLSI 13
Choice of Assist Evaluation MetricsDynamic (time dependent ) - Static (time independent ) write ability:
Static Write-Ability (Write Margin):The speed of operation is not prime goal;but the functionality at possible lower supply
“An ability of the cell to get flipped before the word line voltage reaches to the maximum voltage of WL signal”
BL= 0
WL
‘1’
VDD
‘ON’
‘ON’
Write Margin (WM)
n1
n2
VDD
WL Sweep
Rob
ust
Low
Power
VLSI 14
Results: Test SetupTool : Technology Agnostic Simulation Environment (TASE)
Technology : commercial 130nm node.
Tests : Write Margin
Measurement : Apply assist with step of 10-20-30% of supply.
e.g. for VDD=0.5V10% VDD Lowering VDD = 0.45V10% VSS raising VSS = 0.05V10% WL Boosting WL = 0.55V10% NegBL BL(holding 0) = -0.05V
Rob
ust
Low
Power
VLSI 15
Results: Write Margin
Write Margin across supply: Without Assist
Min. possible operating
supply voltage(Vmin)
Supply Voltage (V)
Vmin reduced to 0.5V from 0.7V
WL Boosting brings Vmin down
to VDD=0.3V
Take away Points:
- WL Boosting is the optimal assist technique to scale the supply down to VDD=0.3V
- WL Boosting increases Write Margin by ~7X across the supply voltages.
Rob
ust
Low
Power
VLSI 16
Metric for evaluation vary based on application of device.
Assist techniques help to reduce Vmin for SRAM.
Vmin can be reduced to VDD=0.3V using 30% of WL boosting
WL boosting improves WM across the supply voltages by ~7X.
Conclusion
Rob
ust
Low
Power
VLSI 17
1) V. Chandra, R. Aitken, C. Pietrzyk, “On the Efficacy of Write Assist Techniques in Low Voltage Nanoscale SRAMs”, DATE, 2010.
2) R. W. Mann, J. Wang, S. Nalam, S. Khanna, G. Braceras, H. Pilo and B.H. Calhoun, “Impact of circuit assist methods on margin and performance in 6T SRAM” Solid State Electron., Nov 2010.
3) B. Calhoun, A. Wang, A. Chandrakasan, “Modeling and Sizing for Minimum Energy Operation in Subthreshold Circuit. JSSC, 2005.
4) Verma, N.; Chandrakasan, A.P., “A 256 kb 65 nm 8T Subthreshold SRAM Employing Sense-Amplifier Redundancy” IEEE Journal of Solid-State Circuits, JSSC 2007.
5) Boley, James ; Chandra, Vikas ; Aitken, Robert ; Calhoun, Benton, “Leveraging sensitivity analysis for fast, accurate estimation of SRAM dynamic write VMIN”, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013
References
Rob
ust
Low
Power
VLSI 18
Thank You!
Questions?
Rob
ust
Low
Power
VLSI 19
ION/IOFF Improvement
Backup
Rob
ust
Low
Power
VLSI 20
Points withWM > 150mV andWrite Delay < 2
Backup
