EE 5900 Advanced Algorithms for Robust VLSI CAD, Spring 2009 Combinational Circuits

EE 5900 Advanced EE 5900 Advanced Algorithms for Robust Algorithms for Robust VLSI CAD, Spring 2009VLSI CAD, Spring 2009

Combinational CircuitsCombinational Circuits

OverviewOverview

Combinational CircuitCombinational Circuit Chip Design stylesChip Design styles

Full-custom designFull-custom design Cell library based designCell library based design Programmable Logic ArrayProgrammable Logic Array

2023.04.22 PJF- 2Combinational Logic


Combinational CircuitsCombinational Circuits A combinational circuit consists of A combinational circuit consists of

logic gates whose outputs, at logic gates whose outputs, at any any timetime, are determined by combining , are determined by combining the values of the inputs.the values of the inputs.

For For nn input variables, there are 2 input variables, there are 2nn possible binary input combinations.possible binary input combinations.

For each binary combination of the For each binary combination of the input variables, there is one possible input variables, there is one possible output.output.


Combinational Circuits Combinational Circuits (cont.)(cont.)

Hence, a combinational circuit can be Hence, a combinational circuit can be described by:described by:

1.1. A truth table that lists the output values for A truth table that lists the output values for each combination of the input variables, oreach combination of the input variables, or

2.2. mm Boolean functions, one for each output Boolean functions, one for each output variable.variable.

CombinationalCircuit

n-inputs m-outputs••• •••


Combinational vs. Sequential Combinational vs. Sequential CircuitsCircuits

Combinational circuits are Combinational circuits are memory-less.memory-less. Thus, the output value depends ONLY on Thus, the output value depends ONLY on the current input values.the current input values.

Sequential circuits consist of Sequential circuits consist of combinational logic as well as memory combinational logic as well as memory elements (used to store certain circuit elements (used to store certain circuit states). Outputs depend on BOTH current states). Outputs depend on BOTH current input values and previous input values input values and previous input values (kept in the storage elements).(kept in the storage elements).


Combinational vs. Sequential Combinational vs. Sequential CircuitsCircuits


n-inputs m-outputs(Depend only on inputs)


n-inputs

m-outputs

StorageElementsNext

statePresentstate

Sequential Circuit

Combinational Circuit


Important Design ConceptsImportant Design Concepts

Modern digital design deals with various Modern digital design deals with various methodsmethods and and toolstools that are used to design that are used to design and verify complex circuits and systems. and verify complex circuits and systems.

Concepts:Concepts: Design HierarchyDesign Hierarchy Computer-Aided-Design (CAD) toolsComputer-Aided-Design (CAD) tools Hardware Description Languages (HDLs)Hardware Description Languages (HDLs)


Design HierarchyDesign Hierarchy

““ Divide-and-Conquer”Divide-and-Conquer” approach approach used to cope with the challenges of used to cope with the challenges of designing complex circuits and designing complex circuits and systems (many times in the order of systems (many times in the order of millions of gates).millions of gates).

Circuit is broken into Circuit is broken into blocksblocks, , repetitively.repetitively.


Design Hierarchy Design Hierarchy Example: 9-input odd function (for counting # of 1 in Example: 9-input odd function (for counting # of 1 in

inputs)inputs)


Why is Hierarchy useful?Why is Hierarchy useful?

Reduces the complexity required to Reduces the complexity required to design and represent the overall design and represent the overall schematic of the circuit.schematic of the circuit.

ReuseReuse of blocks is possible. Identical of blocks is possible. Identical blocks can be used in various places blocks can be used in various places in a design, or in different designs.in a design, or in different designs.


Reusable Functions and Reusable Functions and CADCAD Whenever possible, we try to decompose a complex Whenever possible, we try to decompose a complex

design into common, design into common, reusablereusable function blocks function blocks These blocks areThese blocks are

verified and well-documentedverified and well-documented placed in libraries for future useplaced in libraries for future use


Integrated CircuitsIntegrated Circuits Integrated circuit (a chip) is a semiconductor Integrated circuit (a chip) is a semiconductor

crystal (most often silicon) containing the crystal (most often silicon) containing the electronic components for the digital gates and electronic components for the digital gates and storage elements which are interconnected on the storage elements which are interconnected on the chip.chip.

Terminology - Levels of chip integrationTerminology - Levels of chip integration SSISSI ( (small-scale integratedsmall-scale integrated) - fewer than 10 gates) - fewer than 10 gates MSIMSI ( (medium-scale integratedmedium-scale integrated) - 10 to 100 gates) - 10 to 100 gates LSILSI ( (large-scale integratedlarge-scale integrated) - 100 to thousands of gates) - 100 to thousands of gates VLSIVLSI ( (very large-scale integratedvery large-scale integrated) - thousands to 100s of ) - thousands to 100s of

millions of gatesmillions of gates


Technology ParametersTechnology Parameters Specific gate implementation technologies are Specific gate implementation technologies are

characterized by the following parameters: characterized by the following parameters: Fan-inFan-in – the number of inputs available on a gate – the number of inputs available on a gate Fan-outFan-out – the number of standard loads driven by a gate – the number of standard loads driven by a gate

outputoutput Cost for a gateCost for a gate - a measure of the contribution by the gate to - a measure of the contribution by the gate to

the cost of the integrated circuitthe cost of the integrated circuit Propagation DelayPropagation Delay – The time required for a change in the – The time required for a change in the

value of a signal to propagate from an input to an outputvalue of a signal to propagate from an input to an output Power DissipationPower Dissipation – the amount of power drawn from the – the amount of power drawn from the

power supply and consumed by the gatepower supply and consumed by the gate


Propagation DelayPropagation Delay Propagation delay is the time for a change on an input of a Propagation delay is the time for a change on an input of a

gate to propagate to the output.gate to propagate to the output. Delay is usually measured at the 50% point with respect to Delay is usually measured at the 50% point with respect to

the H and L output voltage levels.the H and L output voltage levels. High-to-low falling and low-to-high rising delays.High-to-low falling and low-to-high rising delays.


Propagation Delay ExamplePropagation Delay Example

IN (

volt

s)O

UT

(vo

lts)

t (ns)1.0 ns per division


Chip Design StylesChip Design Styles Full custom - the entire design of the chip down to the smallest Full custom - the entire design of the chip down to the smallest

detail of the layout is performeddetail of the layout is performed Expensive, its timing and power is hard to analyzeExpensive, its timing and power is hard to analyze only for dense, fast chips with high sales volumeonly for dense, fast chips with high sales volume

Standard cell - blocks have been design ahead of time or as part Standard cell - blocks have been design ahead of time or as part of previous designsof previous designs

Intermediate cost Intermediate cost Less density and speed compared to full customLess density and speed compared to full custom

Gate array - regular patterns of gate transistors that can be used Gate array - regular patterns of gate transistors that can be used in many designs built into chip - only the interconnections in many designs built into chip - only the interconnections between gates are specific to a designbetween gates are specific to a design

Lowest costLowest cost Less density compared to full custom and standard cellLess density compared to full custom and standard cell Prototype designPrototype design The base of FPGAThe base of FPGA


Cell LibrariesCell Libraries CellCell - a pre-designed primitive block - a pre-designed primitive block Cell libraryCell library - a collection of cells available for - a collection of cells available for

design using a particular implementation design using a particular implementation technologytechnology

Cell characterizationCell characterization - a detailed specification - a detailed specification of a cell for use by a designerof a cell for use by a designer


Cell Library Based Design Cell Library Based Design ProcedureProcedure

1.1. SpecificationSpecification Write a specification for the circuit if one is not already Write a specification for the circuit if one is not already

availableavailable

2.2. FormulationFormulation Derive a truth table or initial Boolean equations that Derive a truth table or initial Boolean equations that

define the required relationships between the inputs define the required relationships between the inputs and outputs, if not in the specificationand outputs, if not in the specification

3.3. OptimizationOptimization Draw a logic diagram or provide a netlist for the Draw a logic diagram or provide a netlist for the

resulting circuit using ANDs, ORs, and invertersresulting circuit using ANDs, ORs, and inverters


Cell Library Based Design Cell Library Based Design ProcedureProcedure

4.4. Technology MappingTechnology Mapping Map the logic diagram to the Map the logic diagram to the

implementation technology selectedimplementation technology selected Map to CMOSMap to CMOS

5.5. EvaluationEvaluation Evaluate the timing and power Evaluate the timing and power


Design ExampleDesign Example1.1. Specification Specification

BCD to Excess-3 code converterBCD to Excess-3 code converter Transforms BCD code for the decimal digits to Transforms BCD code for the decimal digits to

Excess-3 code for the decimal digitsExcess-3 code for the decimal digits BCD code words for digits 0 through 9: 4-bit BCD code words for digits 0 through 9: 4-bit

patterns 0000 to 1001, respectivelypatterns 0000 to 1001, respectively Excess-3 code words for digits 0 through 9: 4-Excess-3 code words for digits 0 through 9: 4-

bit patterns consisting of 3 (binary 0011) added bit patterns consisting of 3 (binary 0011) added to each BCD code wordto each BCD code word


Design Example Design Example (continued)(continued)2.2. FormulationFormulation

Conversion of 4-bit codes can be most easily Conversion of 4-bit codes can be most easily formulated by a truth tableformulated by a truth table

VariablesVariables- - BCDBCD:: A,B,C,D A,B,C,D

VariablesVariables- - Excess-3Excess-3 W,X,Y,Z W,X,Y,Z

Don’t CaresDon’t Cares- BCD 1010- BCD 1010 to 1111 to 1111

Input BCD A B C D

Output Excess-3 WXYZ

0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 0 0 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 0 0 1 1 1 0 1 0 1 1 0 0 0 0 1 1 0 1 0 0 1 0 1 1 1 1 0 1 0 1 0 0 0 1 0 1 1 1 0 0 1 1 0 1 1


Design Example Design Example (continued)(continued)

3.3. OptimizationOptimizationa.a. K-mapsK-maps

W = A + BC + BDW = A + BC + BD

X = C + D + BX = C + D + B

Y = CD + Y = CD +

Z = Z =

B

C

D

A

0 1 3 2

4 5 7 6

12 13 15 14

8 9 11 10

1

11

1

X X X

X X

X

1

B

C

D

A

0 1 3 2

4 5 7 6

12 13 15 14

8 9 11 10

1

11

1

X X X

X X

X

1

B

C

D

A

0 1 3 2

4 5 7 6

12 13 15 14

8 9 11 10

1 1

1

1

X X X

X X

X

1

B

C

D

A

0 1 3 2

4 5 7 6

12 13 15 14

8 9 11 10

1 1

1

X X X

X X

X

1

1

w

z y

xB CDB

CD

D


Design Example Design Example (continued)(continued)

3.3. Optimization (continued)Optimization (continued) Multiple-level using transformationsMultiple-level using transformations

W = A + BC + BDW = A + BC + BDX = C + D + BX = C + D + BY = CD + Y = CD + Z = Z =

Perform extraction, finding factor:Perform extraction, finding factor: TT11 = C + D = C + D

W = A + BTW = A + BT11 X = TX = T11 + B + BY = CD + Y = CD + Z =Z =

B CDBCD

D

B C DCD

D

2023.04.22Combinational Logic

Design Example Design Example (continued)(continued)4.4. Technology Mapping Technology Mapping

Map with a library containing inverters and 2-input Map with a library containing inverters and 2-input NAND, and then map it to a CMOS based circuitNAND, and then map it to a CMOS based circuit

Z

A

B

CD

W

X

Y

Z


NAND Mapping ExampleNAND Mapping ExampleA

B

C

D

F

E

(a)

AB

C7

5

1

6

2

4

9

X

Y

38DE

F

(b)

AB

C

D

E

F

(d)

X

5

5

7

6Y

(c)

OI

Timing AnalysisTiming Analysis

Use static timing analysis which has Use static timing analysis which has been covered.been covered.


Apr 22, 2023

PJF - 27Combinational Logic

Programmable Logic ArrayProgrammable Logic Array The set of functions to be implemented is first transformed The set of functions to be implemented is first transformed

to product termsto product terms Since output inversion is available, terms can implement Since output inversion is available, terms can implement

either a function or its complementeither a function or its complement

Apr 22, 2023


Programmable Logic Array Programmable Logic Array ExampleExample

To implementTo implement F1= A’B’C+A’BC’+AB’C’=(AB+AC+BC+A’B’C’)’F1= A’B’C+A’BC’+AB’C’=(AB+AC+BC+A’B’C’)’ F2=AB+AC+BCF2=AB+AC+BC

Apr 22, 2023


Programmable Logic Array Programmable Logic Array ExampleExample

XFuse intactFuse blown

01

F1

F2

A

B

C

C B AC B A

1

2

4

3

X X

X X

X X

X XX

X

X

X X

X

X

X

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X

Documents

EE 5900 Advanced Algorithms for Robust VLSI CAD, Spring 2009 Combinational Circuits