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EDK Lab for PowerPC and MicroBlaze. Paul Glover, Winnie Hsu Global Services Division. Agenda. Introduction (30min) Embedded System Tools Overview Labs (90min) Lab1(a) Intro to EDK Flow - PowerPC Track Lab1(b) Intro to EDK Flow - MicroBlaze Track - PowerPoint PPT Presentation
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EDK Lab for PowerPC and MicroBlaze
Paul Glover, Winnie HsuGlobal Services Division
“Xilinx Confidential”
AgendaIntroduction (30min)
Embedded System Tools Overview
Labs (90min)
Lab1(a) Intro to EDK Flow - PowerPC Track
Lab1(b) Intro to EDK Flow - MicroBlaze Track
Lab2 Web Server Design Example (Optional)
Lab3 Using SGP as MHS Editor (Preview)
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EDK GlossaryTools
EDK = Embedded development Kit. PlatGen = Platform generator. Uses MHS file to create an implementation netlist of a bus-based subsystem.LibGen = Library generator. Uses MHS/MSS files, SW libraries and source files to generate executable images.SimGen = Simulation generator. Uses MHS/MVS files to configure and generate simulation related package including simulation models, HDL wrappers, script, etc.XMD = Xilinx Microprocessor Debug
Platform Specification Format (PSF)MHS = Microprocessor Hardware Specification.MSS = Microprocessor Software Specification.MVS = Microprocessor Verification Specification.MPD = Microprocessor Peripheral Description.PAO = Peripheral Analyze OrderBBD = Black-Box DefinitionMDD = Microprocessor Driver Description.
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Embedded System Design Consists ofHardware designSoftware designHW / SW co-verification (Simulation & Debug)
Xilinx Platform Studio (XPS)Provides project management interfacesCoordinates tool elements with well defined interfaces
XPSSoftware
Design
HardwareDesign
Debug
Simulation
HW-SW Co-VerificationHW-SW Partitioning
Embedded Development Flow
“Xilinx Confidential”
Embedded System Design Consists ofHardware designSoftware designHW / SW co-verification (Simulation & Debug)
XPSSoftware
Design
HardwareDesign
Debug
Simulation
HW-SW Co-VerificationHW-SW Partitioning
Embedded Development Flow
“Xilinx Confidential”
Hardware FlowHW Development Flow
1. Specify Processor, Bus & Peripherals
2. Automatic HardwarePlatform Generation
3. Xilinx Implementation Flow
HW Configuration
Bitstream
Download to FPGAPPC405
PLB /Arbiter
PLBEMC
OPBGPIO
OPBUART
PLB2OPBBridgeOPB2PLBBridge
BRAMBlock
OPB /Arbiter
JTAGCNTL
PLBBRAM
I/F
MHS
PlatGen
MHSMicroprocessor Hardware SpecificationA template that describes hardware structure
PlatGenUses MHS file to create the hardware platform
Xflow /ProjNav
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Example MHS Format# Global Ports
PARAMETER VERSION = 2.0.0
PORT sys_clk = sys_clk, DIR=INPUT
PORT system_reset = system_reset, DIR=INPUT
PORT leds = leds, DIR = INOUT, VEC = [0:7]
...
BEGIN plb_v34
PARAMETER HW_VER = 1.01.a
PARAMETER INSTANCE = myplb
PORT PLB_Clk = sys_clk
PORT SYS_Rst = sys_bus_reset
PARAMETER C_DCR_INTFCE = 0
END
BEGIN plb2opb_bridge
PARAMETER INSTANCE = myplb2opb
PARAMETER C_RNG0_BASEADDR = 0xA0000000
PARAMETER C_RNG0_HIGHADDR = 0xA03FFFFF
BUS_INTERFACE SPLB = myplb
BUS_INTERFACE MOPB= myopb
...
BEGIN ppc405
PARAMETER INSTANCE = PPC405_i
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE IPLB = myplb
BUS_INTERFACE DPLB = myplb
PORT CPMC405CLOCK = sys_clk
PORT PLBCLK = sys_clk
PORT CPMC405CORECLKINACTIVE = net_gnd
….
PPC405
PLB2OPBBridge
PLBBRAM
……
PLBBRAM
OPB GPIO
FFFFFFFF
FFFF8000
A0000000
A00001FF
PLB
… …
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How to Create an MHS?
* This new feature in SGP-beta has not been completed yet.
XPS GUIGenerate MHS TemplateFill in the connections in the editor
* SysGenPro Block-like Entry
LAB1 LAB3
!
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What Does PlatGen Do?
MHS File
MPDPAOBDD
MPDPAOBDD
MPDPAOBDD
MPDPAOBDD
Processor(s)Processor(s)
Processor IP(s)Processor IP(s) PlatGen
HDL Wrappers, NGC, BMM, Synth SCR/PRJ,
MPD &others
MPD &others
PlatGen Generates HDL wrappersNGC(s)BMM File, to initialize BRAMs in the later stepsSynthesis scripts / project file
MPDPAOBDD
MPDPAOBDD
MYIP and LogicMYIP and Logic
MPD &others
HW Development Flow
1. Specify Processor, Bus & Peripherals
2. Automatic HardwarePlatform Generation
3. Xilinx Implementation Flow
HW Configuration
Bitstream
Download to FPGA
MHS
PlatGen
Xflow/ISE NPL
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Q: How to Add My Peripheral?
Design Processor Peripherals Understand common bus protocols (OPB / PLB / DCR)Understand logic elements you need (addr decode, regs, etc..) Understand PlatGen supported signals and generics
Incorporate into PlatGen FlowCreate MPD,PAO, BBD (if applicable)Search pathDirectory tree
PPC405PLB /
Arbiter
PLBEMC
OPBGPIO
OPBUART
PLB2OPBBridge
OPB2PLBBridge
BRAMBlock
OPB /Arbiter
JTAGCNTL
PLBBRAM
I/F ?
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Q: How to Export the System into a Larger Design?
PPC405PLB /
Arbiter
PLBEMC
OPBGPIO
OPBUART
PLB2OPBBridge
OPB2PLBBridge
BRAMBlock
OPB /Arbiter
JTAGCNTL
PLBBRAM
I/F
XPS Exports a Project Navigator Project (NPL) File
??LAB1
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Embedded System Design Consists ofHardware designSoftware designHW / SW co-verification (Simulation & Debug)
XPSSoftware
Design
HardwareDesign
Debug
Simulation
HW-SW Co-VerificationHW-SW Partitioning
Embedded Development Flow
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Software Flow
1. Specify Software Architecture
Executable in on-chipmemory
Download to Board
SW Development Flow
Executable in off-chip memory
?
2. Automatic SoftwareBSP/Library Generation
3. Software Compilation
SW Configuration
Executable
Data2BRAM
PPC405PLB /
Arbiter
PLBEMC
OPBGPIO
OPBUART
PLB2OPBBridgeOPB2PLBBridge
BRAMBlock
OPB /Arbiter
JTAGCNTL
PLBBRAM
I/F
Download to FPGA
MHSMicroprocessor Software Specification
LibGenCustomizes libraries, drivers etc.
Data2BRAMUpdate Bitstream with program/data information
MHS
LibGen
GNU (MB&PPC)Diab(PPC)Compilers
GDB /XMD
Hardware Flow
Bitstream
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Example MSS FormatPARAMETER VERSION = 2.0.0
PARAMETER HW_SPEC_FILE = system.mhs
BEGIN PROCESSOR
PARAMETER HW_INSTANCE = my_microblaze
PARAMETER DRIVER_NAME = cpu
PARAMETER DRIVER_VER = 1.00.a
PARAMETER EXECUTABLE = executable.elf
PARAMETER COMPILER = mb-gcc
PARAMETER ARCHIVER = mb-ar
PARAMETER DEBUG_PERIPHERAL = my_jtaguart
PARAMETER BOOT_PERIPHERAL = my_jtaguart
PARAMETER STDIN = my_uartlite
PARAMETER STDOUT = my_uartlite
...
END
BEGIN DRIVER
PARAMETER HW_INSTANCE = myethernet
PARAMETER DRIVER_NAME = emac
PARAMETER DRIVER_VER = 1.00.b
PARAMERER LEVEL = 0
PARAMETER LIBRARY = XilNet
END
MicroBlaze
OPB /Arbiter
OPBJTAGUART
OPBUARTLITE
BRAMBlock
OPBBRAM
I/F
OPBGPIO
LM
BEGIN DRIVER
PARAMETER HW_INSTANCE = my_uartlite
PARAMETER DRIVER_NAME = uartlite
PARAMETER DRIVER_VER = 1.00.b
PARAMERER LEVEL = 0
END
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How to Create an MSS?
Identifies driver for selected processor
Identify STDIO for selected processor
Identify debug/boot peripherals ( MB only)
MicroBlaze Only
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How to Create an MSS?
Identifies ISR for selected peripheral
Identifies driver for selected peripheral
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What Does LibGen Do?
Libraries
boot.o (for PPC)xmdstub.elf (for MB)
*.a, *.h,
MPDPAOBDD
MPDPAOBDD Drivers for
Processor IPProcessor IPor MYIPMYIP
MDD
MHS File
MSS FilePowerPC BSP /MicroBlaze BSP
LibGen Generates and ConfiguresInclude file, such as xparameters.hlibc.a, libm.a, libxil.a libraries
1. Specify Software Architecture
Executable in on-chipmemory
Download to Board
SW Development Flow
Executable in off-chip memory
?
2. Automatic SoftwareBSP/Library Generation
3. Software Compilation
SW Configuration
Executable
MHS
LibGen
GNU /Diab
Compilers
GDB /XMD
LibGen
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XPS Manages Source Code and Setup Compiler Options
Supports GNU and Diab Compilers
1. Specify Software Architecture
Executable in on-chipmemory
Download to Board
SW Development Flow
Executable in off-chip memory
?
2. Automatic SoftwareBSP/Library Generation
3. Software Compilation
SW Configuration
Executable
MHS
LibGen
GNU/Diab
Compilers
GDB /XMD
“Xilinx Confidential”
Embedded System Design Consists ofHardware designSoftware designHW / SW co-verification (Simulation & debug )
XPSSoftware
DesignDebug
HW-SW Co-VerificationHW-SW Partitioning
Embedded Development Flow
SimulationHardware
Design
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Simulation Flow
1. Specify Simulation Platform
Simulation Flow
2. Automatic SimulationPlatform Generation
3. Simulator
Sim Configuration MVS
SimGen
Modelsim /Verilog XL
MVSMicroprocessor Verification Specification
SimGenSimulation Model GeneratorGenerates and configures simulation models for a specified hardware.
• MVS Example
PARAMETER HW_SPEC_FILE = system.mhsPARAMETER SW_SPEC_FILE = system.mssPARAMETER LANGUAGE = VHDLPARAMETER SIMULATOR = mtiPARAMETER SIM_MODEL = BEHAVIORAL..
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ExecutableNGCHDL
Wrapper(s)
MHS FileHardware Flow MVS File
SimGen
SoftwareFlow
BMM Processor IPProcessor IPSim Sim
Model(s)Model(s)*_Init.vhd
(Init BRAM),HDL Wrappers
DO FileCompile listMap libraries
Simulation FlowSimGen
Generates and configures simulation models, do-filesUsed in conjunction with PlatGen and MHSTakes ELF + BMM to generate models to initialize BRAMs
PowerPCPowerPCSWIFT ModelSWIFT ModelSimulator
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Simulation Model Generator(SimGen)
Simulation Models Supported by SimGenBehavioral (functional simulation)
Processor IP (including MicroBlaze) simulation models are provided
Structural (gate-level simulation)Structural with timing
Simulators Supported by SimGenModelSimVerilog-XL
Languages Supported by SimGenVHDLVerilog (gate-level)
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Bus Function Model Generator(BfmGen)
Creates Testbench for Module Level VerificationGenerates PLB / OPB / DCR transactions (Test Stimulus)
Used in Conjunction with IBM CoreConnect ToolkitNeed CoreConnect license from IBMNeed to install CoreConnect toolkit
MyPeripheral
BFMDoes my design work ?
* For bus monitors, also take a look at the solution from Chipscope Integrated Bus Analyzer (IBA)
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Embedded Development FlowEmbedded System Design Consists of
Hardware designSoftware designHW / SW co-verification (Simulation & Debug )
XPSSoftware
Design
HW-SW Co-VerificationHW-SW Partitioning
HardwareDesign
Debug
Simulation
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Debug Using XMDPlumbing and synchronization between host-side application and:
Other host-side applicationsActual (hardware) targets
Tcl interface
PPC
XMD for PowerPCGDB connects to XMD connects to Parallel IV cable
GDB Remote
(TCP/IP) XMD
LAB1
Debug with actual hardware of PowerPC
“Xilinx Confidential”
XMD for MicroBlazeConnects to:
ISS for cycle accurate SW debugUART, or JTAG_UART for HW target debug
Debug Using XMD
GDB Remote(TCP/IP)
Cycle Accurate ISS for MB
XMD Protocol
GDB Remote
(TCP/IP) XMD
XMD LAB1
Debug with actual hardware of MB
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Design for DebugPowerPC
Dedicate debug port in the hard macro (BDM)BDM can shared with FPGA’s JTAG PinsBut there is a rule in FPGA: ALL or NONE !!!
PPC PPC
PPC PPC
jtagppc_cntlr.vhd :
U0_JTAGPPC : JTAGPPC Port Map (TCK => JTGC405TCK, --oTDIPPC => JTGC405TDI, --oTMS => JTGC405TMS, --oTDOPPC => C405JTGTDO, --iTDOTSPPC => C405JTGTDOEN --i
*Find out more information regarding to Wind River’s requirement!
LAB1
*XMD currently supports 2VP4 / P7 only
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MicroBlazeMicroBlaze
Design for Debug (cont.)MicroBlaze
No dedicate debug interface (future plan)Use UART(Serial Cable) or JTAG(Parallel Cable) to connectSmall debug program “XMDStub” resides in the memory
MicroBlaze
OPB
JTAGUART
MicroBlaze
OPB OR
UARTLite
LAB1
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Conclusion: Xilinx Platform Studio Architecture
XPS provides project management interfaces
XPS coordinates multiple point tools with well defined interfaces
XPS GUI provide user intuitive design entries
Makefile flow engine is even more flexible to manage customed design methodologies in batch mode
XPSSoftware
Design
HardwareDesign
Debug
Simulation
HW-SW Co-VerificationHW-SW Partitioning
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Reference and Resources
Always: Datasheets / Reference Guide
Forums / Tech Tips / SolutionsC to Bit tutorials - coming soon
EDK How-To Guide - coming soon
www.embedded.com
