ECE 171Digital Circuits

Chapter 6Logic Circuits

Herbert G. Mayer, PSUStatus 1/16/2016

Copied with Permission from prof. Mark Faust @ PSU ECE

Syllabus

Combinatorial Logic Circuits Truth Tables Logic Functions References

Lecture 6

• Topics– Combinational Logic Circuits

• Graphic Symbols (IEEE and IEC)• Switching Circuits• Analyzing IC Logic Circuits• Designing IC Logic Circuits• Detailed Schematic Diagrams• Using Equivalent Symbols

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Combinational Logic Circuits

• Combinational Logic– Outputs depend only upon the current inputs (not

previous “state”)• Positive Logic

– High voltage (H) represents logic 1 (“True”)– “Signal BusGrant is asserted High”

• Negative Logic– Low voltage (L) represents logic 1 (“True”)– “Signal BusRequest# is asserted Low”

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IEEE: Institute of Electricaland Electronics Engineers

IEC: International Electro-technical Commission

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n.o. = normally openn.c. = normally closed

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All Possible Two Variable FunctionsQuestion: How many unique functions of twovariables are there?

Recall earlier question…

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Truth Tables

B5 B4 B3 B2 B1 B0 F

0 0 0 0 0 0 0

0 0 0 0 0 1 1

0 0 0 0 1 0 1

0 0 0 0 1 1 0

.

.

.

1 1 1 1 1 1 1

0

1

2

3

.

.

.

63

26 = 64

Question: How many rows are there in a truth tablefor n variables?As many rows as unique combinationsof inputs

Enumerate by counting in binary

2n

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Two Variable FunctionsQuestion: How many unique combinations of 2n bits?

Enumerate by counting in binary

22n

264

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B5 B4 B3 B2 B1 B0 F

0 0 0 0 0 0 0

0 0 0 0 0 1 1

0 0 0 0 1 0 1

0 0 0 0 1 1 0

.

.

.

1 1 1 1 1 1 1

0

1

2

3

.

.

.

63

26 = 64

All Possible Two Variable FunctionsQuestion: How many unique functions of twovariables are there? B1 B0 F

0 0 0

0 1 1

1 0 1

1 1 0

22 = 4 rows 4 bits

Number of unique 4 bit words = 24 = 16

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Analyzing Logic Circuits

Reference Designators (“Instances”)

X + Z

XX + Y

(X + Y)×(X + Z)

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Analyzing Logic Circuits

C

A×B

B×C

A×B + B×C

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Designing Logic Circuits

F1 = A×B×C + B×C + A×B

SOP form with 3 terms 3 input OR gate

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Designing Logic Circuits

F1 = A×B×C + B×C + A×B

Complement already available

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Some Terminology

F1 = A×B×C + B×C + A×BSignal line – any “wire” to a gate input or output

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Some Terminology

F1 = A×B×C + B×C + A×BNet – collection of signal lines which are connected

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Some Terminology

F1 = A×B×C + B×C + A×BFan-out – Number of inputs an IC output is driving

Fan-out of 2

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Some Terminology

F1 = A×B×C + B×C + A×BFan-in – Number of inputs to a gate

Fan-in of 3

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Vertical Layout Scheme – SOP Form

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Vertical Layout Scheme – SOP Form

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>2 Input OR Gates Not Available for all IC Technologies

Solution: “Cascading” gates

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Vertical Layout Scheme – POS Form

F2 = (X+Y)×(X+Y)×(X+Z)

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Designing Using DeMorgan Equivalents

• Often prefer NAND/NOR to AND/OR when using real ICs– NAND/NOR typically have more fan-in– NAND/NOR “functionally complete”– NAND/NOR usually faster than AND/OR

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AND/OR forms of NAND

DeMorgan’s Theorem

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Summary of AND/OR forms

Change OR to AND“Complement” bubbles

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Equivalent Signal Lines

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NAND/NAND Example

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NOR/NOR Example

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