ECE 257 Linear Integrated Analog Circuits Switched-Capacitor

Switched-Capacitor Circuits © 2007 S. J. Ashtiani 1

ECE 257Linear Integrated Analog Circuits

Switched-Capacitor Circuits

Shaahin J. Ashtiani


Switched Capacitor Circuits• Basics Operation• Functional Operation

Switched-Capacitor IntegratorDiscrete-Time Signal ProcessingSwitched Capacitor FiltersSample and Hold CircuitsGain Stages

• Non-Ideal effects and Practical SolutionsAnalysis of Sampling SwitchesCharge injection and Clock Feed-throughBottom-Plate SamplingEffect of op-amp non-idealitiesNoiseCorrelated double-sampling


Why SC Circuits?• SC Circuits

Discrete-time systems• Accurate realization of filters and gains

Accuracy related to matching of capacitorsNo need to resistorsPerformance Independent of absolute values of C

• Highly linearIndependent of shape of waveformsOnly settling accuracy is important


Basic Operation: SC Resistor

• Iavg= C(V1-V2)/T• Req=T/C=1/fC• Low-frequency approximation


Basic Switched-Capacitor Integrator

• Phase Φ1: C1 is charged up tp Vin (Q=C1Vin)• Phase Φ2: C1 charge (Q=C1Vin) is transferred into C2• Charge transfer equation:

)()()2/( 122 TnTViCTnTVoCTnTVoC −−−=−

)1()1()( 122 −−−= nViCnVoCnVoC112

1)()()(

1

−−−==

−

zz

CC

nVinVozH


Sensitivity to Parasitic Capacitance

• Basic SC equal resistor is sensitive to parasitics

)(12

1)(

1

11 nVi

zz

CCC

nVo p

−−

+−=

−


Parasitic-Insensitive Integrator

• Non-inverting integrator• Delayed

1121

)()()(

1

−−==

−

zz

CC

nVinVozH )1()1()( 122 −+−= nViCnVoCnVoC


Parasitic-Insensitive Integrator: Operation

• Cp2: Always connected to ground• CP1: Connected to ground in Φ2


Parasitic-Insensitive Integrator: Delay Free

• Inverting integrator• Delay Free

111

21

)()()(

−−−==

zCC

nVinVozH )()1()( 122 nViCnVoCnVoC −−=


Switched Capacitor Filters

• H(s) to H(z)Bilinear Transform: Accurate

Impulse invariant: Simple but not accurate

1

1

112

−

−

+−

−=zz

Ts

)(][ nTThnh c=


Implementing H(z) by SC Circuits

CA

Vo

V2

1C2

1

V1

1C1

1

V2 C3

1111

−− zCA

1C−

12

−zC

( )13 1 −− zC


Example: First-Order Filter

1111

−− zCA

2C−

( )11 1 −− zC

3C−


First-Order Filter

• DC Gain:

• Pole:

• Zero:

11)(

3

121

−⎟⎟⎠

⎞⎜⎜⎝

⎛+

+⎟⎟⎠

⎞⎜⎜⎝

⎛ +

−=z

CC

CCz

CCC

zH

A

AA

3

2)1(CCH −=

1111

−− zCA

2C−

( )11 1 −− zC

3C−

3CCCz

A

Ap +=

21

1

CCCzz +

=


Design Example• First order filter: -3dB @ 10kHz, 0 @ 50kHz, fs=100kHz, DC

Gain=1• Zero at 50kHz: zz=-1, (Negative capacitor)• Using bilinear transform: zp=10kHz, s=2/T(z-1)/(z+1)

zp=.53327

• H(z): H(1)=1 K=0.23337

• Assume CA=10pf C1=4.376pFC2=-8.752pFC3=8.752pF

• Implementing C2: Cross-couple it in a fully differential design

53327.0)1()(

−+

=z

zKzH


Switch Sharing

• Removing redundant switched


Biquad Filter: Low-Q

• Biquad: General second-order system• Any filter can be realized by cascading biquads and first-

orders• Low-Q and High-Q implementation

20

02

012

2)(ωω

+⎟⎟⎠

⎞⎜⎜⎝

⎛+

++=

sQ

s

ksksksH


Low-Q Biquad Filter: CT Implementation


Low-Q Biquad Filter: SC Implementation

From Analog Integrated Circuit Design (Johns & Martin)


Low-Q Biquad Filter: z domain flow-graph

• One degree of freedom for K1,K4 and K5• Optimum choice for dynamic range:

1)(

12

2

012

2

++++

=zbzb

azazazH

• K3=a0

• K2=a2-a0

• K1K5=a0+a1+a2

• K6=b2-1• K4K5=b1+b2+1

12154 ++== bbKK


CT to SW Conversion• Impulse invariance• Rewrite to

• for z-1/2 and z1/2 we have:

H(jω) is:

For ωT<<1

K4=K5=ω0T, K6=ω0T/Q• For high Q, large capacitor ratio required

( ) ( )( ) ( ) 121

2)(654

26

332512

32

+−−+++−−++

−=zKKKzK

KzKKKKzKKzH( ) ( )( ) ( )22/12/12/12/12/1

654

22/12/13

2/12/12/1251)(

−−

−−

−+−+

−+−+−=

zzzzzKKK

zzKzzzKKKzH

⎟⎠⎞

⎜⎝⎛+⎟

⎠⎞

⎜⎝⎛=

2sin

2cos2/1 TjTz ωω

⎟⎠⎞

⎜⎝⎛−⎟

⎠⎞

⎜⎝⎛=−

2sin

2cos2/1 TjTz ωω

( )

( ) )2

(sin24)sin(

)2

(sin24)sin()(

26654

223251

TKTjKKK

TKKTjKKKzH ωω

ωω

+++

+++−=

( ) ( )( ) ( ) 2

6654

223251

)(2/1)(2/)(

TKTjKKKTKKTjKKKzH

ωωωω

++++++

−=


Biquad Filter: High-Q

• Biquad HQ

( )( ) ( )656554

252335251

23

122)(

KKzKKKKzKKKzKKKKKzKzH

−+−++−+−++

−=


Sample and Hold Circuits: Flip-Around

C

Vo

1

1

1

Vi

• Fast: OTA out does not change: Relaxed SR • Feedback factor =1• Common-Mode Issue: Input signal CM should be equal to OTA CM


Flip-Around S&H: Fully Differential

C

Φ1

Φ1

C

VCMI

Φ1

Φ2

Vi+

Φ1

Φ2

Vi-

Vo+

Vo-

Φ1


Sample and Hold Circuits: Two-Capacitor

C

Vo

1

1

1

Vi

C

1

• OTA Settles: Slower• Insensitive to CM difference


Gain Stage I

C1

Vo

1

1

1

Vi

C2

1

• Same as S&H: G=-C1/C2


Gain Stage II

• G=1+C1/C2


Practical Issues and Non-Idealities• MOS Sampling• Speed• Linearity• Switch bootstrapping• Charge Injection• Jitter• Noise


MOS T&H: Simulation


MOS S&H: Tracking Speed & Distorsion

• Simple RC model:

•

• R is non-linear!

• Tracked signal has harmonic distortion!

⎟⎟⎠

⎞⎜⎜⎝

⎛−=

−τt

eViVo 1

RC1

=τ( )ViVV

LWc

RTDDox −−

≅μ

1

⎟⎟⎟

⎠

⎞

⎜⎜⎜

⎝

⎛−=

⎟⎟⎠

⎞⎜⎜⎝

⎛−

−−TDD VV

Vit

eViVo1

21 τ


MOS S&H: Tracking Distortion

0.0 5.0M 10.0M 15.0M 20.0M 25.0M

-160

-140

-120

-100

-80

-60

-40

-20

0

Vo (d

B)

Frequency (Hz)

Fully Diff Single

• W=10, L=0.18, Cin=1pF fs=50M, fin=1.56M ,Vin=.5V,


Improving Tracking Speed: T-GATE

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8

60

80

100

120

140

160

Res

ista

nce

(ohm

)

Input Voltage (V)

• Not a good choice for low-voltage technologies


Improving Tracking Speed: Bootstrapping

• Improving R by increasing VGS• No terminal-to-terminal voltage exceeds VDD• Overdrive Independent of Vi


Improving Tracking Speed: Bootstrapping


Charge Injection and Clock Feed-through• Error in sampled voltage due to

charge injection and clock feed-through

• Clock feed-throughIndependent of Vi

• Charge injectionDepends on ViBody effect

• Charge injection causes harmonic distortion

DDLgd

gd VCc

cVo

+=Δ

( )L

TDDox

CVViVWLcVo −−

=Δ β


Canceling Charge Injection• Dummy transistor

Dummy transistor: half size

• Tgate as switchNMOS and PMOS have same size

Vi

1

Vo

CL

1


Canceling Charge Injection: Fully Differential


Bottom-Plate Sampling

• Q2 turns off first Q2 induces Constant charge in C1• Q1 turns off later Q1 does not add charge in C1 • Induced error is independent of Vin


SC Circuits with Bottom-Plate Sampling


Clock Jitter• Jitter (Δt): Uncertainty in

rising and falling of clock signalΔt in the range of 1-100psΔt Δv in sampling


Correlated Double Sampling

• Canceling opamp offset and 1/f noise• Store offset in C2’ during sampling phase


Effect of Op-Amp • Limited Gain• Limited Settling

Linear settlingNonlinear settling

• Non-LinearityVariable gainSlewingSwitched

• Noise


Limited Gain of op-ampC2

Vo

Vin

1C1

1 A

• SC Integrator: Convert to low-pass filter• Sample and hold: Gain error

( )1)1(1

121

)()()(

1

−−−−==

−

zz

CC

nVinVozH

ελ

2

111

11

CC

A+

=−ε

⎟⎟⎠

⎞⎜⎜⎝

⎛ ++=

2

21

2

1 11C

CCAC

CGain

⎟⎟⎠

⎞⎜⎜⎝

⎛+=

2

111CC

Aλ


Linear & Nonlinear Settling

• Linear Settling: Caused gain error• Nonlinear Settling: Input-dependent response

harmonic distortionHigh-Slew-Rate op-amp required!

111

21

)()()(

1

−−⎟⎟⎠

⎞⎜⎜⎝

⎛−==

−−

zze

CC

nVinVozH

Tτ


Linear Settling: Feedback Factor

• Larger gain Larger C1/C2 Slower settling• Large input parasitic CP Slow settling

2

21

21

CCCC

fP

T

++=

πτ


Op-Amp Noise

C2

Vo

Vin

1C1

1

Vn(t)

C1Vi

C2

CP

Vo

Vn(t)

• Noise: • KT/C Noise• Op-Amp noise

Documents

ECE 257 Linear Integrated Analog Circuits Switched-Capacitor