Ec Manual New

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Analog Electronics Circuits Laboratory Manual

EXPERIMENT NO. 1

RC COUPLED AMPLIFIER

AIM: To design and conduct of RC Coupled single stage (a) BJT (b) FET amplifier anddetermination of gain frequency response, input and output impedance

COMPONENTS: Resistors, Capacitors, RPS, AFG, BJT SL100, FET BFW 10/11, DRB,Multimeter, Connecting Board and wires

A. BJT RC COUPLED AMPLIFIER

CIRCUIT DIAGRAM:

DESIGN: a) To Find RE

Assume VCC = 12V, VRE = 2V,IC = 4 mA, = 100(SL100)IE ICRE = VRE / IE = VRE/ IC

= 2/4.0m = 470RE = 470 (Std)

b) To Find R1 and R2VB = VBE + VRE

= 0.7 + 2 = 2.7VIB = IC /= 4m/100 = 0.04mA

Dept of E&C, G.C.E., Ramanagaram

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Assume 10IB flows in R1, 9IB flows in R2

R1 =( VCC VB)/ 10IB= (12 2.7)/ 10(0.04m) = 23.25K

R1 = 22K (Std)

VB = VR2 = 9IB * R2R2 = VB /9IB = 2.7 / 9(0.04m) = 7.5K

R2 = 6.8K (Std)c) To Find RC

Choose VCE = VCC /2= 12/2 = 6VVCC ICRC VCE VRE = 012 (4m)RC 6 2 = 0

RC = 1KRC = 1K (Std)

b) To Find CE, CC1 and CC2

XCE = RE /10 at f = 100Hz1/2fCE = RE/10

CE = 10 / 2fRE = 10 /[2(100)(270)] = 59FCE = 47F (Electrolyte)

Choose CC1 = CC2 = 0.47F. These are coupling capacitors to offer lowreactance path for ac signal


2

10IB

9IB


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B. FET RC COUPLED AMPLIFIER

CIRCUIT DIAGRAM:

DESIGN:From data sheet of BFW 10/11

IDSS = 10 mAVP = - 3V or - 4VLet ID = 2mA

a) To Find Rs :From the equation of the currentID = IDSS( 1 VGS/VP)2

ID / IDSS = ( 1 VGS/VP)2

Substituting for ID = IDSS and VDVGS = - 1.65VGS = IDRSRS = VGS /ID =0.820KRS = 1K

b) To Find RG :IGSRG = VGSRG = VGS/ IGS = 1.65 /1A = 1.65MRG = 2M

c) To Find RD :Applying KVL Assume & setVDD = IDRD +IDRS+VDS VDD = 10V

RD = (VDD-VDS IDRS)/ ID then VDS = VDD = 5/2VRD = 1.5K


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d) To Find Cs & CCLet f =100KHzXCS = RS /100 = 1000 /100= 10XCS= 1/2fCS

CS = 1/ 2fCE = 0.15fCs= 0.15f

Select C = 0.22f = CC1 = CC2

FOR BJT & FET AMPLIFIERS

PROCEDURE:

a) To get frequency response:1. The connection are made as shown in the circuit diagram2. Before applying the input signal, the DC conditions are checked y setting Vcc =

12V. Vcc must be closed to 1/2Vcc = 6V.3. Input sinusoidal signal (frequency = 1 KHz and voltage 50 mV peak-to-peak)

should be applied using ASG. Care should be taken to get undistorted wave atthe output, while applying input signal.

4. Keeping input signal Vin constant, the frequency of input is varied from 100Hzto 1MHz in suitable steps while measuring the output voltage for differentfrequencies.

5. The gain of the amplitude is calculated and tabulated. The graph of frequencyVs gain in dB is plotted on a semi log sheet.

6. Bandwidth is calculated from the frequency response. Also gain bandwidthproduct is computed.

TABULAR COLUMN:

Vs = _____________________mV

Frequency(Hz) Vo(P-P) (V) Gain Av = Vo/Vi Gain Av in dB= 20log10Av

100Hz

1MHz


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INPUT & OUTPUT WAVEFORM:

t

V0(V)

Vin(V)

t

Vm

FREQUENCY RESPONSE CURVE:

b) To measure output impedance Zo:


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Gain in dB


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1. DRB is connected as shown in the circuit and let the resistance of DRB behigh in terms of several kilo ohms or mega ohms.

2. Keep the input frequency in the mid band region.3. Output voltage Vo is measured

4. Resistance on DRB is decreased till Vo reduces to half of its value. The DRBvalue gives the output impedance Zo of an amplifier.

c) To measure input impedance Zi:

1. DRB is connected as shown in the circuit and keep the resistance of DRB tozero.

2. Keep the input sine wave frequency in the mid band region.3. Output voltage Vo is measured.4. Resistance on DRB is increased till Vo reduces to half of its value. The DRB

value gives the input impedance Zi of an amplifier.

RESULT:

1. Bandwidth (BW) = _____________________Hz2. Midband gain = Amid = _____________________3. Gain Bandwidth Product = BWxAmid = _______________4. Input Impedance = _______________5. Output Impedance = __________________


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EXPERIMENT NO. 2

DARLINGTON EMITTER FOLLOWER

AIM: Designing and wiring of BJT Darlington emitter follower with & withoutbootstrapping and determination of gain, input and output impedances.

COMPONENTS: Transistor SL100 (2 Nos), Resistors, Capacitors, RPS, 0-30 V RANGE,CRO, ASG, CRO probes

CIRCUIT WITHOUT BOOTSTRAP

CIRCUIT DIAGRAM:

DESIGN: for SL 100, = 100Let VCC=10V, IC1= 4mA, IC2=0 .4AVCE2= VCC /2= 5V

To find RE:Applying KVL to the output circuitVCC= VCE2+ ICE2 RERE= VCC VCE2/IC2= 10-5/4m= 1.25kRE = 1 k (Std)

To find R1 & R2:Let, IB2= IC2/= 0.04maIB1= IC1/= 0.4 ALet I1=10 I B1= (10)( 0.4A)= 4AI2= 9 IB1= 3.6 AR2= VR2/I2 = VRE+ VBE1+ V BE2/ I2= 5+0.6+0.6/3.6 = 1.7 M

R2= 1M (Std)R1= VR1/I1= VCC V R2/ 4 = 10 6.2/4 = 0.75 M R1= 1M (Std)


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CIRCUIT WITH BOOTSTRAP:

DESIGN:Let R3= 10KBootstrap capacitor CB should be large. Select CB= 10fZi (without bootstrap ) = hie + R3 = 11KZi ( with bootstrap ) = Rs/ 1-Av = 10k/ 1- 0.95 = 200k

PROCEDURE (for both with and without Bootstrap):

1) The circuit is connected as shown in the circuit diagram.

2) The DC condition is checked i e VCE = VCC/ 2 is measured which should beapproximately 5V

3) A sine wave of 1V PEAK TO PEAK (1 KHz is applied to the input and output voltageis measured for different frequencies. The voltage gain = Vo/Vi should beapproximately equal to 1 for different frequencies.

4) The same procedure is repeated with & without bootstrap.

5) Input and output impedances are measured for both the circuits. Procedure is same asRC coupled amplifier.


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To measure output impedance Zo(for both with and without Bootstrap):


2. Keep the input frequency in the mid band region.

3. Output voltage Vo is measured4. Resistance on DRB is decreased till Vo reduces to half of its value. The DRBvalue gives the output impedance Zo of an amplifier.

To measure input impedance Zi(for both with and without Bootstrap):



value gives the input impedance Zi of an amplifier.

EXPECTED INPUT & OUTPUT WAVEFORM(for both with & without Bootstrap):


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Tabular column for without bootstrap:

Vi = __________________ V

Frequency (Hz) Vo(V) A v= Vo/ Vi100 HZ

1 M H Z

Tabular column for with bootstrap:

Vi = __________________ V

Frequency (Hz) Vo(V) A v= Vo/ Vi100 HZ

1 M H Z

RESULTS:

1. WITHOUT BOOTSTRAP :

a) Voltage gain = A v = _______________________b) Input impedance = Z i = ___________________

c) Output impedance = Zo = _______________________

2. WITH BOOTSTRAP :

a) Voltage gain = Av = ________________________

b) Input impedance = Z i = ________________________

c) Output impedance = Zo = ______________________


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EXPERIMENT NO. 3

VOLTAGE SERIES FEEDBACK AMPLIFIER

AIM: To design BJT voltage series feedback amplifier and determination of gain,frequency response, input and output impedance with and without feedback.

COMPONENTS: Resistors, Capacitors, RPS, AFG, BJT SL100, DRB, Multimeter,Connecting Board and wires

CIRCUIT DIAGRAM:

DESIGN:Assume Vcc = 12VVRE = VCC / 2 = 12/2 = 6VIC = 2mA = 115 (transistor Q1 & Q2 are BC1474 )

a) To Find RELet VRE = 12/10 = 1.2V

RE = VRE / IE = 1.2/2mA = 600RE =600

(for the first stage alone, split the 600 resistance as 220 + 390)


= 0.7 + 1.2= 1.9V

IB = IC / = 2m/115 = 17.35AAssume 10IB flows in R1, 9IB flows in R2

R1 = (VCC VB )/10IB= (12 1.9)/10(17.35) = 58.21K

R1 = 56K


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VB = VR2 = 9IB * R2R2 = VB /9IB = 1.9/ 9(17.35) = 12.16 KR2 = 12K

c) To Find RC

Choose VCE = VCC/2 = 12/2 = 6VVCC ICRC VCE VRE = 012 (2m)RC 6 -1.2 = 0

RC = 2.4KRC = 2.2K

b) To Find CE, CC1 and CC2

XCE = RE / 10 at f = 100Hz

1/2fCE = RE/10CE = 10 / 2fRE = 10 / 2(100)(270) = 59FCE = 47F (Electrolyte)

Choose CC1 = CC2 = 0.47F. These are coupling capacitors to offer lowreactance path for ac signal

II STAGE: Design of second stage is same as that of the first stageLet RF = 10K

Calculation of feedback factor () theoretical

The feedback amplifier is given by, = RE / (RE + Rf )

= 390 / (10K+390)= 0.037

(The value of is usually chosen between 0.01 to 0.1)

PROCEDURE:

a) To get frequency response:

1. The connection are made as shown in the circuit diagram2. Before applying the input signal, the DC conditions are checked y setting Vcc =

12V. VCC must be closed to 1/2VCC = 6V.3. Input sinusoidal signal (frequency = 1 KHz and voltage 50 mV peak-to-peak)should be applied using ASG. Care should be taken to get undistorted wave atthe output, while applying input signal.

4. Keeping input signal Vin constant, the frequency of input is varied from 100Hzto 1MHz in suitable steps while measuring the output voltage for differentfrequencies.

5. The gain of the amplitude is calculated and tabulated. The graph of frequencyVs gain in Db (=20log Vo/Vin) is plotted on a semi log sheet.

6. Bandwidth is calculated from the frequency response. Also gain bandwidthproduct is computed.


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TABULAR COLUMN:

Vi = _____________________mV

Frequency(Hz) Vo(P-P) (V) Gain Av = Vo/Vi Gain Av in dB= 20log10Av100Hz

1MHz

EXPECTED WAVEFORM:

FREQUENCY RESPONSE CURVE:

Without feedback

Withfeedback

f11f1 f2 f22

F(Hz )

Gain

indB


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b) To measure output impedance Zo:


2. Keep the input frequency in the mid band region.3. Output voltage Vo is measured4. Resistance on DRB is decreased till Vo reduces to half of its value. The DRB

value gives the output impedance Zo of an amplifier.

c) To measure input impedance Zi:



value gives the input impedance Zi of an amplifier.RESULT:

A. WITH FEEDBACK


B. WITHOUT FEEDBACK



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EXPERIMENT NO. 4

RC PHASE SHIFT OSCILLATOR

AIM: Wiring and testing for the performance of BJT-RC phase shift Oscillator for f0 10 KHz

COMPONENTS: Transistor SL100 (1 number), Resistor, capacitors, RPS (0-30 range),CRO, ASG, CRO probes, Multimeter, Connecting wires and board.

CIRCUIT DIAGRAM:

CE47 F

0.047 f 0.047 f 0.047 f

VCC12 V

0.1F

R122 K RC1K

R26.8K RE

470

1K 1K

1Kor

5Kpot

V0

POT1k

SL100

12 3

4

NOTE: Point 1, 2, 3 & 4 are to observe the different phase shift of the RC phase shiftoscillator.

Design For tank circuit:

f0= 1/[2RC(6+4k)] Where k = RC/RAssume f0 = 1 KHz, R = 1KFrom design RC = 1K

k = RC /R = 1C = 1/[2R f0(6+4k)]C = 1/[2 (1K)(1K)(6+4)]

= 0.0503 fSelect C 0.047 f (Std)


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NOTE:Thehfe of SL100/BC107 is 100.The value of4k +23 +29/kis 56.

Hence, Condition for sustained Oscillation i.e. hfe 4k +23 +29/kis satisfied.

Design of an amplifier:

a) To Find REAssume VCC = 12V, VRE = 2V,IC = 4 mA, = 100(SL100)IE ICRE = VRE / IE = VRE/ IC

= 2/4.0m = 470RE = 470 (Std)


= 0.7 + 2 = 2.7VIB = IC /= 4m/100 = 0.04mA


R1 =( VCC VB)/ 10IB= (12 2.7)/ 10(0.04m) = 23.25K

R1 = 22K (Std)

VB = VR2 = 9IB * R2R2 = VB /9IB = 2.7 / 9(0.04m) = 7.5K

R2 = 6.8K (Std)

c) To Find RC

Choose VCE = VCC /2= 12/2 = 6VVCC ICRC VCE VRE = 0

12 (4m)RC 6 2 = 0RC = 1KRC = 1K (Std)

d) To Find CE


CE = 10 / 2fRE = 10 /[2(100)(270)] = 59FCE = 47f(Electrolyte)


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EXPECTED WAVEFORMS:

1. Output Waveform:

2. Lissageous Pattern

B

A

Point1, 1 = 0 point 2, 2 = 60

B

A

B

point 3, 3 = 120 point 4, 4 = 180

2 = tan-1 ( B/A )3 = 180- tan-1 ( B/A)


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V0


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PROCEDURE:

1. The amplifier is rigged up as per the circuit and DC conditions is checkedi.e. VCE = VCC2. After getting the above DC condition, the entire circuit has to be rigged up.

3. CRO (1st channel) has to be connected between points(1) and ground to observeSinusoidal waveform.

4. For proper undistorted output, the 1K or 5 K pot has to be adjusted.

5. The frequency & amplitude of the sine wave is noted at the output.

6. Theoretical frequency should be compared with practical frequency.

Procedure to observe Lissageous pattern (or phase shift):

1. Keep the time/sec knob in X-Y position & output voltage VO point tochannel1 fixed.

2. To observe the different angles , keep the channel 2 to different points 1, 2,3 & 4 respectively, one at a time as shown in the table below:

Angle (Degree)

Channel 2

0 point 160 point 2120 point 3180 point 4

RESULT:

1. f pract= 1/T Hz = .. Hz & fth.. Hz2. VOP-P =. Volts3. 1= . Degree4. 2 = Degree5. 3 =.Degree6. 4 =.Degree


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EXPERIMENT N0. 5

HARTLEY & COLPITTS OSCILLATORS

AIM: To test the performance of BJT Hartley and Collpitt Osicillator for RF rangef0 100KHz

COMPONENTS: Resistors, capacitors and Inductors, RPS( 0 -30V ), Multimeter, CRO,CRO probes, SL100/BC107, Connecting wires & Board.

A. HARTLEY OSCILLATOR

CIRCUIT DIAGRAM:Vcc12 V

RC1K

RE470

R122 K

R26.8K

Vo

SL 100

0.1f

CE47 f

0.1f

C330 pf

L22.6mH

L15mH

0.1f

POT1K

DESIGN OF TANK CIRCUIT

Assume fo = 100KHz C = 330 pf

fo = 1 / 2 ( LeqC)

Leq = 1 / (2fo)2C=1 / [(2x 100K)2330p]= 7.68 mH

Leq = L1 + L2 = (5 + 2.6)mHzL1 = 5mH,L2 = 2.6mH

NOTE:Thehfe of SL100/BC107 is 100 and ratio ofL1 / L2 is 2.Hence, Condition for sustained Oscillation i.e. hfe L1 / L2 is satisfied.


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B. COLPITTS OSCILLATOR

CIRCUIT DIAGRAM:

Vcc12V

RC1k

POT

1K

R122K

R26.8K

Vo

SL100

0.1f

CE

47f

0.1f

C11000 pf

L3.6mH

0.1f

C22200 pf

RE

470

DESIGN OF TANK CIRCUIT

Assume fo = 100KHzAssume C1 = 1000pF

C2 = 2200pF

fo = 1 / 2 ( LeqC)

Ceq = ( C1* C2 )/ (C1 + C2)= 687.801

L = 1 / ( (2fo)2C )= 1 / [(2x 100K)2687.8]

L = 3.6 mHNOTE:

Thehfe of SL100/BC107 is 100 and ratio ofC2 / C1 is 2.2.Hence Condition for sustained Oscillation i.e. hfe C2 / C1 is satisfied.


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AMPLIFIER DESIGN OF BOTH THE OSCILLATORS

a) To Find REAssume VCC = 12V, VRE = 2V,

IC = 4 mA, = 100(SL100)IE ICRE = VRE / IE = VRE/ IC

= 2/4.0m = 470RE = 470 (Std)


= 0.7 + 2 = 2.7VIB = IC /= 4m/100 = 0.04mA


R1 =( VCC VB)/ 10IB= (12 2.7)/ 10(0.04m) = 23.25K

R1 = 22K (Std)

VB = VR2 = 9IB * R2R2 = VB /9IB = 2.7 / 9(0.04m) = 7.5K

R2 = 6.8K (Std)

c) To Find RC



d) To Find CE, CC1 and CC2

XCE = RE /10 at f = 100Hz1/2fCE = RE/10CE = 10 / 2fRE = 10 /[2(100)(270)] = 59FCE = 47f(Electrolyte)

Choose CC1 = CC2 = 0.47f. These are coupling capacitors to offer lowreactance path for ac signal


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EXPECTED OUTPUT:

PROCEDURE:

1) The amplifier circuit is rigged up as shown in the circuit diagram & the DC conditionis checked i.e. VCE = VCC

2) After checking the above condition, tank circuit is also connected and the output is

observed between collector and the ground.

3) Undistorted sine wave is obtained by adjusting the variable inductor /capacitor

4) The amplitude and frequency of the sine wave is noted.

5) Practical frequency is compared with theoretical frequency.

RESULT:

Hartley oscillator:1) VOP-P = ________________V

2) F(theo) = ________________ KHz

3) f( pract) = _______________KHz

Colpitts Oscillator:1) VOP-P = _______________V

2) f(theor) = _______________ KHz

3) f( pract) = ______________ KHz


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Vo(V)

t


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EXPERIMENT NO. 6

BJT CRYSTAL OSCILLATOR

AIM: Testing for the performance of BJT crystal oscillator for f0 > 100 KHz

COMPONENTS: Resistor, SL100 (NPN), 1MHz or 2MHz crystal, Capacitors, RPS(0-30Vrange),1K Potentiometer, Connecting wires and board.

CIRCUIT DIAGRAM:Vcc12V

RC1K

POT

1K

R122K

R26.8K

Vo

SL100

0.1f

CE

47f

1000pf

0.1f

RE

470

CRYSTAL

2 MHz

EXPECTED OUTPUT WAVEFORM:

ftheo = 2 MHzf = 1/T


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Vo(V)

T(Sec)


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AMPLIFIER DESIGN:

a) To Find REAssume VCC = 12V, VRE = 2V,IC = 4 mA, = 100(SL100)IE ICRE = VRE / IE = VRE/ IC

= 2/4.0m = 470RE = 470 (Std)


= 0.7 + 2 = 2.7V

IB = IC /= 4m/100 = 0.04mA


R1 =( VCC VB)/ 10IB= (12 2.7)/ 10(0.04m) = 23.25K

R1 = 22K (Std)

VB = VR2 = 9IB * R2R2 = VB /9IB = 2.7 / 9(0.04m) = 7.5K

R2 = 6.8K (Std)

c) To Find RC



d) To Find CE


CE = 10 / 2fRE = 10 /[2(100)(270)] = 59FCE = 47f(Electrolyte) (Std)


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PROCEDURE:

1. The circuit (amplifier part) has to be rigged up as per the diagram.

2. DC condition should be checked (VCE =1/2Vcc = 5V)3. By connecting the tank circuit, the oscillations are observed at the collector.4. To get undistorted sine wave output, 1K pot can be slightly be adjusted.5. The frequency of the sine wave (f =1/T) is calculated and noted.

RESULT:

1. fpract =. Hz2. V o(p-p) =.. Volts


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EXPERIMENT NO 7

DIODE CLIPPING CIRCUITSAIM: To test the diode clipping (single/double ended) circuits for peak clipping and peakdetection

COMPONENTS: Diode BY127, Resistors, DC Regulated Power Supply, Connecting Wiresand Board, ASG, CRO Probes.

1. POSITIVE CLIPPER:

Circuit Diagram:

VR1.4V

BY 127

10K

AFG

Vi

10Vpp

1KHz

+

-

Vo

-

+

Design:

Let the outputbe clipped to say +2VVo(max) = +2VVo(max) = Vf+Vref (Assume Vf = 0.6)Vref = Vo(max) Vf

Vref = 1.4VThe value of resistor R is chosen is

R = RfRr where Rf =10 R = 10K Rr = 10M

Waveform:

TransferCharacteristic:


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t

V0(V)

Vin(V)

10Vpp

t

Vm =

5V

T

F = 1/T

2 V


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VO (V)

Vin (V)

2V

2V

2. NEGATIVE CLIPPER:

Circuit Diagram:

VR1.4V

BY 127

10 K

AFG

Vi

10 Vpp

1KHz

+

-Vo

+

-

Design:

Let the output be clipped to say -2VVo(min) = -2VVo(min) = Vf + Vref (without sign) (Assume Vf = 0.6)Vref = Vo(min) Vf

= -2 (-0.6) = -1.4V

The value of resistor R is chosen isR = RfRr where Rf =10= 10K Rr = 10M

Waveform:

t

V0(V)

Vin(V)

10 Vpp

t

Vm 5 V

-2V

TF = 1/T

Transfer Characteristic:


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VO (V)

Vin (V)

-2V

-2V

3. DOUBLE ENDED CLIPPER

(i) Clipping at independent levels:

Circuit Diagram:

Vref 22.6V

BY 127

10K

AFG

Vi10Vpp

1KHz

+

-

Vo

BY 127

Vref 13.4V

- -

++

Design:

Let the output be clipped to say below 2V and 4V level

Vo(max) = 4VVo(min) = 2VVo(max) = Vf+Vref1(Assume Vf= 0.6)Vref1 = Vo(max) Vf

= 4 0.6= 3.4V

Vref1 = 3.4VVo(min) = -Vf+Vref 2Vref2 = Vo(min) + Vf

= 2 + 0.6

= 2.6 VVref2 = 2.6 V

The value of resistor R is chosen is

R = RfRr where Rf =10R = 10K Rr = 10M

Waveform:


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t

V0(V)

Vin(V)

10Vpp

t

Vm5V2 V

TF = 1/T

4 V

Transfer Characteristic:VO(V)

Vin(V)

2V

4V

4V

2V0

(ii) Square Wave Generator:

Circuit Diagram:

Vref 21.4V

BY 127

10 K

AFG

Vi10 Vpp

1KHz

+

-Vo

BY 127

Vref 11.4V

-

-

+

+

Design:

Let the output be clipped to say below +2V and -2V levelVo(max) = +2VVo(min) = -2VVo(max) = Vf+Vref1(Assume Vf = 0.6)Vref1 = Vo(max) Vf

= 2 0.6= 1.4V

-Vo(min) = -(Vf+Vref 2 )Vref2 = Vo(min) - Vf

= -2 (- 0.6)


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= -1.4 V The value of resistor R is chosen is

R = RfRr where Rf =10= 10K Rr = 10M

Waveform:

t

V0(V)

Vin(V)

10 Vpp

t

Vm5V2 V

TF = 1/T

-2 V

Transfer Characteristic:

VO (V)

Vin (V)

2V

-2V

-2V

2V

PROCEDURE:

1. The circuits are connected as per the diagrams.2. By giving input as 10V peak-to-peak outputs are observed and compared with the actualwaveforms (i.e. Vin(peak) > Vref).3. Different clipping levels are noted for all circuits by connecting input to 1st channel of theCRO and output to 2nd channel.4. The corresponding transfer characteristics are observed using X via Y mode.

RESULTS:

The following different clippers are verified:1. Positive Clipper

2. Negative Clipper

3. Double Ended Clipper

a. Slice Circuit

b. Square wave generator


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EXPERIMENT NO 8

DIODE CLAMPING CIRCUITS

AIM: To design and test positive and negative clamping circuits.

COMPONENTS: Diode BY127, Resistors, Capacitor, DC Regulated Power Supply,Connecting Wires and Board, ASG, CRO Probes.

DESIGN:

For all the circuits, the time constant RC>>TLet RC = 100T (Condition for Stiff Clamper)Assume T = 1msec i.e. F =1KHz

R = 10K100T (100) (1msec)C = -------- = -------------- = 10 f

R 10KC = 10 f

1. NEGATIVE PEAK CLAMPER OR POSITIVE CLAMPER

A) WITH POSITIVE REFERENECE

Circuit Diagram:

VR2.6V

BY 127

R

10 K

AFG

Vi10Vpp1KHz

+

-Vo

C10 f

-

+

Design:

The value of resistor R is chosen isR = RfRr where Rf =10R = 10K Rr = 10M

Design forVo(min) = +2V

Vo(min) = +Vref - Vf (Assume Vf = 0.6)Vref = Vo(min) + Vf

= 2 + 0.6Vref = +2.6V

Capacitor voltage, Vc = Vm + Vref - Vf


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Vo = +Vi + Vc = +Vi + [ Vm - Vf + Vref] (1)

From equation (1)

Vi Vo Vi(V)

Vo(V)

Theoretical Practical0 Vm - Vf + Vref 0 7Vm 2Vm - Vf + Vref 5 12-Vm - Vf + Vref -5 2

Waveform:Vin(V)

VO(V)

5V

12V

2V

T

f=1/T

-5V

10Vp-p

0 t(sec)

t(sec)0

B) WITH NO REFERENCE

Circuit Diagram:

BY 127R

10K

AFG

Vi10Vpp1KHz

+

-Vo

C10 f

Design:

The value of resistor R is chosen isR = RfRr where Rf =10 R = 10K Rr = 10M

Design for Vo(min) = 0V

From equation (1)Vo = +Vi + Vc

= +Vi + [ Vm - Vf + Vref] (1)


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Vref = 0VAssume Vf= 0.6V

Vi Vo Vi(V)Vo(V)

Theoretical Practical

0 Vm - Vf 0 4.4Vm 2Vm - Vf 5 9.4-Vm - Vf -5 -0.6

Waveform:Vin(V)

VO(V)

5V

9.4V

-0.6V

Tf =1/T

-5V

10 Vp-p

0 t(sec )

t(sec )0

C) WITH NEGATIVE REFERENCE

Circuit Diagram:

VR1.4V

BY 127

R10 K

AFGVi

10 Vpp1KHz

+

-Vo

C10 f

+

-

Design:

The value of resistor R is chosen isR = RfRr where Rf =10R = 10K Rr = 10M

Design forVo(min) = - 2V

Vo(min) = -Vref - Vf (Assume Vf = 0.6)Vref = - Vo(min) - Vf

= - 2 - 0.6= -1.4V

Capacitor voltage, Vc = Vm - Vref - Vf


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Vo = +Vi + Vc = +Vi + [ Vm - Vf - Vref] (1)

From equation (1)

Vi Vo Vi(V)

Vo(V)

Theoretical Practical0 Vm - Vf - Vref 0 5.8Vm 2Vm - Vf - Vref 5 8-Vm - (Vf + Vref) -5 -2

Waveform:Vin(V)

VO(V)

5V

8V

-2V

T

f=1/T

-5V

10Vp-p

0 t(sec)

t(sec)

0

2. POSITIVE PEAK CLAMPER OR NEGATIVE CLAMPERA) WITH POSITIVE REFERENCECircuit Diagram:

BY 127

R

10K

AFG

Vi10Vpp1KHz

+

-Vo

C10 f

VR1.4V

-

+

Design:The value of resistor R is chosen is

R = RfRr where Rf =10= 10K Rr = 10M

Design Vo(max) = +2V


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Vo(min) = +Vref + Vf (Assume Vf = 0.6)Vref = Vo(max) - Vf

= 2 - 0.6 = 1.4 VVref = 1.4V

Capacitor voltage is considered when diode conducting

Vi - Vc - Vref - Vf = 0Vc = Vi - Vref - VfOutput voltage +Vi - Vc Vo = 0

Vo = Vi - Vc= +Vi - [Vi - Vref - Vf]

= +Vi - [ Vm - Vf - Vref] (2)From equation (2)

Vi Vo Vi(V)Vo(V)

Theoretical Practical

0 -Vm +Vf + Vref 0 -3Vm + Vf + Vref 5 2-Vm -2Vm + Vf + Vref -5 -8

Waveform:Vin(V)

VO(V)

5V

-8V

2V

T

f=1/T

-5V

10Vp-p

0 t(sec)

t(sec)0

B) WITH NO REFERENCE

Circuit Diagram:

BY 127R

10 K

AFG

Vi10 Vpp1KHz

+

-Vo

C10 f


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Design:The value of resistor R is chosen is

R = RfRr where Rf =10R = 10K Rr = 10M

Design forVo(max) = - 2VVo(max) = -Vref + Vf (Assume Vf= 0.6)Vref= - Vo(max) - Vf

= - (- 2) + 0.6Vref = +2.6V (magnitude)

Capacitor voltage, Vc = Vm - Vref - VfVo = +Vi - Vc

= +Vi - [ Vm - Vf + Vref] (1)

From equation (1)

Vi Vo Vi(V)

Vo(V)

Theoretical Practical0 - [Vm - Vf + Vref] 0 -7Vm Vf - Vref 5 -2-Vm - 2Vm + Vf - Vref -5 -12

Waveform:Vin(V)

VO(V)

5V

-12V

-2V

T

f=1/T

-5V

10Vp-p

0 t(sec )

t(sec )

0

PROCEDURE:

1. The circuit is rigged up as shown in the circuit diagram.

2. A square wave of amplitude 10V peak-to-peak is given as input. (sine wave can alsobe input)3. Output is observed on the CRO for each circuit by putting the amplitude knob to DC

and should be compared with theoretical waveform.4. The different clamping levels should be noted for each circuit.

RESULT: The given waveform for both the positive and negative clamping is verified.

OBSERVATION:1. Only dc shift is observed at the output.2. The shape, time period and peak-to-peak amplitude of the output is same as input


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EXPERIMENT NO 9

CLASS-B PUSH PULL AMPLIFIERAIM: To determine the conversion efficiency of Transformer less Class-B Push Pullamplifier.

COMPONENTS: AFG, Load resistor (75, 10Watts), CRO, Power supplies,transistors(SL100, SK100)

CIRCUIT DIAGRAM:

AC

12 V

RPS

-12 V

RPS

75

10W

0.1f

SL 100

SK 100

0 VP -P

1KHz

0.1f

Vo(P-P)Vi

DESIGN:

Assume RL as 75 (10Watts) and VCC = 12V

When Power developed is maximum Vm = VCC

RL = Vm / ImIm = Vm /RL =Vcc/RL

= 12/75 = 0.16 A

Pdc = (2/)(VCC*Im)Watt= (2/)( 12 x 0.16)= 1.22W

Pac = V2CC/2RL= 122 / 2 x 75= 0.96W

% = Pac /Pdc*100 %= 0.96/1.22 * 100%= 78.6%


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Theoretical value of% is also 78.5%Hence choose RL as 75(10Watts)

CALCULATIONS:

Take Vm across the load resistor RL through CRO.Vm = VO(P-P)/2Im = Vm /RLPdc = (2/)(Vm*Im)WattPac = V2m/2RL

Conversion Efficiency, % = (Pac /Pdc)* 100%

OUTPUT WAVEFORM:

V0(V)

Vm

PROCEDURE:

1. Connect the circuit as shown in the fig and switch on the power supply.

2. AFG is set to 10V,1KHz sine wave applied to the input of the circuit

3. Measure output across the RL and not the value of Vm

4. Calculate the conversion efficiency

RESULT: Conversion Efficiency of Class-B Push Pull amplifier is =_______%


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EXPERIMENT NO 10

RECTIFIER CIRCUITS

AIM: To test half wave, full wave, bridge wave rectifier circuits with and without capacitorfilter. Determination of ripple factor, regulation and efficiency,

COMPONENTS: Transformer (12-0-12)V, Diodes (BY127), Power Resistor (75, 10W),Connecting Wires and Board, CRO Probes.

THEORY:

For Half Wave RectifierVdc = Vm / Vrms = Vm/ 2

Ripple factor, = Vac / VdcVac = (V2rms V2dc ) /Vdc

= [( Vm/ 2) 2 (Vm/ ) 2] / (Vm/ )= [( 1/ 2) 2 (1/ ) 2] / (1/ )

= 1.21

Efficiency, % = (V2dc / V2rms) * 100= [I2dc R / I2rms (R+Rf)] * 100

= [(Im/ ) 2R / (Im/ 2)2(R+Rf)] * 100= [(1/ ) 2R / (1/ 2)2(R+Rf)] * 100= [(1/ ) 2/ (1/ 2)2] * [R/ (R+Rf)] * 100= [(1/ ) 2/ (1/ 2)2] ( If R f


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Efficiency, % = (V2dc / V2rms) * 100= [I2dc R / I2rms (R+Rf)] * 100= [(2Im/ ) 2R / (Im/ 2)2(R+Rf)] * 100

= [(2/ ) 2R / (1/ 2)2(R+Rf)] * 100= [(2/ ) 2/ (1/ 2)2] * [R/ (R+Rf)] * 100= [(4/ 2) / (1/ 2)] ( If R f


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c) PRACTICAL DESIGN:

Vm from output figureAverage or DC value of voltage, Vdc = Vm/ rms value of voltage, Vrms = Vm/ 2

Vac = (V2rms V2dc )Ripple factor, = Vac / Vdc

Efficiency, % = (V2dc / V2rms) * 100% Voltage regulation, %R = [(VNL VmFL) / VmFL ]* 100

d) EXPECTED OUTPUT WAVEFORM:

t

V0(V)

Vin(V)

t

Vm

e)TABULAR COLUMN:

VNL =_________VVmFL =_________VVm =_________V

Vrms(V) Vdc(V) Vac(V) Ripple factor

Efficiency%

Voltage regulation% R

2. HALF WAVE RECTIFIER (HWR) with C- Filter:

a) CIRCUIT DESIGN:

Load Resistor:Assume Vdc = 17V, Idc = IL = 775mA; Rf = 8

RL = Vdc / Idc = 5 / 225mRL = 75RL = 75 , 10Watts (Std)


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Transformer:Vdc = (Vm / ) + Idc RfVm = (Vdc - Idc Rf)Vm = 16.99 VVrms = Vm / 2 = 16.99 / 2 = 12

12V is required as input voltage to the rectifier.Use 12 0 12V Transformer

Capacitor:

Choose C = 470 fAssume f = 50Hz, RL =75 ,10Watts

= 1 / 23fRLC = 0.163 = 0.163

Also the theoretically the value of is 0.163

b) CIRCUIT DIAGRAM:

230V

50HzAc

supply

BY127

RL75,10W

V0470 f

12V

0V


Vr (p-p) , Vm is taken from the output wave form

Vdc = Vm (Vr (p-p) / 2)Vrms = Vr (p-p) / 23 = Vrms / Vdc

%R = [(VNL VmFL) / VmFL ]* 100



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t

Vin(V)

t

Vm

Vr(P-P)V0(V)

With

C-filter

V0(V)

With

out

filter

t

e) TABULAR COLUMN:VmFL =_________VVNL =_________VVm =_________V

Vr(P-P)(V) VDC(V) Vrms(V) Ripple factor Voltage regulation% R

3. CENTER-TAPPED FULL WAVE RECTIFIER with out filter:

a) CIRCUIT DESIGN:

Load Resistor:

Assume Vdc = 11V, Idc = IL = 150mA; Rf = 8RL = Vdc / Idc = 5 / 150mRL = 73.33Choose RL = 75 , 10Watts

Transformer:Vdc = (2Vm / ) - Idc RfVm = (Vdc + Idc Rf)/2Vm = 16.96 VVrms = Vm / 2 = 16.96 / 2 = 11.96

12V is required as input voltage to the rectifier.


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Use 12 0 12V Transformer

b) CIRCUIT DIAGRAM:

230 V

50 HzAc

supply

BY 127

RL75 10W

V0

BY 127

12V

12V

0V


Vm is taken from the output wave formVdc = 2Vm / )Vrms = Vm/ 2Vac = (V2rms V2dc )

= Vac / Vdc

% = (V2dc / V2rms) * 100%R = [(VNL VmFL) / VmFL ]* 100


t

V0(V)

Vin(V)

t

Vm


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e) TABULAR COLUMN:

VmFL =_________VVNL =_________VVm =_________V

Vrms(V) Vdc(V) Vac(V) Ripple factor

Efficiency%


4. CENTER-TAPPED FULL WAVE RECTIFIER with C - filter:

a) CIRCUIT DESIGN:

Load Resistor:


Transformer:

Vdc = (2Vm / ) - Idc RfVm = (Vdc + Idc Rf)/2Vm = 16.96 VVrms = Vm / 2 = 16.96 / 2 = 11.96

12V is required as input voltage to the rectifier.

Use 12 0 12V TransformerCapacitor:

Choose C = 470 fAssume f = 50Hz, RL =75

= 1 / 43fRLC = 0.082 = 0.082



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b) CIRCUIT DIAGRAM:BY127

RL7510W

V047 0f

BY127

12V

12V

0V

230V

50HzAc

supply


Vr (p-p) ,Vm is taken from the output wave formVdc = Vm (Vr(p-p) / 2)Vrms = Vr(p-p) / (23)Ripple factor, = Vrms / Vdc

Voltage regulation, %R = [(VNL VmFL) / VmFL ]* 100



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t

V0(V)

With

out

filter

Vin(V)

t

Vm

t

Vr(P-P)V0(V)

With

C-

filter

e) TABULAR COLUMN:

VmFL =_________V

VNL =_________VVm =_________V

Vr(p-p) (V) VDC(V) Vrms(V) Ripple factor


5. FULL WAVE BRIDGE RECTIFIER without filter:

a) CIRCUIT DESIGN:

Load Resistor:


Transformer:Vdc = (2Vm / ) - Idc Rf


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VNL =_________VVm =_________V

Vrms(V) VDC(V) Vac(V) Ripple factor

Efficiency%


6. FULL WAVE BRIDGE RECTIFIER with C - filter:

a) CIRCUIT DESIGN:

Load Resistor:

Assume Vdc = 17V, Idc = IL = 225mA; Rf = 8

RL = Vdc / Idc = 5 / 225mRL = 75.5Choose RL = 75 , 10Watts (Std)

Transformer:Vdc = (2Vm / ) - Idc RfVm = (Vdc + Idc Rf)/2Vm = 16.96 VVrms = Vm / 2 = 16.96 / 2 = 11.96

12V is required as input voltage to the rectifier.Use 12 0 12V Transformer

Capacitor: Choose C = 470 fAssume f = 50Hz, RL =75

= 1 / 43fRLC = 0.082 = 0.082


b) CIRCUIT DIAGRAM:

230 V

50HzAc

supply

RL7510W

V0470 f

12V

12V

D1

D2

D3

D4

D1, D2, D3 ,D4 -- BY127

c) PRACTICAL DESIGN:Vr (p-p) ,Vm is taken from the output wave form


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Vdc = Vm (Vr(p-p) / 2)Vrms = Vr(p-p) / (23)

= Vrms / Vdc% = (V2dc / V2rms) * 100

%R = [(VNL VmFL) / VmFL ]* 100


t

V0(V)Without

filter

Vin(V)

t

Vm

t

Vr(P-P)V0(V)With

C-filter

e) TABULAR COLUMN:

VmFL =_________VVNL =_________VVm =_________V

Vr(p-p) (V) VDC(V) Vrms(V) Ripple factor


PROCEDURE:

1. The circuit is rigged up as per the circuit diagram.2. Input AC is applied & output waveform should be noted.3. Output voltage Vm is noted for rectifierwithout filter from CRO or multimeter. Output

voltage Vr (p-p) is noted for rectifierwith filter from CRO or multimeter ,4. With load resistor (RL), output voltage VNL is measured. The output voltage is with RL is

denoted by VFL. %R is calculated5. With C filter output waveform should be noted down % , % R& is calculated.

RESULT: The output waveform of Half wave rectifier, Center tapped full wave rectifier andBridge full wave rectifier is tested and respective % , and %R is calculated.


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EXPERIMENT NO 11

THEVENINS THEOREM & MAXIMUM POWER TRANSFERTHEOREM

1. THEVENINS THEOREM:

AIM: To verify THEVENINS THEOREM using DC circuit

COMPONENTS: Resistors, RPS, multimeter & milliammeter.

Circuit diagram:

RP S

V in

D C

I

0-100m A

R1

4 7 0

R2

6 8 0

R3

1K

RL

1KVL

+

-

A

B

Fig.1

Vin (V) IL(mA) VL(V)

234567


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RPSVinDC

R1470

R2680

R31K

Vth+

-

A

B

Fig2

Vin (V) Vth(V)

234567

R1

4 7 0

R2

6 8 0

R3

1K Rt h

A

B

R2

6 8 0

R1 // R3

3 2 0Rt h

A

B

Fig 3 Fig 4

Rth = ( R1 // R3 ) + R2 = (470 // 1K ) + 680 = 1K

RPSVthDC

I'L0-100 mA

Rth1K

V'L

Rth1K

+

-

A

B

Fig 5


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Vth (V) I'L(mA) V'L(V)

PROCEDURE:

1. Connect the components as shown in fig. (1). Vary the DC power supply set the voltage to2V load current IL & load voltage VL are measured & tabulated. Then vary power supply to3V, 4V, 5V, 6V and the corresponding values of IL & VL are noted.

2. The RL is removed as in fig (2) & voltage across the terminals A & B is measured, which isthe thevenins voltage (Vth).The Vth are measured for different values of input voltage & aretabulated.

3. The voltage source is removed & terminals A &B are shorted as in fig (3). The resistanceof the circuit is measured across the terminals P & Q using a multimeter or by using a ohmslaw. The resistance in the thevinins resistance (Rth).

4. The circuit is connected as shown in the fig (4). The values of DC supply voltage areadjusted to thevenins voltage. The corresponding values of load current & load voltage arenoted. The experiment is repeated for different values of thevenins voltage & thecorresponding valuesm of I'L & V'L are tabulated.

RESULT:

It is found that VL & IL are obtained from the complex network are equal to I'L & V'Lare obtained from the thevenins equivalent network.

B. MAXIMUM POWER TRANSFER THEOREM:

AIM: To verify maximum transfer power transfer theorem.

COMPONENTS: Resistance in the range of 100 to 300, a DC power supply, multimeter,a potentiometer or a resistance box and connecting wires.

CIRCUIT DIAGRAM:


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RPS

Vin5V

DC

I

0-100 mAR

RL-

+

+ -

EXPECTED GRAPH:

RL inOhmsRL= R

Pmax

PowerinWatts

TABULAR COLUMN:

1. When R = 1K

SL No R L() I (mA) P = I2 RL (Watts)

2. When R= 470

SL no R L() I (mA) P = I2 RL(Watts)

PROCEDURE:

1. The circuit is connected as shown in the fig(1) for R=1K. And set the power supply to5V.


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2. The load resistance RL is varied and the corresponding values of current are noted andtabulated. Power transferred to load is calculated using the relation P= I2 RL.A plot of loadresistor VS power is drawn as in figure (2)

3. The experiment is repeated for different values of R (= 470).

RESULT: Maximum power is transferred when RL = R

EXPERIMENT NO 12

SERIES & PARALLEL RESONANT CIRCUIT

1. SERIES RESONANT CIRCUIT

AIM: To find the resonant frequency, band width and Q-factor of the given Series Resonantcircuit.

COMPONENTS: ASG, DIB, DCB, Millimeter (0- 100A) A, Multimeter & connectingwires.

CIRCUIT DIAGRAM:

L

8.86 mHAFGVin

10Vpp1KHz

I

0-100 mA

C10.47f

Fig 1: Circuit diagram for f = 2.5 KHz

FORMULAS:

At resonance, XL = XCWrL= 1/ WrCWr2 = 1/LC

fr = 1 / 2 LCDESIGN:

Forfr =2.5KHz


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Assume C = 0.47fL = 1/ (2 fr) 2 C

= 1/(2 x2.5m) 2(0.47)L = 8.86 mH

EXPECTED GRAPH:

f1 f2Frequency in

Hzfr

Imax

I in

mA

0.707Imax

TABULAR COLUMN:Vi = ________________V

Frequency (Hz) I (mA)0.5K1.0K1.5K

2.0K2.1K2.2K

.

.

.

.2.8K2.9K3.0K3.5K

4.0KPROCEDURE:

1. The connections are made as shown in the figure.2. The values of L, C are fixed.3. For each frequency, current is noted and the frequency Vs current is plotted. The frequency

at which current is maximum is known as the resonant frequency (fr)4. From the graph, bandwidth is calculated5. The same procedure is repeated to calculate the resonance frequency by varying L & C

(keeping frequency and voltage constant)


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f1 f2 Frequency i nHz

fr

Imin

I in

mA

1.414Imin

TABULAR COLUMN:V = ___________________ V

Frequency (Hz) I (mA)0.5K1.0K1.5K2.0K2.1K2.2K

.

.

..2.8K2.9K3.0K3.5K4.0K

PROCEDURE:

1. The connections are made as shown in the figure.2. The values of L, C are fixed.

3. For each frequency, current is noted and the frequency Vs current is plotted. The frequencyat which current is maximum is known as the resonant frequency (fr).

4. From the graph, bandwidth is calculated.5. The same procedure is repeated to calculate the resonance frequency by varying L & C

(keeping frequency and voltage constant).

RESULT:1 f ( ti l) H

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