Dynamics of charge storage in acoustic charge transport devices on GaAsBruce C. Schmukler Citation: Journal of Applied Physics 69, 3335 (1991); doi: 10.1063/1.348562 View online: http://dx.doi.org/10.1063/1.348562 View Table of Contents: http://scitation.aip.org/content/aip/journal/jap/69/5?ver=pdfcov Published by the AIP Publishing Articles you may be interested in The effects of grating size on acoustic charge transport properties on GaAs J. Appl. Phys. 71, 3853 (1992); 10.1063/1.350875 Heterojunction acoustic charge transport devices on GaAs Appl. Phys. Lett. 52, 18 (1988); 10.1063/1.99325 Simple theory of buried channel acoustic charge transport in GaAs J. Appl. Phys. 55, 413 (1984); 10.1063/1.333089 Charge transport by surface acoustic waves in GaAs Appl. Phys. Lett. 41, 332 (1982); 10.1063/1.93526 Acoustic readout of charge storage on GaAs Appl. Phys. Lett. 25, 99 (1974); 10.1063/1.1655406

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Dynamics of charge storage in acoustic charge transport devices on GaAs Bruce C. Schmuklef) Coordinated Science Laboratory University of Illinois, Urbana, Illinois 61801

(Received 29 October 1990; accepted for publication 18 December 1990)

Acoustic charge transport devices in GaAs are charge-coupled devices that typically transport charge at the velocity of sound. However, charge transport can be temporarily inhibited by electrical barriers in the transport channel, a process known as charge storage. In this paper the fundamental properties of two methods of charge storage, single-packet and double-packet, are investigated and compared using theory and experiments. A 1-D storage model is developed which provides insight into the dynamics of the charge storage process. The impact of charge storage on device frequency response is analyzed. Storage capacity is experimentally characterized as a function of storage voltage. The key factors that limit storage capacity are found to be intercell diffusion, surface charge extraction, barrier transition times, and delay-line charge capacity. Furthermore, double-packet storage has been found to provide higher storage capacity with less storage voltage than single-packet storage.

I. INTRODUCTION

Acoustic charge transport (ACT) devices in GaAs are high-transfer efficiency charge-coupled devices that have attracted attention in recent years.le3 Charge is transported by the sinusoidal voltage wave that accompanies a surface acoustic wave (SAW) in GaAs, instead of by clock pulses as in more conventional charge-coupled devices. Using ACT devices, a variety of signal processing functions can be performed.2>4’5

Most of the attention concerning ACT in GaAs has been focused on pure delay-line devices; i.e., devices in which the charge continuously travels at the velocity of sound. The charge transport process can be momentarily stopped, however, by applying barrier potentials to the sur- face electrodes, thereby overpowering the synchronous transport field of the surface wave. This process is known as charge storage. By using charge storage, an ACT device can hold signal bursts for a longer time than a pure delay- line device and can also allow a signal to be integrated over a specified time.

Charge storage adds more diversity to the possible ap- plications of ACT. Pure delay-line ACT devices have been used to make delay lines,6 correlators,2 convolvers,’ and transversal filters.4 Charge storage ACT devices, on the other hand, have the potential of being utilized as rf mem- ories,2 imagers,7 or parallel-to-serial converters.2

It has been found previously that virtually any quan- tity of charge can be stored behind a single electrode, a result of the screening effect of surface Schottky metaliza- tion.* Single-barrier storage generally does not preserve the input signal, however. Practical storage structures, there- fore, require periodic barrier arrays. This limits the storage capacity, which is the amount of the charge that can be stored in a cell. Prior to this work, little regarding the dynamics of charge storage has been studied. In particular,

“Presently at Watkins-Johnson Co., Palo Alto, CA 94304.

the factors that limit storage capacity have not been pre- viously identified.

The type of device used in this investigation is depicted in Fig. 1. The device has an n-type active layer on a semi- insulating substrate. The transducer and reflector create a unidirectional acoustic wave with a wavelength of 8 pm. The active layer is depleted of charge by front gating and substrate bias, which creates a buried charge-transport channel. Typical charge-transport depths are 2.0-2.5 pm. Proton isolation delineates the channel in the lateral direc- tion.’ An rf signal can be applied to the input, where it is automatically sampled every wave interval. The sampled discrete charge packets are then transported to the output where they are destructively sensed.

Surface electrodes or arrays can be placed between the input and output of the device in order to control charge. In the experimental devices used in this investigation, sev- eral different barrier arrays are placed in the same channel-they are denoted I to V in Fig. 1. Barrier-types II, III and V are used for charge-storage experiments. One period of each of these barrier types is shown in Fig. 2. Barrier-type II has a periodicity of one acoustic wavelength il, and barrier-types III and V have a periodicity of 2,L Barrier-type II stores one charge packet per cell and there- fore provides single-packet storage, while barrier-types III and V store two charge packets per cell and therefore pro- vide double-packet storage.

In this paper, the properties of single-packet and double-packet storage are investigated and compared. Double-packet storage in ACT devices is demonstrated for the first time, and it is found that double-packet storage can provide some significant advantages over single-packet storage. A 1-D storage model is developed which provides insight into the dynamics of charge storage. Other topics covered are optimal charge-transport depths for ACT stor- age devices, the impact of storage and release on frequency

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semi-hsulathg QaAr

d substrate l&s 0 schottky

I Ohmic

fZ3 Roton Isolation

FIG. 1. Experimental ACT device. Several different barrier arrays lie in the same channel.

response, and storage capacity measurement techniques. Through experiments and theory, the key factors that limit the fundamental storage capacity of ACT storage devices in GaAs are identified.

II. I-D MODEL

The following 1-D model reveals the physics concern- ing the charge storage process in a simple fashion. In this model both the wave potential and barrier potential are assumed to be 1-D in nature and have sinusoidal variation.

The single-packet barrier electron potential is given by

v,= VBO cos(kx), (1)

where k is the wave number and the double-packet barrier electron potential is given by

v,= VBO cos(kx/2) (2)

The wave electron potential is

VW= V,cos(kx - wt). (3)

At a given instant, the phase at x=0 is defined as

e=wt. (4)

The total potential VT is then the sum of the barrier po- tential and the wave potential

VT= v, + VW (5)

II 2 itwiLL 1 1

V’ V‘

I m ,:_A ?cAI

P dT-?T -+~-A

V’ V-

xz A;’ 1.6 1.6

- lpm

FIG. 2. One period of barrier-types II, III, and V. II has a periodicity of 1. III and V have periodicities of 2,L

1 -- b) Y-----u-)

Wave

-l-- A ’ Potential

8 = o”

“El L “w

Cc) ). ~~~~l “B$ “w

1

(4 by----?' -1 --

Total x Potential

h B= 180°

Total L I>

h ’ x Potential

8 = 270°

FIG. 3. 1-D model for single-packet storage.

The barrier potential, wave potential, and total potential at several different phases are depicted in Fig. 3 for single- packet storage and Fig. 4 for double-packet storage.

In single-packet storage, the shallowest potential well and, therefore, lowest storage capacity occur when 8 = 180”. Here, the wave maximally cancels the confining barrier field. The resulting total potential at this phase is sinusoidal with amplitude VW, where

VFW= VBO - VW0 (6)

At this phase, 1-D theory2”‘*” can be used to analyze the capacity of the total potential using VWE as the wave po- tential. Clearly, there is no storage capacity unless VBo > VW0 which can be otherwise stated that the barrier field must be greater than the wave field. Increasing VB in- creases the storage capacity. For the storage capacity to equal the delay-line capacity, VwE must equal Vwa which implies that the barrier potential must be twice the wave potential, VBO = 2 VW0

The dynamics of double-packet storage are slightly dif- ferent. The charge is continuously redistributed between two charge packets as the phase of the SAW with respect to the storage cell changes. At 8 = 0” two distinct charge packets exist. The critical phase is 8 = 90”; here the max- imum wave field and barrier field are aligned. The maxi- mum barrier field EB must overcome the maximum SAW field Ew and charge field EC in order to ensure that charge is not transported over the barrier. Let the total field at the critical phase be E,

E=EB+EcfEw (7)

3336 J. Appl. Phys., Vol. 69, No. 5, 1 March 1991 B. Schmukler 3336

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‘-- G Wave (b) :,r->&p+?-.J> X Potential

-l-- h 2h e= o”

A --

vB+ VW ,. r. 1 ‘n Total

(d) ) y-y- : n> X Potential -l-- 2h El= 9o”

vB+ vW

, . Total

1 1) X Potential -l-- 9= 270°

FIG. 4. I-D model for double-packet storage.

Then

00 (8)

is the storage condition. If the storage condition is satisfied, all of the charge from the leading packet should be redis- tributed to the trailing packet as opposed to being trans- ported over the barrier. This process continues. The new single-charge packet propagates forward, is split into two and is recombined into one if the storage condition is sat- isfied.

At the critical phase, the wave potential maximally cancels the barrier potential; this presents the stored charge with its lowest diffusion barrier height and best chance to escape from the cell. A minimum estimate of the diffusion barrier height V, can be obtained by

s 2A

vb> Edx. A

(9)

The actual vb may be larger. Evaluating (9) and using (7) to obtain EB,

v,>4vwo+&(2rr--)/k. (10)

EC depends on the number of carriers in the cell N. If N is limited by the number of carriers that can be carried by a single wave crest, then - Vwok < EC < 0. If EC = - Vwok

vb> 1.7 v&‘O

which is a minimum estimate of Vb

(11)

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A diffusion barrier height of 1.7 VW0 is a very substan- tial deterrent to diffusion between cells. In addition, actual values will most likely be greater. Equation (9) evaluates only part of vb and a real device will provide partial screening of EC by surface metalization. Therefore, diffu- sion is not predicted to be a key limiting factor of storage capacity in double-packet cells, provided the storage con- dition is satisfied.

III. TRANSPORT DEPTH

An estimate is desirable for appropriate charge- transport depths ym for charge storage ACT devices. In delay-line devices, the peak wave potential V, occurs at y=O.45/2. Therefore, the deeper y, is, generally, the greater is the charge capacity of the wave. However, greater values of ym cause more frequency response rolloff in the nondestructive sense response l2 and create fabrica- tion difficulties. As a compromise, for delay-line devices ym = 0.M is typically used. Charge storage devices have the added complexity that surface electrodes must be able to control charge transport with reasonable voltages; this can alter acceptable values of y,.

The magnitude of the SAW potential as a function of depth13 VW(y) and the maximum x-directed barrier field as a function of depth for the barrier structure of interest are required to estimate optimal y, for charge storage ACT devices. The maximum x-directed barrier field per applied barrier voltage, denoted {, can be obtained by solv- ing for the potentials using finite differences. Since the delay-line charge capacity N,, places an upper limit on storage capacity, optimizing N,, per storage volt should yield the optimum ym. N,, is approximately proportional to VW(y) - VwB,2 where Vws is the barrier offset and rep- resents the portion of the wave potential that is used to create a diffusion barrier between charge packets.‘OY” A typical value of VW8 is close to 0.3 V at room temperature. The storage voltage is inversely proportional to 6. Hence,

O(Y) = [V,(Y) - V,lC (12)

is a function that has a maximum value when N,, per storage volt is optimized. The absolute value of O(y) is meaningless; it is the trend with y that matters.

Figure 5 shows O(y) for barrier-types II, III, and V of Fig. 2. Barrier-type II provides single-packet storage and barriers III and V provide double-packet storage. As can be seen, y, _ - 0.25A tends to optimize single-packet storage capability and y, z 0.3il tends to optimize double-packet storage capability. Single-packet storage is optimized at a slightly shallower y, than normal delay-line devices, which will cause a charge capacity reduction. They, for double- packet storage is more consistent with normal delay-line devices. The barrier fields for double-packet storage do not decay as fast withy as the barrier fields for single-packet- this allows operation at deeper ym.

These results are only approximate and are meant to be a rule of thumb. Experimentally, ym is difficult to control consistently; it depends greatly on the material properties of the substrate.

B. Schmukler 3337

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2 looor -1

FIG. 5. Determination of the optimal charge-transport depth for the different storage cells. The optimal depth in wavelengths is where the optimizing function peaks.

IV. 2-D DIFFUSION LIMITED STORAGE CAPACITY

The I-D model is good for predicting trends, but be- cause it does not include 2-D effects, it cannot be used to predict real charge capacities. For this reason, the charge screening method to estimate charge capacities is devel- oped, the details of which can be found elsewhere.” In this section the charge screening method is used to analyze the storage capacity of a single-packet storage example to pro- vide trends of storage capacity with storage voltage V,,. The charge screening method can also be used to verify that diffusion-limited storage capacity is not a key factor in double-packet storage.

The storage capacity for a single-packet storage cell with type II barriers, a donor density Nd= 1015 cm - 3, ym = 1.9 pm, il = 8 ,um and peak SAW potential Vo=0.6 V is analyzed using the charge screening method. The critical SAW phase for determining storage capacity is 13 = 180”. For this phase, the rate of carrier leakage from the stored charge packet, denoted Js, is determined as a function of carrier load N for storage voltages from - 4 V to - 8 V. The carrier load is proportional to storage capacity.

Figure 6 shows the carrier load N as a function of VsT with Js as a parameter. For a constant leakage rate

Js, N increases with Vsr from - 4 V to - 6 V, but then decreases from - 6 V to - 8 V. Further analysis of the components of J, shows that intercell diffusion dominates between - 4 V to - 6 V for this theoretical device, and diffusion of charge to the surface electrodes dominates be- tween-6Vto -8V.”

The fundamental storage capacity of a single-packet cell is diffusion limited and the barrier potentials provide the intercell diffusion barrier. Therefore, the barrier field must overcome the SAW field in order to inhibit charge transport and also provide a diffusion barrier. When inter- cell diffusion dominates, increasing storage voltage is ex- pected to increase storage capacity.

Also apparent from the simulation results is the possi- bility of charge extraction via surface electrodes. Increas-

FIG. 6. Theoretical storage carrier load as a function of storage voltage for a single-packet storage cell.

ing Vsr not only increases the intercell confinement of the charge, it also pushes the charge closer to the surface. If the doping density is not sufficient to confine charge in the channel in the presence of VsT, leakage of charge to the surface electrodes can limit the storage capacity. In this case, increasing Vs, decreases the storage capacity.

When intercell diffusion dominates, the following model can be used to simulate frequency response. The fractional loss of signal charge a is given by

Js1 P a=- Nlf

, (13)

Tp=barrier pulse duration

N,.r= carriers associated with the rf signal.

The quiescent carrier load NdC and N,.r combine to form the total carrier load N.

N=Nd+ Ndc. (14)

Since the charge and fields for 8 = 180” are symmetric about the center of the packet, it is reasonable to assume the intercell leakage is evenly split between adjacent cells. Then, the impulse response is

h(r)=+- Ts) + (1 -a)S(t) +;&r+ Ts),

(15)

where T, is the SAW period. The frequency response is

H(f) = (1 - a) + a cosmf/f~s) (16) where fs is the SAW frequency. Intercell diffusion causes a rolloff in N(f), which is different from that of a linear

3338 J. Appl. Phys., Vol. 69, No. 5, 1 March 1991 B. Schmukler 3338

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transfer inefficiency response as the loss of charge from a sample is a one-time loss as opposed to a recursive loss.

When surface charge extraction occurs, the signal charge is irretrievably lost. Since the charge loss depends on N,+ the resulting impact on frequency response will be nonlinear with the signal. However, in the small-signal case, the charge loss can be assumed to be constant for all charge packets, regardless of size. The resulting small- signal frequency response is expected to show attenuation for all frequencies as opposed to rolling off with frequency when intercell diffusion dominates.

The charge screening method was also used to analyze a double-packet storage cell with type III barriers, yrn = 2.4 pm and other parameters that are the same as for the single-packet simulation. The trend of the 1-D theory was verified, and the storage condition is violated before the intercell diffusion becomes significant. Violation of the storage condition leads to the possibility that charge can be transported over the barrier even though a significant dif- fusion barrier exists. Increasing Vsr above the threshold voltage of storage is not expected to increase storage ca- pacity. In addition, surface charge extraction effects were not observed for double-packet simulation.

V. THEORETICAL IMPULSE RESPONSE OF STORAGE AND RELEASE

The intrinsic effect of the storage process on the device frequency response is analyzed in this section. To calculate this intrinsic response, the barriers are assumed to rise and fall instantaneously and at the appropriate phase of the wave potential (the effect of finite barrier rise times are looked at in the next section). The impact of charge stor- age on the frequency response can then be viewed as a storage response, which represents the integration of input signal samples into a single-storage sample, and a release response, which represents the redistribution of the stored charge back into the crests of the wave potential.***i4

The storage response depends on the number of input samples M integrated into one storage sample. If Ts is the period of the SAW, the input samples are spaced T, apart and the storage samples are spaced MTs apart (the barrier period is assumed to be M acoustic wavelengths). If g( t) is the input signal and Q(f) is the stored signal, then the nth storage sample at a time t = nMTs is

M-l Q(nMTs) = mzo g(nTs - mTd. (17)

In order to obtain Q(f), the Fourier transform of the stored signal, in terms of G(f), the Fourier transform of the input signal, the stored signal can be viewed as the sum of M delayed input signals, each one delayed Ts more than the previous one. This resulting sum is then decimated to leave only every Mth sample. The resulting relation be- tween Q(f) and G(f) is

e- j2TCf[m7-,+ CM- 1)~,/21 , (18)

I M=l

0 20 40 60 80 100 Percent of Nwlst Frequency

FIG. 7. Theoretical storage response for M input samples per storage sample. The Nyquist frequency is fs/2M.

where the impulse response is arbitrarily centered about c = (M - 1)Ts/2. The ratio of Q(f) to G(f) is the storage response HST (f). The storage response is plotted as a function of normalized frequency in Fig. 7 for several different values of M.

Single-packet storage does not have an intrinsic storage response, provided the storage cell has a capacity large enough to hold the charge. The charge packets are kept separate and do not mix.

For double-packet storage, if two input samples are combined into a single storage sample, then M=2 and the intrinsic storage response is

f&T (f ) = COS ( rf /f S ). (19)

This is the simplest method of experimentally imple- menting double-packet storage and results in 3 dB of rolloff at the Nyquist frequency offs/4. However, if input signal sampling can be inhibited for every other wave crest, then one storage sample contains only one input sample, and the storage response is eliminated. In general, the intrinsic storage response can be eliminated by only storing one signal sample per barrier cell.

The release response is independent of input sampling, but is does depend on the fraction of charge released in trailing packets. The general impulse response of release ha,(t) into M packets is

M-l

ARE(t) = 2 a(m) 6(t - mTs), (20) m=o

where a(m) represents the fraction of stored charge re- leased into the mth packet, and the sum of the a(m)% is unity (indicating that charge is conserved upon release). If all the stored charge can fit into one charge packet, then the release response can be eliminated.

Single packet storage does not have a release response. The relaxation time of the charge is very fast compared to the period of the wave, and the charge should theoretically be able to move from its storage distribution to transport distribution without loss of signal integrity.

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f0 t<o

FIG. 8. Transition time equivalent circuit.

For double-packet storage, the worst release response occurs when the stored charge is evenly split between two charge packets. This produces a response that is function- ally the same as the storage response in ( 19) and results in 3 dB of extra rolloff at the Nyquist frequency offs/4. If all of the charge can fit into a single wave crest and the bar- riers are properly timed, the release response is easily elim- inated.It is interesting to note that the worst combined storage and release response for double-packet storage causes 6 dB of rolloff at the Nyquist frequency, a quantity that is also verified by experiments.

VI. INFLUENCE OF BARRIER TRANSITION TIMES

When the barriers are fully raised, the barrier structure and voltage limit the storage capacity; however, if the bar- rier transitions are not speedy and appropriately timed, then the wave potential can be presented with excessive perturbing channel fields resulting in a loss of delay-line charge capacity. When the delay-line capacity is less than the fundamental storage capacity of the cell, it will domi- nate the total storage-device capacity. Long barrier transi- tions can reduce storage-device capacity to almost zero by this means. The influence of barrier transition times is an important consideration not to be overlooked.

The key factors limiting transition times are the capac- itance of the barrier array C, and the source resistance of the pulse circuit Rp Figure 8 shows a simple equivalent circuit for analyzing transition times. C, and RI represent parasitic capacitances and internal barrier resistance. C, is fixed by the length of the barrier array. C, and RI can be kept to a minimum by using large low resistance busbars and by providing a good ground for the storage electrodes, the electrodes to which barrier potentials are not applied. RS is the principle factor that can be reduced to decrease transition times. Transition times, therefore, are more of a problem of the barrier driver circuit as opposed to a fun- damental device limitation.

For single-packet storage, the influence of rise times is relatively straightforward. By the time point G of the wave, shown in Fig. 3, aligns with E of the barriers, the barriers must be fully raised to provide full charge confinement at the critical phase 8 = 180”. Two functions are candidates for modeling the barrier voltage in time: the exponential and the ramp. Because practical experience shows the ramp function is more prevalent, it shall be used.

The barriers are assumed to start rising at t=O and are assumed to be fully raised at t = T,, the time when G and E coincide. The ramp function r(t) is then

r(t)= t/T,

I

O<t<TR. (21) 1 TR<t

If EJx) represents the static x-directed barrier electric field at y, obtained by solution of the Laplace equation for the applied barrier voltage, then the instantaneous x-directed barrier electric field at y,, EXs(x,t) is given by

&(w) =r(Wxfb)- (22)

The maximum EJx,t) encountered by point G of the wave is the desired quantity to estimate charge capacity loss. If EJx) is assumed to be sinusoidal in nature, G will have the position

x=v,(t - T,) + 3U4, (23)

where v, is the sound velocity. Let E,(t) be EJx,t) en- countered by G as the wave propagates; then, using (23) in (22)

E;;(t) =r(t)E,du,(t - TR) + 31141, (24)

Let t* be the time at which E&t) is maximized for t be- tween t=O and the time G reaches E, then EG( t*) is the maximum perturbing field the wave potential must over- come. Using an empirical expression for charge capacity loss, 2110**1 the delay-line carrier capacity N,, as a function of the unperturbed capacity Ned) is approximately

E&t*) kl~,(Y,) - VW?] 1.

(25)

When N,, is less than the fundamental storage capacity Nsr, the barrier transition times limit the overall storage- device capacity.

Possibly the most significant result of the above theory for single-packet storage is that for

T, < 3 T,/4 (26)

the barrier transition times do not impact storage-device charge capacity. Once G reaches B, the wave and barrier potentials start to add together instead of cancelling. Therefore, the instantaneous delay-line capacity is in- creased once the wave reaches this point.

The barrier-fall process for single-packet storage is the time-reverse process of the rise. Hence, if the falltime T, is also less than 3TS/4, it should not impact storage-device charge capacity.

The effects of barrier transition times on double-packet storage are more complicated than for single-packet stor- age. The effects depend on the mode of operation of the storage device and the degree to which each of the two wells are filled with a given sample. Some general conclu- sions can be drawn, however. If input sampling is inhibited for every other wave crest, then TX < 3TS/2 will not affect the signal, because point G of the wave, which is shown in Fig. 4, can move from B to E without loss of charge. If input sampling is not inhibited for every other wave crest, then the barriers must be up by the time G moves from B to C in order to not reduce the delay-line capacity; this

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implies T, < TJ2. The pulse fall process for double-packet storage is, unfortunately, not the time-reverse process of the pulse rise. In order not to perturb the charge capacity of the first packet over the barrier upon release, the barriers must fall in the time that G moves from C to D, i.e., TF < Ts/2, but if the barriers fall from C to F, corresponding

to T, < 3Ts/2, the charge in a stored sample will reside in two adjacent charge packets and will not intermingle with the charge from other storage cells.

In practice, the criteria given above for double-packet storage may be more stringent than necessary as the wave crests may not be completely filled. In fact, they may only be half full at times. If the wave crests are not full, then more perturbation due to longer transition times can be tolerated without a loss of signal integrity.

VII. EXPERIMENTAL RESULTS

The device used for experimentation is depicted in Fig. 1. Barrier-types II, III, and V are used for storage experi- ments and a period of each is shown in Fig. 2. The input and input gate are used to inject a charge burst into the device, and the barrier array used for storage is chosen by adjusting the delay between the injection pulse and the barrier pulse. The signal charge is then destructively sensed at the output upon release. The width of the channel is 400 pm-

The barrier electrodes are the V- electrodes and are used to stop charge transport. The storage electrodes are the Yt electrodes; the stored charge resides under them. For these experiments, the storage electrodes are grounded, and a negative pulse is applied to the barrier electrodes.

Two types of measurements are made: time-domain measurements and frequency-domain measurements. The time-domain measurements are required to obtain the cur- rent amplitude of the injected pulses, but attempting to quantify the storage capacity in the time-domain can lead to unreliable data. A more quantitative measure of storage capacity can be obtained by monitoring the rolloff associ- ated with a small rf signal. In this way, the storage capacity can be measured for a constant rolloff value, which leads to reliable results. However, measuring the frequency re- sponse of an ACT device in storage mode is not simple.

A drawing of the output pulse and superimposed small rf signal is shown in Fig. 9(a). Unfortunately, the spec- trum of the pulse masks that of the small signal. Hence, direct measurement of the small-signal frequency response would be futile. The remaining diagrams of Fig. 9 show the technique used to overcome this problem. The output sig- nal first goes through a high-pass rc filter, as shown in Fig. 9(b). The response is then gated to eliminate the pulse transients; hence, an rf burst is created. The burst has a sin x/x spectrum, but when the input frequency is swept, the peak of the spectrum will trace out the frequency re- sponse of the device. This last operation is the inherent function of a network analyzer, to simultaneously sweep transmitted and received frequencies.

The rf test set used is shown in Fig. 10. A frequency generator is used to create 354 MHz to drive the SAW

3341 J. Appl. Phys., Vol. 69, No. 5, 1 March 1991

d) H(f) b, >

f

FIG. 9. Pulsed frequency response measurement technique. (a) output pulse and superimposed rf signal. (b) pulse after high-pass filtering. (c) gated output pulse. (d) resulting frequency response.

transducer. Before the signal is amplified and fed to the transducer, part of it is bled to an ECL frequency divider. The purpose of the ECL frequency divider is to exactly synchronize the barrier transitions with the SAW fre- quency. The ECL divider triggers the input gate pulse, which injects a charge train into the device (the gate is normally biased to inhibit charge injection). The gate pulse generator then triggers the barrier pulse generator. The barrier pulse is amplified and fed to the device barriers.

Up to this point, the equipment used for time-domain and frequency-domain measurements has been the same.

1 ECL 1 Gate 1 1 Barrier uh3se r 01

Shi fter Frequency Generator

Pulse Generator

Trig In Trig Out* out (+I I _

_-zv

Time Domain Connections

Frequency Domain Measurementa

FIG. 10. Diagram of measurement test set.

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For time-domain measurements no signal is applied to the device input, and the output signal goes directly through a preamplifier to an oscilloscope, which is triggered by the gate pulse generator. For frequency-domain measure- ments, a network analyzer supplies the device input signal. The output signal passes through a high-pass rc filter and then through a preamplifier. The signal is gated using an rf switch, as described previously. The pulse generator used to operate the rf switch is triggered from the barrier pulse generator. The signal then returns to the network analyzer.

The procedure used to characterize storage capacity is as follows. The barrier pulse width is adjusted to be exactly 4Ts. The delay on the barrier pulse generator is adjusted to store charge in the desired barrier array and to fill the entire array. Next, the “zero charge” threshold voltage of storage is measured in the time domain. This is done by injecting a small quantity of charge into the channel (AI- 1 PA) and increasing the barrier voltage until the signal pulse is delayed Tp over the normal delay of the device. The minimum voltage that accomplishes charge storage is the threshold voltage of storage.

The threshold voltage is first measured to ensure that the device is operating in storage mode; the storage capac- ity is then best obtained while monitoring the frequency response. To obtain data in the frequency domain, the de- lay and pulse width on the rf switch pulse generator are adjusted to maximize the length of the rf burst after the output gating process depicted in Fig. 9(c). The phase shifter is also adjusted to minimize rolloff.

The test set is now ready to characterize storage ca- pacity. The barrier voltage is set to a value greater than or equal to the measured threshold voltage of storage. The injected current pulse amplitude AZ is increased until 3 dB of extra rolloff is observed at the Nyquist frequency. The Nyquist frequency for single-packet storage is 177 MHz and for double-packet storage is 88 MHz. This u is then measured in the time domain. The procedure is then re- peated for another barrier voltage.

The following experimental data are obtained using the same device parameters. The charge-transport depth is es- timated to be 2.1 pm. The amplitude of the peak shorted surface potential is estimated to be 0.6 V from transducer insertion loss measurements. The lo%-90% barrier rise times are measured to be 1.9 ns.

Figure 11 shows a vivid demonstration of double- packet charge storage. It shows the output pulse for delay- line operation and the same for storage operation. The charge from every two charge packets is integrated into one packet by the storage process. Upon release of the charge, every other charge packet is empty, demonstrating the capability of double-packet storage barriers to release a single charge packet even when two packets are trans- ported into the cell. Barrier timing is critical to achieve such operation. It should be noted that a low-pass filter (LPF) with a cutoff frequency of 225 MHz is used to obtain this picture as opposed to an LPF with a cutoff frequency of 120 MHz normally used to obtain frequency- domain data; this is necessary in order to observe individ- ual charge packets.

20 ns/dv (4

20 ns/div 0’))

FIG. 11. Double-packet storage in the time domain. (a) delay-line re- sponse. (b) storage response.

Figure 12 shows a typical frequency response in stor- age mode for single-packet storage. The given response is with respect to the normal delay-line response and, there- fore, should be considered the frequency response of the storage process. The single-packet response is reasonably flat up to its Nyquist frequency of 177 MHz. This demon- strates the ability of single-packet storage to preserve signal integrity. The exact cause of the 1 dB of perturbation is not presently known. It is speculated that a subtle difference between acoustic /z and barrier period, ringing in the bar- rier pulse or a residual response of the measurement system might be the cause.

The double-packet frequency response in Fig. 13 shows the residual 3 dB of rolloff at the Nyquist frequency result- ing from the integration of two input samples into a single

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FIG. 12. Frequency response of single-packet storage. VsT = - 7.6 V.

3342 J. Appl. Phys., Vol. 69, No. 5, 1 March 1991 8. Schmukler 3342

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50 Frequency (MHZ)

FIG. 13. Frequency response of double-packet storage for barrier-type V. v,, = - 4.0 v.

storage sample. This is the same amount of rolloff pre- dicted in Sec. V. In theory, this rolloff could be eliminated by inhibiting input sampling for every other wave crest. It is interesting to note that this is the least rolloff obtainable by tuning the phase shifter in the test set. When the phase shifter was adjusted for the worst rolloff for the same AI, the observed rolloff at the Nyquist frequency was 6 dB. The extra 3 dB of rolloff is believed to be a result of the splitting of the storage sample into two charge packets upon release, as described in Sec. IV.

Figure 14(a) shows the storage capacity characterized as a function of barrier voltage for single-packet storage (barrier-type II). The threshold voltage of storage was found to be - 6.2 V. More voltage than this is required to provide storage capacity. The storage capacity increases with barrier voltage up to - 7.6 V and decreases for more barrier voltage. The decrease was verified, by two different means, to be due to charge extraction. Charge loss was observed in the time domain and the entire frequency re- sponse dropped as predicted previously.

Figures 14(b) and 14(c) show the storage capacity as a function of barrier voltage for barrier-types III and V, respectively. The threshold voltage of storage was found to be between - 3.5 V to - 3.8 V for these barrier arrays. The storage capacity is found to be relatively constant with increasing storage voltage, once a threshold is reached. The deviations in storage capacity are well within experimental errors. Both barrier arrays appear to have the same storage capacity, which is slightly more than the delay-line capac- ity of N,, = 1.26 X lo7 cm - ‘.

The storage capacity of double-packet storage appears to be limited by the amount of charge a single wave crest can carry and not by intercell or surface diffusion as in the single-packet case. If intercell diffusion were a limiting fac- tor, then increasing the barrier voltage would dramatically reduce intercell diffusion resulting in increased storage ca- pacity, which is not observed. In addition, no extraction effects were observed in either the time domain or fre- quency domain.

In theory, for double-packet storage, no storage capac-

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FIG. 14. Measured storage capacity as a function of storage voltage for (a) single-packet storage barrier-type II, (b) double-packet storage barrier-type III and (c) double-packet storage barrier-type V.

ity is expected below the “zero charge” threshold voltage of storage, because the device is not in storage mode. Since the threshold voltage is partially a function of stored charge, slightly more voltage is required to store the delay- line charge capacity. The storage capacity for this storage voltage or greater is essentially limited by the delay-line capacity. In the transition region, the storage capacity is expected to increase sharply with storage voltage; however, it is not advisable to operate in this region.

VIII. DISCUSSION

The theoretical trends of single-packet storage with re- spect to barrier voltage are verified. At the threshold volt- age, no storage capacity exists. A larger barrier voltage is required to provide an intercell diffusion barrier. There- fore, increasing the barrier voltage in single-packet storage tends to increase the storage capacity. However, if the con- fining fields of the channel are not large enough, a barrier voltage will be obtained at which surface extraction effects take over. Once this voltage is reached, increasing the bar- rier voltage will decrease storage capacity. In theory, ex- traction effects can be eliminated by increasing the channel confinement with slightly higher doping densities.

In double-packet storage, the storage capacity appears to be limited primarily by the delay-line capacity and not by diffusion effects. The lowest frequency response rolloff for double-packet operation is predicted to occur when the

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carrier load per storage cell is equal to or less than the delay-line capacity of one wave crest and when only one input sample is stored in a cell. Input sampling for every wave crest (the normal mode of input sampling) will result in the observed 3 dB of rolloff at fs/4 as a result of the integration of two input samples into one storage sample.

Barrier transition times can be a severe limiting factor, if the device and barrier driver are not designed correctly. One device tested in this investigation had high internal barrier resistance creating a barrier risetime of 8.0 ns ( Ts = 2.8 ns). As a result, the device had very poor per- formance. Low internal barrier resistance RI and source resistance Rs should keep the transition time effects in check.

Single-packet storage offers twice the bandwidth of double-packet storage for the same SAW frequency. How- ever, for the same photolithographic constraints, the band- width differential may be less, because double-packet stor- age can utilize gratings with fewer electrodes per acoustic wavelength. Double-packet storage offers lower storage voltages for the same SAW power and higher storage ca- pacity per cell. In addition, double-packet storage appears to be more robust with respect to barrier timing than single-packet storage. A rolloff of 6 dB was the worst ob- served for double-packet storage when the barrier timing was deliberately skewed, whereas storage response can be obliterated for single-packet storage by errant barrier tim- ing. Furthermore, virtually no intercell diffusion occurs with double-packet storage, but there is intercell diffusion with single-packet storage. Intercell diffusion will reduce storage capacity for long storage times.

The marked differences between single-packet and double-packet storage are a result of the storage dynamics. When the wave potential is 180” out of phase with the barrier potential, as in the case of single-packet storage, the wave potential opposes the barrier potential in an attempt to push charge out of the cell. However, in double-packet storage, no matter what the wave potential phase, there is always at least one wave crest in which the charge can reside. It is for this reason that charge extraction by surface electrodes is far less likely for double-packet storage than for single-packet storage for the same device parameters. Double-packet storage could very well be the more natural mode of operation for charge storage ACT devices, for the wave and barriers act together to contain charge.

IX. CONCLUSIONS

The properties of single-packet and double-packet stor- age are investigated and compared. Double-packet storage is demonstrated for the first time and can provide higher storage capacity per cell than single-packet storage with less barrier voltage. For the same SAW frequency, how- ever, double-packet storage has half the bandwidth of single-packet storage. During the investigation, a method to obtain the frequency response of an ACT device in charge storage mode was developed, a task that had not been accomplished previously.

A 1-D storage model is developed that provides useful insight into the dynamics of charge storage in ACT devices

on GaAs. Optimal charge-transport depths for storage de- vices are also discussed, and it is found that the optimal transport depth for single-packet storage is shallower than that for double-packet storage.

The intrinsic effect of the charge storage process on the device frequency response is split into a storage response and a release response. The storage response can be elim- inated, in theory, by using only one input sample to form a storage sample. Likewise, the release response can be elim- inated by releasing only one charge packet.

Four factors are found to limit storage capacity: inter- cell diffusion, surface extraction, barrier transition times and ACT delay-line capacity. Surface extraction can be a significant limiting factor for single-packet storage if the doping density is too low to provide proper charge confine- ment. Surface extraction was not found to be a significant factor for double-packet storage. Intercell diffusion is a key limiting factor for single-packet storage but not for double- packet storage. The primary limiting factor for double packet storage is found to be the ACT delay-line charge capacity.

ACKNOWLEDGMENTS

The author warmly thanks Jim Peterson for his con- sultation regarding device fabrication. I would also like to thank my advisors Michael J. Hoskins and Bill Hunsinger for their inputs. The devices used in this investigation were manufactured by Electronic Decisions, Inc. The support of the Physical Electronics Affiliates Program of the Univer- sity of Illinois is greatly appreciated.

‘M. J. Hoskins, M. Morkoc, and B. J. Hunsinger, Appl. Phys. Lett. 41, 332 (1982).

2 M. J. Hoskins and B. J. Hunsinger, I986 IEEE Ultrasonics Symposium Proceedings (IEEE, New York, 1986). p. 439.

“W. J. Tanski, S. W. Merritt, R. N. Sacks, D. E. Cullen, E. J. Branci- forte, R. D. Carroll, and T. C. Eschrich, Appl. Phys. Lett. 52, 18 (1988).

4F. M. Fliegel, R. L. Martin, and F. Guediri, IEEE Trans. Microwave Theory Tech. MTT-35, 1164 (1987).

5F. M. Fliegel, Ph.D. dissertation, University of Illinois, 1987. ‘M. J. Hoskins, E. G. Bogus, and B. J. Hunsinger, IEEE Electron Dev.

Lett. EDL-4. 396 (1983). ‘M. J. Hoskins, H. L. Hsiung, and F. 0. Guediri, SPIE I989 Electronic

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Peterson, 1986 Frequency Control Symposium (IEEE, New York, 1986), p. 285.

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3344 J. Appt. Phys., Vol. 69, No. 5, 1 March 1991 B. Schmukler 3344

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