LAUNCHING GAAs WAFER FAB TECHNOLOGY INTO LSI

D.A. Nelson, C.J. Imboden, and B.M. Welch

Process StabilizationEstablishing a complete set of process specif-

ications is of paramount importance in establishinga stable process in a semiconductor fabricationfacility. No process can truly stabilize if 'theprocess "knobs" are being tweaked by good inten-tioned engineers, technicians, or operators. Thediscipline of following a fixed set of specs is asimportant in tracking down manufacturing problemsas it is in process repeatability. The good andbad points of any process can not be understood ormeasured if unknown or uncontrolled changes areoccurring throughout the FAB. This leads to theimportance of training FAB personnel. The oper-ators and technicians must read, understand, andinterpret the process specs in the same manner asthe engineers. This requires that the specs bereviewed on line with all involved, and in ad-dition, regular "audits" of the spec will en sur ethat nuances are not forgotten. The process specsalso provide information as to what constitutes aproperly functioning process. Statistical processcontrol charts are maintained by the operatorsproviding immediate feedback to production on thestatus of the process. Thus a flag can be raisedwhen the process is out of spec. Everyone involvedmust understand not only how to run a process, butalso when, how, and why a process module may bechanged. It is important to remember that changeis not impossible, but it must be documented andcontrolled. The final contributor to process sta-bilization discussed here is equipment/processrequalification. It is very important that a setof standard tests be established that are performedwhen process equipment stops performing a processproperly, following clean cycles, or followingmechanical repairs. The equipment is not consider-ed process ready or returned to production untilthese requalification tests are passed.' The excel-lent process stability that has been attained is adirect result of the detailed manufacturing speci-fications which control production procedures, therigid engineering change notice system which docu-ments and controls changes, and the statisticalprocess control methodology which informs and flagsengineering regarding process health.

GigaBit Logic, Inc.1908 Oak Terrace Lane, Newbury Park, CA 91320

ABSTRACT

As the manufacture of GaAs Integrated Circuitsmatures, it is important to underetiand zhe proceee,parametria, and yieZd requirements in moving f'rompredominantZy MSI to LSI cipuits. At GigaBit, withwafers processed approaching 25000 at peak punpates of 150 wafer starts per week, it has becomecl.ear that the main yieLd Limiting factor is theinteraction of the design with the basic deviceparameters ppoduced on the wafeps. We wiLL discussthe improvements which have been made at GigaBit inthe basic process, process stabiLity, and para-metric repeatabiLity areas since the manufacturingstatus was Last reported. 1,2 Puxrthe» improvementsin the process and circuit design technoLogies wiLLreeul.t: in the abiLity to design and manufactureproducts with 5000 to 10000 gates in the nearfuture.

INTRODUCTION

Whether the circuit technology is based onEnhancement/Depletion, all depletion, or some hy-brid of the two, the manufacturing requirements onthe FAB are really quite similar. In addition tomaintaining low levels of defects, the process mustbe stable, parametric yields must be high, andwafer loss due to breakage must be kept very low.In fact, process stability and parametric repeat-ability are of prime importance in manufacturingtechnology. In maintaining parametric repeatabili-ty, st rict cont rol of the incoming GaAs material,cap technology, implants, anneal, and ESD are veryimportant. In this paper, we discuss the improve-ments that have been made in manufacturing stabili-ty and parametric yield and how these improvementscan be measured. The overall effect on circuit ordie yield will be discussed as well as the futuredirections of manufacturing technology at GigaBitLogic.

MANUFACTURINGPROCESSSTABILITY

There are many areas and details that lead toa well founded manufacturing line, all of whichcannot be discussed in detail here. In this paper,the following areas will be addressed since thesewere key in moving GigaBit from an R & D pilot lineto a production line: Process Stabilization, WaferBreakage Reduction, ESD, and Defects and ProcessQuality. Obviously this is not a complete discus-sion of any of these areas but includes some of theideas and highlights of current work.

Wafer BreakageWafer breakage is a serious problem for any

GaAs FAB. This is where GaAs manufacturing tech-niques diverge from what is found in a siliconFAB. Processing and handling experience on thepart of the operators and technicians, while con-tributing to reducing breakage, can never totallyof itself bring breakage down to an acceptable

MAN TECH Conference - 77

level. Effective breakage reduction requires af-firmative action on all levels. Most cassette tocassette process equipment has been designed andbuilt with silicon wafers in mind. Software andmechanical adjustments must be made to slow downwafer movement and make the handling suitable tothe more "brittle" GaAs. Tweezers and dump trans-fers must be eliminated entirely and slide trans-fers reduced to the extent possible. Processes andequipment are considered down when even one waferis broken, not two in a row or more. All of thisrequi res that at tent ion is paid to the smalles tdetail. Equipment that only chips wafers must befound and fixed because today's chip is tomorrow'sdust. The overall results of such affirmativeaction wafer breakage reduction programs can be

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ESDThe manne r in which elect r o+s tatic discharge

(ESD) can affect a manufacturing process can besubtle and insidious. For years it was assumed atGigaBit that ESD was something that one needed tobe concerned about in regards to sawn die or pack-aged parts. No effects were ever correlated to

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levels of electro-static fields (ESF) in the FAB.In reality the effects were there but they were notproperly understood. The scope of the problem wasnot realized until a set of parallel metal lines onlevel 1 were placed on a chip close enough anddense enough with direct connections to peripheralbonding pads. The result was the sudden appearanceon wafers of arcs from line to line that actuallydelaminated the dielect ric between the lines. Itwas not until this problem was reproduced using anESD generator that the source of the problem wasrealized. Immediately, of course, steps were takento optimize the process to decrease the sensitivityto this failure mode. In addition, programs werebegun to measure ESF levels in process equipment,wafer staging areas, and in the FAB in general.Equipment was modified which exhibited high levelsof ESF. Conductive wafer cassettes and boxes wereobtained replacing all of the cassettes and boxesin production. Handling and storage practices werealtered to more ESD safe conditions.

Another effect of ESD was discovered after thewafer sensitivity to ESD and the'high levels of ESFwere established. A nagging bimodal dist ri butionof ideality factor for small diodes used as elec-trical parametric monitors on the wafers had beenexperienced for a long period of time. Diode ide-ality was either good «1.2) or bad (>1.8). Wafermaps did not reveal any pattern, with bad diodesshowing up surrounded by good diodes or viceversa. ESD measurements on diodes was very reveal-ing. When ESD voltages were applied in the forwarddirection, diodes remained functional with applied

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Fig.2 - Affect of Forward Bias ESD on Diodevoltages as high as 250 volts. Figure 2 showshowever that while t~e high current (160 ~A ) be-havior of these 2 I.Im area diodes was unchanged,their low current behavior altered markedly. Thecurve seen at zero volts, which has an ideality of1.147, did not alter until ESD voltages ~ 50 V were

applied. At 50 volts the apparent ideality shiftsto about 1.8. At much higher voltages the idea ofan ideality factor does not even apply. It isinteresting to note that in reverse bias ESD candestroy the diodes at 50 volts but shows no effectbelow this voltage. It should be noted that theESD effects described here are specific to theprocess and to the ultra small (typically 1 X 2um ) Schottky diodes with close ohmic to Schot tky

spacings. In all probability, results will varywith every process. It is clear, however, that asGaAs circuit densities increase, demanding smallerlinewidths, spacings, FETs, and diodes, the effectsof ESD must be incorporated into future designrules.

Defects and Process QualityQuality improvements in the FAB process do not

occur because of constant and vigilant wafer in-spection, but the causes of poor quality can onlybe identified through its diligent use. Visualinspection is a must at all process levels.Through routine inspections, an operator learnswhat a "good" wafer looks like and can be relied onto highlight the abnormal or poor quality wafe r ,When problems are found, it is important to havetimely feedback to prevent the problem occurring onmore wafers. Some key areas where inspection hasbeen extremely effective are the incoming GaAswafers, Schottky gate etching, Schottky and vialift-off, anneal, and alloy. Visual quality isvery subj ective and it is ext remely dif f icult toobtain good concrete measures of the overall pro-duction quality in the FAB. Establishing an indexof visual quality is important, however, if one isto measure progress in attempts to improve it. AtGigaBit, a quality index was established to monitorthe visual quality after the wafers had left theFAB. The inspection was carried out with a high

class 10). Figure 3 shows the improvements thathave been made in the monthly average of theindex. The results of the efforts in the FAB be-come visible to management, engineers, and mostimportantly to those performing the work. One un-avoidable side affect is that as the quality of thewafers improve, the inspectors tend to judge quali-ty more harshly such that over time the visualindex actually slides somewhat.

Another measure of quality is the density ofparticles deposited on the wafers during produc-tion. Using equipment readily available today, itis relatively simple to quantify the particulatelevel associated with any process step or piece ofequipment. It is important to set up a program ofmonitoring particles at each work station in theFAB and to establish "normal" particulate levelsfor t racking purposes and to discover which areasof the process are the "dirtiest" for correctiveaction. This type of program has been used toreduce the number of particle induced defects inthe process. One example at GigaBit is the ionmilling process. Ion mills are notoriously "dirty"because the material removed from the wafers isredeposited on the chamber walls in close proximityto the wafers. Particulate deposited on the wafersbefore or during the milling process can createdefects in the form of shorts because of the shad-owing of the metal mill process. Using a waferparticle mapping tool as the monitor, the processand equipment were modified reducing the particu-late from more than 1000 particles per 3 inch waferto less than 100.

PARAMETRICYIELD

As important as it is to maintain low levelsof defects in the FAB, it is perhaps more importantin a GaAs FAB to keep the wafer parametric yieldshigh. Here by parametric yield we mean the per-centage of wafers that fall within the design w~n-dow of device DC parameters. Thus, meeting theparametric window between wafers and lot to lot isimportant in addition to across wafer uniformity.In order to maintain parametric repeatability,strict qualification of the GaAs material, captechnology, implants, and anneal are very impor-tant. The material qualification procedures arenow identical to the standard IC process, ie. noshort cuts. Although most material will yield goodresults if the process is matched to it, only thatmaterial which falls inside a tight process windowis now accepted. Thus the process itself requireslittle or no tuning. The cap process has also beenimproved, enabling the use of a thinner cap. Last-ly, the old furnace anneal process has been sup-planted by a single wafer RTA using a lamp flashanneal system.

The improvements made in controlling the aboveprocesses this year have resulted in improvementsin the parametric yield on all fronts. Ohmic con-tacts, Schottky contacts, implanted resistors,diodes, and FETs all have more consistent values.In particular, the ability of the process to hit atargeted FET threshold has improved. Figure 4shows the improved capability of the 1987 processto produce a targeted Vp as compared with the 1986process. The ability to reproduce a given Vp is asimportant as uniformity in bringing enhancement

MAN TECHConference- 79

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FETs into the production environment. Overall theparametric yields have increased from 65% in 1986to 80% the first half of 1987. This improvement ismore dramatic in light of the fact that the para-metric acceptance range was approximately cut inhalf in January of this year.

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CIRCUIT YIELD

The great strides made in improving the manu-facturabi1ity of the GaAs process over the pastyear has resulted in dramatic improvement of wafersort yield. The family of logic parts manufactured

80 - MAN TECH Conference

with GigaBit's depletion mode process ranges insize from 6000 square mils to 12000 square mils.In 1986 the average wafer sort yield for all partson all wafers which were yielded out of FAB was

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Fig.5 (a) Best 1986 Wafer Sort Yields42%. In Figure 5 (a). the best wafer sort yieldfor different products is shown as a function ofthe Equivalent Linear Dimension of the Die (thesquare root of the Die area). The four dashedlines in the figure represent the gross functionalyield that would be expected given different defectlevels in the FAB by the Simple Murphy yieldmodel. 3 Using the Murphy model interpretation ofthis yield, it can be seen that the defect densi-ties in the FAB would fall in the 5 to 15 defectsper square centimeter range. It should be notedthat the wafer sort yield mapped for each productis the fully functional and not gross functionalyield of each circuit, ie. only the die which pass

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all functional and parametric specs are counted asyielded. This results in a pessimistic estimate ofthe level of defects in GigaBit's FAB. The im-provements detailed above have brought the averageyield of the same family of logic parts, includingnew designs to 56%. Figure 5 (b) shows the bestyields for 1987 compared to the Murphy curves asbefore. As can be seen in the figure, many of themore recently designed parts yield better for theirsize than the more mature parts. This is a directresult of the improved understanding of how todesign GaAs circuits that has matured at GigaBitthrough the design of some 30 parts over fouryears.

In addition to this extensive family of logicparts, GigaBit Logic has strong experience in theproduction of lK Static RAMs, having built approxi-mately 6,000 fully functional RAMs using severaldifferent designs. The newest RAMdesign has suc-cessfully passed all functional and parametricspecs with a cycle time of 2 ns over the tempera-ture range of 5 to 95 Centigrade. The RAMyieldshave varied greatly with design with the highestyielding lot at 37% yield and the highest yieldingwafer at 51% yield. At 150 mils on a side for thebest yielding design, the FAB would be rated at 5defects per square centimeter by the Murphy model.

SUMMARY

The average FAB line yield in 1987, to date is64% with more recent values hitting 75%. Lineyield includes all wafer breakage and all visual,process, or parametric rejects. When combined withan average sort yield of 52% (including RAMs) andan average Back-End yield of 70% (including allassembly yields, burn-in, and high speed testyields); we find a total end to end yield ofGigaBit Logic products of approximately 25%. Thismeans that 25% of all the circuits on all of the

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wafers run on GigaBit Logic's FAB line in 1987 havebeen yielded as fully functional end products. Thebest monthly end to end yield this year has reached29%. Yield, however, is not the only issue inmoving LS1 circuits into production. It is obviousthat as circuit size is increased power must bedecreased. This can only be accomplished if dis-crete device performance is improved so that ci r-cuit performance will not suffer. Figure 6 showsthe improvements that have been made in GigaBit'sstandard depletion process over the past 2fouryears. With typical FET K-values of 110 \JA/V +umand transconductances of 160. mS/rom at -1 voltpinch-off in production today, standard cell pro-ducts with up to 2000 gates have become possible.The top curve in Figure 6 shows the results pre-sently in R & D. With this device performance,GigaBit will soon bring E/D and other design tech-nologies into production which will have powerlevels commensurate with true LSI and VLSI parts.Currently a production 4K RAMand a standard cellfamily capable of up to 10000 gates are in design.

ACKNOWLEDGMENTS

The authors would like to thank all of themembers of the FAB, manufacturing, and design with-out whom none of this would have been possible.Additional thanks go to Cathy Hankins and LornaSmiley for preparing the manuscript.

REFERENCES

1. B.M. Welch, D.A. Nelson, and Y.D. Shen, "GaAsIntegrated Ci rcui t Manufacturing TechnologyComes of Age", Proc. IEEE 1986 Custom Inte-grated Circuits Conference, p. 67 (May 1986).B.M. Welch, "GaAs Digital Manufacturing Tech-nology: Methods, Status and FutureChallenges", Proc. Conference on GaAs Manu-facturing Technology, p. 27 (October 1986).B.T. Murphy, "Cost-Size Optima of MonolithicIntegrated Circuits", Pr oc , IEEE, vol. 51, pp ,1537-1545, Dec. 1964.

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MAN TECH Conference- 81