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Digital Design with Verilog HDL

Module, Data Types, Lexical Conventions,

Operators


Verilog: The Module


Module Header Format

module decoder_2_to_4 (A, D) ;input [1:0] A ;output [3:0] D ;

assign D = (A == 2'b00) ? 4'b0001 :(A == 2'b01) ? 4'b0010 :(A == 2'b10) ? 4'b0100 :(A == 2'b11) ? 4'b1000 ;

endmodule

module decoder_2_to_4 (input [1:0] A, output [3:0] D) ;assign D = (A == 2'b00) ? 4'b0001 :

(A == 2'b01) ? 4'b0010 :(A == 2'b10) ? 4'b0100 :(A == 2'b11) ? 4'b1000 ;

endmodule

Traditional

header format

Newer header format

- Verilog 2001 Style


Basic Modeling Structure

� Case-sensitive

� All keywords are lowercase

� Whitespace is used for readability

� Semicolon is the statement

terminator

� Single line comment: //

� Multi-line comment: /* */

� Timing specification is for

simulation


Verilog Module

module decoder_2_to_4 (A, D) ;

input [1:0] A ;output [3:0] D ;

assign D = (A == 2'b00) ? 4'b0001 :(A == 2'b01) ? 4'b0010 :(A == 2'b10) ? 4'b0100 :

4'b1000 ;endmodule

Decoder2-to-4

A[1:0]

D[3:0]

2

4

ports names of

module

module name

port types port sizes

module

contents

keywords underlined

� In Verilog, a circuit is a module.


Declaring A Module

� Can’t use keywords as module/port/signal names– Choose a descriptive module name

� Indicate the ports (connectivity)

� Declare the signals connected to the ports– Choose descriptive signal names

� Declare any internal signals

� Write the internals of the module (functionality)


Declaring Ports

� A signal is attached to every port

� Declare type of port– input

– output

– inout (bidirectional)

� Scalar (single bit) - don’t specify a size– input cin;

� Vector (multiple bits) - specify size using range– Range is MSB to LSB (left to right)– Don’t have to include zero if you don’t want to… (D[2:1])– output OUT [7:0];– input IN [0:4];


Physical Data Types

� Nets

� Vectors

� Registers

� Arrays


Physical Data Types

� Net data type

– Represent physical interconnect between processes (activity flows)

– Do not store value

� Register data type

– Represent a variable to store data temporarily

• it does not represent a physical (hardware) register


Name Keyword Default value Default size

net wire, supply0, supply1

z 1bit

wire net1;wire net2, net4;supply0 vss;

Physical Data Types: Nets

Example


Physical Data Types: Registers

Name Keyword Default value Default size

register reg x 1bit

reg register1;reg register2, register3;

Example


Physical Data Types: Vectors

� Wire or register which is more than 1 bit in size– Definition syntax

• <data type> [<start>:<end>] <identifer>

– Reference syntax

• <variable_name>{array_reference}

reg [3:0] output; // output is a 4-bit register

wire [31:0] data; // data is a 32-bit wire

reg [7:0] a;

data[3:0] = output; // partial assignment

output = 4'b0101; // assignment to the whole register

data[24]; // referencing to 24th bit

Example


Physical Data Types: Arrays

� Array– Definition syntax

• <data_type_spec> {size} <variable_name> {array_size}

– Reference syntax

• <variable_name> {array_reference} {bit_reference}

reg data [7:0]; // 8 1-bit data elements integer [3:0] out[31:0]; // 32 4-bit output elements out[27][3]; // referencing bit number 3

// in the 27th element

Example


Physical Data Types : Examples

� tri : represents a tri-state node (bus)

� Bus declarations :

– <data_type> [MSB : LSB] <signal name>;

– <data_type> [LSB : MSB] < signal name>;

� Examples:

– wire [15:0] Dataout;

– reg [7:0] Dataout;


Physical Data Types : Examples (2)

� Concatenate bits

– { } concatenates the bits separated by commas

– initial begin: int1

A=8`b01011010;

B={A[0:3] | A[4:7], 4`b0000}; // [<start-bit> : <end-bit>]

end

� Memory

– Two dimensional register array

– Can not be a net type

– Examples:

• reg [31:0] mem[0:1023]; // 1Kx32

reg [31:0] instr;

instr=mem[2];

– Double-indexing is not permitted (in Verilog-95)

• instr=mem[2][7:0] // Illegal


Parameter Types

� Parameters– Parameters are unsigned integer constants by default

– Must be assigned when declared. Width defaults are enough for the value assigned

– May be declared signed (but many tools reject it)

– May be declared real (but not synthesizable)

– May be typed by vector index range

– Declaration allowed anywhere in module, but local parameter proffered in body


Abstract Data Types

� For the convenience of the designer

– Do not have a corresponding hardware realization

– integer : signed variable (usually 32bit)

– time : unsigned integer (usually 64bit)

• used in conjunction with the $time function

– real : double precision floating point variable

– Array of integer and time variable (not reals) are allowed

– Multiple dimensional arrays are not allowed

– Example

• integer count;

• integer K[1:64];

• time start, stop;

– Parameter : assigning a value to symbolic name

• parameter size=8;

reg [size-1:0] a,b;


Lexical Conventions

� Comments

� Numbers

� Strings

� Identifier

� Operators


Lexical Conventions: Comments

Syntax

One line comment- //commentMultiple line comment- /*comment*/

Example

sum=a+b; // This is a one line comment

d[1]=1’b0; /* d[0]=1’b1; This is a multiple-line comment block */


Lexical Conventions: Identifiers

� Identifiers– Names given to objects

– Cannot start with a number or dollar sign ($)

– Can start with alphabetic character or underscore

wire a1; // wire is a keyword, a1 is an identifier

output sum; // output is a keyword, sum is an identifier


Lexical Conventions: Numbers

� Sized numbers <size>`<base format><number>– 5`b10111 // 5-bit binary number

– 16`hcdab // 16-bit hexadecimal number

– 3`d7 // 3-bit decimal number

� Unsized numbers– 16549 // 32-bit decimal number by default

– `o21 // 32-bit octal number


Lexical Conventions: Numbers (2)

� x or z values– x – unknown value

– z – high impedance value

– 16`h536x // This is a 16-bit hexadecimal value with 4 least significant bits unknown

� Negative numbers– Number with a minus sign before the size of a constant number

– -10`d9

� Underscore, Question mark– “_” character – anywhere in a number except the first character

• 16`b1010_0110_1101

– “?” question mark – substitutes z in numbers for better readability

• 8`b111?


Lexical Conventions: Numbers (3)The x and z values

� IN SIMULATION– Can detect x or z using special comparison operators

– x is useful to see:

• Uninitialized signals

• Conflicting drivers to a wire

• Undefined behavior

� IN REALITY– Cannot detect x or z

– No actual ‘x’ – electrically just isn’t 0, 1, or z

– Except for some uninitialized signals, x is bad!

• Multiple strong conflicting drivers => short circuit

• Weak signals => circuit can’t operate, unexpected results

– z means nothing driving signal (tri-state)


Lexical Conventions: Numbers (4)Resolving 4-Value Logic

A

B

OUT

A B OUT

0 0 0

0 1 1

1 1 1

0 x x

0 z x

1 x 1

1 z 1

A B OUT

0 0 0

0 1 0

1 1 1

0 x 0

0 z 0

1 x x

1 z x

A

B

OUT A

B

OUT

S A T B OUT

0 0 z z z

0 1 z x x

0 x z 1 1

0 z z 0 0

1 0 0 1 x

1 0 0 z 0

1 1 1 z 1

1 x x z x

1 z x 0 x

S

T

AOUT A

OUT0 1 x z1 0 x x


Lexical Conventions: Strings

� Strings – Any characters enclosed by double quotes

• “Verilog HDL Concepts”


Lexical Conventions: Operators

� Operators– Unary operators

• stand before the operand

– Binary operators

• stand between two operands

– Ternary operators

• have two separate operators that separate three operands


Operator Types

Operator Type Operator

Arithmetic operators *, /, +, -, %

Logical operators &&, ||, !

Relational operators >, <, >=, <=

Equality = =, !=, = = =, != =

Bitwise operators ~, &, |, ^, (~^, ^~)

Reduction Operator &, ~&, |, ~|, ^, ~^, ^~

Shift Operator >>, <<

Concatenation {, }

Replication c = {4{a}}

Conditional ?:


Operator Precedence

Operators Operator Symbols

Unary + - ! ~

Multiply, Divide, Modulus * / %

Add, Subtract + -

Shift << >>

Relational < <= > >=

Equality == != === !==

Reduction &, ~&^, ^~|, ~|

Logical &&||

Conditional ?:

Highest Precedence

Lowest Precedence


Arithmetic/Bitwise Operators


Reduction / Relational Operators


Equality / Logical / Shift Operators


Miscellaneous Operators


Basic Compiler Directives

� Syntax: `<keyword> Example:– `define MAX 16`b1111111111111111;

• The given 16-bit number will be substituted wherever `MAX appears

– `include integrator.v

• Includes the contents of Verilog source file in another Verilog file during compilation

– `timescale <reference time unit>/<time_precision>

• <reference time unit> specifies the unit of measurement for times and delays

• <time_precision> specifies the precision to which the delays are rounded off during simulation


Sequential Blocks

� Sequential Blocks– Statements in a sequential block are processed in the order they

are specified

– A statement is executed only after its preceding statement completes execution (except for non-blocking assignments)

– If delay or event control is specified it is relative to the simulation time, i.e. execution of the previous statement


Sequential Blocks

� The begin - end keywords:– Group several statements together.

– Cause the statements to be evaluated sequentially (one at a time)

• Any timing within the sequential groups is relative to the previous statement.

• Delays in the sequence accumulate (each delay is added to the previous delay)

• Block finishes after the last statement in the block

module sequential();

reg a;

initial begin

$monitor("%g a=%b", $time, a);

#10 a = 0;

#11 a = 1;

#12 a = 0;

#13 a = 1;

#14

$finish;

end

endmodule

0 a = x

10 a = 0

21 a = 1

33 a = 0

46 a = 1


Parallel Blocks

� Statements in a parallel block are executed concurrently

� Ordering of statements is controlled by the delay or event control assigned to each statement

� If delay or event control is specified, it is relative to the time the block was entered

� All statements in a parallel block start at the time when the block was entered– Thus, the order in which the statements are written in the block is

not important


Parallel Blocks (2)

� The fork - join keywords:– Group several statements together.

• Cause the statements to be evaluated in parallel (all at the same time).

• Timing within parallel group is absolute to the beginning of the group.

• Block finishes after the last statement completes (Statement with highest delay, it can be the first statement in the block)

module parallel();

reg a;

initial fork

$monitor ("%g a = %b", $time, a);

#10 a = 0;

#11 a = 1;

#12 a = 0;

#13 a = 1;

#14

$finish;

join

endmodule

0 a = x

10 a = 0

11 a = 1

12 a = 0

13 a = 1

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Digital Design with Verilog HDL - Multimedia …viscom.kau.ac.kr/wordpress/wp-content/uploads/2017/08/... · Digital Design with Verilog HDL Module, Data Types, Lexical Conventions,