Design of A Novel High Speed Dynamic Comparator with Low ... · Abstract- A new CMOS dynamic comparator using dual input single ... Back to-back inverter in the ... the transient

International Journal of Electronics and Computer Science Engineering 411

Available Online at www.ijecse.org ISSN- 2277-1956

ISSN:2277-1956/V2N1-411-426

Design of A Novel High Speed Dynamic Comparator with Low Power Dissipation for High Speed ADCs

Sougata Ghosh 1 ,Samraat Sharma 2

1 Department of Electronics and Communication Engineering 1 Assistant Professor, IFTM University, Moradabad, Uttarpradesh-244102

2 Department of Electrical Engineering 2 Assistant Professor, IFTM University, Moradabad, Uttarpradesh-244102

Email- [email protected] , [email protected] Abstract- A new CMOS dynamic comparator using dual input single output differential amplifier as latch stage suitable for high speed analog-to-digital converters with High Speed, low power dissipation and immune to noise than the previous reported work is proposed. Back to-back inverter in the latch stage is replaced with dual-input single output differential amplifier. This topology completely removes the noise that is present in the input. The structure shows lower power dissipation and higher speed than the conventional comparators. The circuit is simulated with 1V DC supply voltage and 250 MHz clock frequency. The proposed topology is based on two cross coupled differential pairs positive feedback and switchable current sources, has a lower power dissipation, higher speed, less area, and it is shown to be very robust against transistor mismatch, noise immunity. Previous reported comparators are designed and simulated their DC response and Transient response in Cadence®Virtuoso Analog Design Environment using GPDK 90nm technology. Layouts of the proposed comparator have been done in Cadence® Virtuoso Layout XL Design Environment. DRC and LVS has been checked and compared with the corresponding circuits and RC extracted diagram has been generated. After that post layout simulation with 1V supply voltage has been done and compared the speed, power dissipation, Area, delay with the results before layout and the superior features of the proposed comparator are established. Keywords – CMOS comparator, low power, High Speed, Analog-to-Digital Converter and Cadence

1. INTRODUCTION

Comparators are most probably second most widely used electronic components after operational amplifiers in this world. Comparators are known as 1-bit analog-to digital converter and for that reason they are mostly used in large abundance in A/D converter. In the analog-to-digital conversion process, it is necessary to first sample the input. This sampled signal is then applied to a combination of comparators to determine the digital equivalent of the analog signal [16]. The conversion speed of comparator is limited by the decision making response time of the comparator. As the comparator is one which limits the speed of the converter, its optimization is of utmost importance. In today’s world, where demand for portable battery operated devices is increasing, a major thrust is given towards low power methodologies for high speed applications. This reduction in power can be achieved by moving towards smaller feature size processes. However, as we move towards smaller feature size processes, the process variations and other non-idealities will greatly affect the overall performance of the device. One such application where low power dissipation, low noise ,high speed, less hysteresis, less Offset voltage are required is Analog to Digital converters for mobile and portable devices. The performance limiting blocks in such ADCs are typically inter-stage gain amplifiers and comparators. The accuracy of such comparators, which is defined by its offset, along with power consumption, speed is of keen interest in achieving overall higher performance of ADCs. In the past, pre-amplifier based comparators [1] have been used for ADC architectures such as flash and pipeline. The main drawback of pre-amplifier based comparators is the more offset voltage. To overcome this problem, dynamic comparators are often used that make a comparison once every clock period and require much less offset voltage. However, these dynamic comparators suffer from large power dissipation compared to pre-amplifier based comparators. The main problem with all these dynamic comparators is the output signal of the latch stage is fluctuating during clock transition. This is happening due to the presence of noise in input terminals. In this paper we have designed all type of comparators

412 Design of A Novel High Speed Dynamic Comparator with Low Power Dissipation for High Speed ADCs

ISSN: 2277-1956/V2N1-411-426

and proposed a circuit which removes the noise from the output and dissipates less power and provides high speed. Keeping these things in mind we have designed a new differential amplifier based comparator.

2. ANALYSIS OF DIFFERENT TYPE OF COMPARATORS:

Table 1: INPUT SPECIFICATIONS

SUPPLY VOLTAGE (VDD) 1V

TECHNOLOGY CADENCE GPDK 90 nm

INPUT VOLTAGE RANGE 0V‐0.9V

CLOCK FREQUENCY 250 KHz

CLOCK RISE TIME 100 ps

CLOCK FALL TIME 100 ps

CLOCK DELAY 1 ns

CLOCK PULSE WIDTH

2 ns

TEMPARATURE 27 ◦C

REFERENCE VOLTAGE 0.2V‐0.7V

Table 2:TRANSISTOR DIMENSIONS(µm)

(In above table for Preamplifier Based Comparator[1],

Latch Type Voltage Sense Amplifier[2] Double Tail Latch Type Voltage SA[3]

Dynamic Comparator without Calibration [4] Double Tail Dual Rail Dynamic Latched Comp.[5])

IJECSE, Volume2, Number 1 Sougata Ghosh and Samraat Sharma

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2.1 PREAMPLIFIER BASED COMPARATOR:

2.1.1 CIRCUIT DIAGRAM: Figure 4.1 shows the schematic (designed in Cadence) of the Preamplifier based comparator circuit. The supply voltage of this comparator is 1 V. Input voltage is .9 V and Reference voltage is .5 V. The temperature is 27◦C. The input specifications are specified in detail in Table 1.

Fig:1 Preamplifier Based Comparator.

2.1.2 DC ANALYSIS: Figure 2. shows the DC analysis of the preamplifier based comparator. For calculating DC analysis, both input and reference voltage is taken as the DC voltage source. DC analysis states that the above comparator works perfectly. Back-to-back NMOS transistors in preamplifier stage keep the PMOS transistors in the preamplifier from turning off.

Figure 2. DC Response of the preamplifier based comparator.

2.1.3 TRANSIENT ANALYSIS: Figure 3. shows the Transient response of the above circuit. For calculating transient response a PULSE voltage source is used as input voltage source and reference voltage source is a DC voltage source.


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Figure 3. Transient response of the circuit.

2.1.4 RESULTS: Offset Voltage: 64.35 mV Static Power Dissipation: 10.89 µW Dynamic Power Dissipation: 72.56 µW Delay: 0.3935 nS Speed: 2.54 GHz Slew Rate: 21.23 V/nS

2.2 LATCH TYPE VOLTAGE SENSE AMPLIFIER: 2.2.1 CIRCUIT DIAGRAM: Figure 4. shows the Circuit Diagram (designed in Cadence) of Latch type voltage sense amplifier. Specifications are given in Table 1. Transistor sizes are specified in Table 2. The circuit comprises of a latch stage followed by buffer stage (which is nothing but a self biased differential amplifier followed by an inverter).

Figure 4. Circuit Diagram of Latch Type Voltage Sense Amplifier.

2.2.2 DC ANALYSIS: Figure 5. shows the DC analysis of the circuit. From Figure 4.5, we can say that the comparator is working fine. Input voltage is swept from -1V to +1V and reference voltage is taken as .2 V.


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Figure 5. DC analysis of the circuit.

2.2.3 TRANSIENT ANALYSIS: Figure 6. shows the transient response of the circuit. From transient response we can conclude that output of outp( as well as outn node) node which acts as an one of the input of the output buffer stage (which is mainly comprises of a self-biased differential amplifier followed by an inverter) is distorted by the noise present in the comparator.

Figure 6. Transient response of the circuit


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2.2.4 RESULTS: Before Layout Simulation: Offset Voltage: 339.6 mV Dynamic Power Dissipation: 14.84 Μw Delay: 1.247 nS Speed: .802 GHz Slew Rate: 11.08 V/nS

After Post Layout Simulation: Dynamic Power Dissipation: 16 µW Delay: 1.35 nS Speed: .735 GHz Slew Rate: 18.27 V/nS

2.3 DOUBLE TAIL LATCH TYPE VOLTAGE SENSE AMPLIFIER:

2.3.1 CIRCUIT DIAGRAM:

Figure 7. Circuit Diagram of Double Tail Latch Type Voltage Sense Amplifier.

4.3.2 DC ANALYSIS: Figure 8. shows the DC Analysis graph of the circuit. Input voltage is taken as 1 V and swept from -1V to +1V. Reference Voltage is taken as .2V. From the graph we can conclude that the comparator is working fine.

Figure 8.


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4.3.3 TRANSIENT ANALYSIS: Figure 9. shows the transient analysis of the circuit. From this analysis we can say that the output of out+ node in latch stage is affected by noise and fluctuating with the clock transition as that was in the previous comparator. For the transient analysis we have taken pulse voltage source as Input stage and a dc voltage source as reference node.

Figure 9. Transient Analysis of the comparator.

2.3.4 Results: Before Layout Simulation: Offset Voltage: 259.8 mV

Dynamic Power Dissipation: 127.9 µW Delay: 1.745 nS Speed: .573 GHz

Slew Rate: 39.85 V/nS

After Post Layout Simulation: Dynamic Power Dissipation: 145.07 µW

Delay: 2.52 nS Speed: .390 GHz

Slew Rate: 2.16 V/nS

2.4 DYNAMIC COMPARATOR WITHOUT CALIBRATION: 2.4.1 CIRCUIT DIAGRAM: Figure 10. shows the Dynamic Comparator without Calibration (Designed in Cadence).This figure also consists of a latch followed by a output buffer stage. Specifications are given in Table 1. Transistor sizes are specified in Table 2.


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Figure 10. Dynamic Comparator without Calibration.

2.4.2 DC ANALYSIS:

Figure 11. DC Analysis of Comparator.

Figure 11. shows the DC response of the circuit. Input voltage is taken as 1 V and swept from -1V to +1V. Reference Voltage is taken as .4V. From the graph we can conclude that the comparator is working fine. 2.4.3 TRANSIENT ANALYSIS: Figure 12. shows the transient analysis of the circuit. From this analysis we can say that the output of out+ node in latch stage is affected by noise and fluctuating with the clock transition as that was in the previous comparator. For the transient analysis we have taken pulse voltage source as Input stage and a dc voltage source as reference node.


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Figure 12. Transient Response of Comparator. 2.4.4 RESULTS: Before Layout Simulation: Offset Voltage: 300.1 mV Dynamic Power Dissipation: 105.33 µW Delay: .61 nS Speed: 1.639 GHz Slew Rate: 3.09 V/nS


2.5 DOUBLE-TAIL DUAL-RAIL DYNAMIC LATCHED COMPARATOR: 2.5.1 CIRCUIT DIAGRAM: Figure 13. shows the schematic diagram of the Dynamic Comparator without Calibration (designed in Cadence). This circuit also comprises of latch stage followed by buffer stage. Specifications are given in Table 1. Transistor sizes are specified in Table 2. Figure 4.13 Schematic Diagram of Double-Tail Dual-Rail Dynamic Latched Comparator.


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Figure 13. Schematic Diagram of Double-Tail Dual-Rail Dynamic Latched Comparator.

2.5.2 DC CHARACTERISTICS:

Figure 14. DC Characteristics of the Comparator

Figure 14. shows the DC response of the circuit. Input voltage is taken as 1V and swept from -1V to +1V. Reference Voltage is taken as .4V. From the graph we can conclude that the comparator is working fine. 2.5.3 TRANSIENT ANALYSIS: Figure 15. shows the transient analysis of the circuit. From this analysis we can say that the output of out+ node in latch stage is affected by noise and fluctuating with the clock transition as that was in the previous comparator. For the transient analysis we have taken pulse voltage source as Input stage and a dc voltage source as reference node.


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Figure 15. Transient Response of Double-Tail Dual-Rail Dynamic Latched Comparator.

2.5.4 RESULTS: Before Layout Simulation Dynamic Power Dissipation: 57.37 µW Delay: 1.49 nS Speed: .671 GHz Slew Rate: 10.77 V/Ns


3. PROPOSED COMPARATOR:

Circuit Diagram of Proposed Comparator is shown in Figure 16. This circuit mainly is a derived version of the [5]. The back-to-back latch stage is replaced with back-to-back dual input single output differential amplifier. Differential amplifier has so many advantages over the conventional latch which nothing but an inverter. It has higher immunity to environmental noise and it rejects common mode noise or in other words it has better CMRR. Another property of differential signaling is the increase in maximum achievable voltage swings. It also provides simpler biasing and higher linearity. Here our main purpose is to eliminate the noise that is present in the latch stage and for which output is getting fluctuated with clock transition.


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3.1 CIRCUIT DIAGRAM OF PROPOSED COMPARATOR:

Figure 16. Schematic of the proposed comparator. The circuit diagram drawn in Cadence® Virtuoso Analog Design Environment is shown in Figure 16. Figure 17. shows the DC response of the circuit.

Figure 17. DC response of the Proposed Comparator.


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Figure 18. Transient Response.

Figure 18. shows the transient response of the circuit. Input specifications are mentioned in Table 1. Table 2 shows the sizes of the transistors. From transient response it is evident that the output of the buffer stage and the output of the out+ node are almost equal which was not seen in the previous comparators either.

4. RESULTS & DISCUSSIONS:

To compare the performance of the proposed comparators with previous works, each circuit was simulated in Cadence® virtuoso analog design environment. Technology used is gpdk 90nm technology with VDD=1V as supply voltage. The layout diagrams and RC extracted diagrams has been given in fig. Table 3 shows the result summary before post layout simulation. Table 4 shows the result summary after post layout simulation. From table 5 we can say that though proposed comparator have highest transistor count but it still consumes less power than [2], [3], [4], [5]. We can also say that from Table 3, the speed is improved with respect to [5]. from Table 4, we can say that the power dissipation of proposed comparator, after post layout simulation is increased by 31% but it is still less than [5]. After post layout simulation the speed of proposed comparator is decreased from 0.910 GHz to 0.485 GHz but is still better than that of [5].


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Table 3: Result summary before layout:

COMPARATORS Transistor Count

Offset Voltage (mV)

Power Dissipation (µW)

Delay (nS)

Speed (GHz)

Slew Rate (V/nS)

Preamplifier Based Comparator[1]

22 64.35 83.45 0.393 2.54 21.23

Latch Type Voltage Sense Amplifier [2]

19 339.6 14.84 1.247 0.802 11.08

Double Tail Latch Type Voltage SA[3]

22 259.8 127.9 1.745 0.573 39.85

Dynamic Comparator without Calibration [4]

23 300.1 105.33 0.61 1.639 3.09

Double Tail Dual Rail Dynamic Latched Comp.[5]

27 300 57.37 1.49 0.671 10.77

Table 4: Result summary after post layout simulation:

COMPARATORS Area(µm2) Power

Dissipation (µW)

Delay (nS)

Speed (GHz)

Slew Rate (V/nS)

Latch Type Voltage Sense Amplifier [2]

349.08 16 1.35 0.735 18.27

Double Tail Latch Type Voltage SA[3]

86.24 145.07 2.52 0.390 2.16

Dynamic Comparator without Calibration [4]

124.23 110 1.95 0.510 16.37

Double Tail Dual Rail Dynamic Latched Comp.[5]

110.24 65 2.15 0.460 11.07


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5. LAYOUT OF PROPOSED COMPARATOR:

6. RC EXTRACTED


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References

[1] T. Kobayashi, K. Nogami, T. Shirotori and Y. Fujimoto, “A current-controlled latch sense amplifier and a static power-saving input buffer for low-power architecture,” IEEE J. Solid-State Circuits, vol. 28, pp. 523-52, April 1993.

[2] B. Wicht, T. Nirschl, and D. Schmitt-Landsiedel, “Yield and speed optimization of a latch-type voltage sense amplifier”, IEEE J. Solid-State Circuits, vol. 39, pp. 1148-1158, July 2004.

[3] D. Schinkel, E. Mensink, E. Kiumperink, E. van Tuijl and B. Nauta, “A Double- Tail Latch-Type Voltage Sense Amplifier with 18ps Setup+Hold Time,” ISSCC Dig. Tech. Papers, pp. 314-315 and 605, Feb. 2007.

[4] M. Miyahara, Y. Asada, P. Daehwa and A. Matsuzawa, “A Low-Noise Self-Calibrating Dynamic Comparator for High-Speed ADCs,” in Proc. A-SSCC, pp.269-272, Nov. 2008.

[5] H.J. Jeon, Y.B. Kim, “A Low-offset High-speed Double-tail Dual-rail Dynamic Latched Comparator,” ACM GLSVLSI’10(Great Lakes Symposium on VLSI), May 16-18, 2010

[6] Philip E. Allen and Douglas R. Holberg, CMOS Analog Circuit Design, 2nd ed.,Oxford Indian Edition, 2006.

[7] Jun He, Sanyi Zhan, Degang Chen, and R.L. Geiger, “Analyses of Static and Dynamic Random Offset Voltages in Dynamic Comparators,” IEEE Trans. Circuits Syst. I: Reg. Papers, vol. 56, pp. 911-919, May 2009.

[8] Nikoozadeh and B. Murmann, “An Analysis of Latch Comparator Offset Due to Load Capacitor Mismatch,” IEEE Trans. Circuits Syst. II: Exp. Briefs, vol. 53, no.12, pp. 1398-1402, Dec. 2006

[9] Pedro M.Figueiredo, Joao C.Vital, “Kickback Noise Reduction Techniques for CMOS Latched Comparator”, IEEE Transactions on Circuits and Systems, vol.53, no.7, pp.541-545, July 2006.

[10] B. Murmann et al., "Impact of scaling on analog performance and associated modeling needs," IEEE Trans. Electron Devices, vol. 53, no. 9, pp. 2160-2167, Sep. 2006.

[11] R. Jacob Baker, Harry W. Li, David E. Boyce, “CMOS- Circuit Design, Layout, And Simulation”, IEEE Press Series on Microelectronic Systems, IEEE Press, Prentice Hall of India Private Limited, Eastern Economy Edition,2002

[12] Meena Panchore, R.S. Gamad, “Low Power High Speed CMOS Comparator Design Using .18µm Technology”, International Journal of Electronic Engineering Research, Vol.2, No.1, pp.71-77, 2010.

[13] M. van Elzakker, A.J.M. van Tuijl, P.F.J. Geraedts, D. Schinkel, E.A.M. Klumperink and B. Nauta, "A 1.9W 4.4fJ/Conversion-step 10b 1MS/s Charge-Redistribution ADC," ISSCC Dig. Tech. Papers, pp. 244–245, February 2008.

[14] S. Kale and R. S. Gamad, “Design of a CMOS Comparator for Low Power and High Speed” , Internationl Journal of Electronic Engineering Research, vol. 2, no. 1, pp. 29-34, 2010.

[15] Heungjun Jeon and Yong-Bin Kim, “A Novel Low-Power, Low-Offset and High-Speed CMOS Dynamic Latched Comparator”, IEEE, 2010.

[16] Razavi Behzad, “Design of Analog CMOS Integrated Circuits”, New York, NY: McGraw-Hill, Inc., 2000

[17] Sansen Willy M.C., Analog Design Essentials”, Neatherlands, Springer International Edition, 2006.

[18] Dutta Ramen, “CMOS Voltage Comparator”,Advanced VLSI Design Lab, IIT Kharagpur.[Online].Available:conf05.iitkgp.ac.in/avlsi/logf/summercourse/2008/c omparator.pdf [Accessed: 14 March, 2011].

[19] Allen Phillip E., Short Course Notes on CMOS Analog IC Design. [Online]. Available: http://www.aicdesign.org/scnotes10.html [Accessed: February 12, 2011].

[20] Allen Phillip E., “Lecture-360- Characterization of Comparator”. [Online]. Available:users.ece.gatech.edu/pallen/.../L360-Char_Comparators-2UP.pdf [Accessed 20 February, 2011].

[21] Johns D., Martin K., Analog Integrated Circuit Design, Wiley India Pvt. Ltd., 2008

[22] Cadence Online Documentation. Avilable: http://www.cadence.com

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Design of A Novel High Speed Dynamic Comparator with Low ... · Abstract- A new CMOS dynamic comparator using dual input single ... Back to-back inverter in the ... the transient