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1
A Low-Noise Self-Calibrating Dynamic Comparator for
High-Speed ADCs
Masaya Miyahara, Yusuke Asada, Daehwa Paik and Akira Matsuzawa
Tokyo Institute of Technology, Japan
2Outline
• Motivation• The Calibration Scheme• Proposed Comparator• Measurement Results• Conclusions
3Motivation (I)Comparator performance is important in comparator based ADCs.
-VFS
+VFSVin
Thermom
eter
Binary
2N N bit
Comparators
Comparator offset ⇒Low linearity⇒Low SNDR
Comparator noise⇒Low SNR
4Motivation (II)10bit SAR ADC6bit Flash ADC
1bit down @Vn(σ) = 1/2 LSB1bit down @Voffset(σ) = 1/4 LSB
ENO
B [b
it]
ENO
B [b
it]
5Comparator Design Challenges•Sensitivity •Speed & Power•Offset Voltage
Vin
Vout
・Transistor mismatch・Parasitic capacitance
・Transistor Noise
CLK
V+
V-Vin
P(high) Vout
Threshold
+σ−σVoffset ttd
・Circuit topology・Transistor size
6Outline
• Motivation• The Calibration Scheme• Proposed Comparator• Measurement Results• Conclusions
7Design ConceptPre-amplifiers are used to reduce to offset voltage.However…
•High DC gain (> 10x)=> Difficult in deep
sub-micron CMOS
•Wide bandwidth (> 1 GHz)=> Large power
consumption
Offset calibration techniques are more suitable in deep sub-micron CMOS design.
8Conventional Offset Calibration
ds
LCI
V∆∆
∝offset[2] G. Van del Plas et al. ISSCC 2006
Advantage: Dynamic circuit, no static power.Drawbacks: Accuracy is limited by the resolution of Ccal.
Latch speed is slowed down.
9Proposed Offset Calibration
Advantages: During the conversion mode, no static power.Wide compensation range.The resolution is variable by changing Icp.
Drawback: Charge pump circuit must refresh CH frequently.
ds
LCI
V∆∆
∝offset
Mc1
Mc2
In
In
Vb
Vcm
Vcm
Vin
VC
Vout
H
Icp
Icp
VoutVin
CAL
CAL
CAL
CAL
CALCAL
Voffset
10Outline
• Motivation• The Calibration Scheme• Proposed Comparator• Measurement Results• Conclusions
11Double-Tail Latched Comparator
CLK
Di+ Di-
VDD
Vout+
CLK
VDDCLK VDD
Vin+Vin-
Vout-
Di+Di-
Vout+
Vout-
CLK
0.0
1.0-0.1
1.0
-0.1
1.0
1.8n 2.1n 2.4n 2.7n 3.1nTime [s]
td:50-100ps
CLK
The 2nd latch stage has to detect ∆VDi in a very short time.
[4]D. Schinkel et al. ISSCC 2007
12Proposed Comparator
CLK
CLK
Di+ Di-
Xi+ Xi-
VDD VDD
VDD VDD
Vout-Vout+
Vin- Vin+
Di+Di-
Vout+
Vout-
CLK
0.0
1.0-0.1
1.0
-0.1
1.0
1.8n 2.1n 2.4n 2.7n 3.1nTime [s]
td:50-100ps
Proposed comparator uses Di nodes voltage instead ofCLK for 2nd stage latch timing.
13Proposed Comparator AdvantagesVDD VDD
VDD VDD
VoutVout
Vin Vin
•Less clock driving
•High 2nd latch Gm (~2x)=> less noise from 2nd latch
•Wide area input transistor=> less offset from 2nd latch
•Unaffected by clock skew
14Proposed Comparator with Calibration
•All transistor channel length is minimized.
•Each transistor channel width is optimized for fast latching.
ICP
ICP
Vb H
VDD VDD
VDD VDD
Vout
Vout
VoutVout
Vin Vin
15Comparison : Offset Voltage90 nm CMOS, 100 times Monte Carlo simulations.Same size transistors are used in each comparators.
ConventionalVoffset(σ) = 21.5 mV
Voffset
Proposed (CAL OFF)Voffset(σ) = 13.5 mV
Proposed (CAL ON)Voffset(σ) = 1.3 mV
Offset voltage 1/16
16Comparison : Noise
V n
_
P
Vin Voffset
Vn
Vn
VDD = 1.0 V, Fc = 4 GHz, Transient-Noise simulations.(Offset calibration is not used.)
@Vcm = 0.6 V
1/3
17Outline
• Motivation• The Calibration Scheme• Proposed Comparator• Measurement Results• Conclusions
18LayoutA prototype comparator has been realized in a 90 nm 10M1P CMOS technology with a chip area of 0.0348mm2
0.29 mm
0.12
mm
64 comparators with SR Latch
0.29 mm
0.12
mm
0.29 mm
0.12
mm
64 comparators with SR Latch
0.29 mm
0.12
mm
64 comparators with SR latch.
19Measurement System
Without CAL
Vcm
Vin+
Vin-
Voffset
VoutRamp wave,Fin = 1MHz
CALCLKWith CAL
Vout
Vin+
Vin- Vout
Ran
dom
CAL CAL
20Measurement Results : Offset
Voffset
Voffset
VDD=1.0 V, FC = 250 MHz, N=64
21Measurement Results : NoiseVDD=1.0 V, Offset Calibration is not used.
FC
FC
Vcm
22Performance Summary
Technology 90nm, 1poly, 10metals CMOSActive Area 120µm x 290µm (64 comparators)Voffset(σ) CAL OFF/ON 13.7mV / 1.69mV
Supply Voltage 1.0VInput eq. noise Vn(σ) 0.7mV @ Fc=600MHz, Vcm=0.5V
Power consumption 40 µW/GHz ( 20 fJ/conv.)
23Outline
• Motivation• The Calibration Scheme• Proposed Comparator• Measurement Results• Conclusions
24Conclusion
A low offset voltage, low noise dynamic latched comparator using a self-calibrating technique is proposed.
☺Features•The new calibration technique does not require any amplifiers for the offset voltage cancellation and quiescent current. •It achieves low offset voltage of 1.69 mV at 1 sigma, while 13.7 mV is measured without calibration. •A low input noise of 0.6 mV at 1 sigma, three times lower than the conventional one.
