Design and Validation of Two Single Event Latch-up ...Design and Validation of Two Single Event Latch-up Protection Solutions Comparing a New Single Event Latch-up Test Circuit with

Design and Validation of TwoSingle Event Latch-up Protection

Solutions

Comparing a New Single Event Latch-upTest Circuit with the IDEAS IDE3466

Single Event Latch-up Detection Module

Jonas Birkeland Carlsen

Thesis submitted for the degree ofMaster in Electronics and Computer Technology

60 credits

Department of PhysicsFaculty of mathematics and natural sciences

UNIVERSITY OF OSLO

Spring 2018

Design and Validation of Two SingleEvent Latch-up Protection Solutions

Comparing a New Single Event Latch-up TestCircuit with the IDEAS IDE3466 Single Event

Latch-up Detection Module

Jonas Birkeland Carlsen

© 2018 Jonas Birkeland Carlsen

Design and Validation of Two Single Event Latch-up Protection Solutions

http://www.duo.uio.no/

Printed: Reprosentralen, University of Oslo

http://www.duo.uio.no/

Abstract

The focus of this thesis is single event effects in electronic circuits, and mainly single eventlatch-up. Various solutions for protecting against single event latch-up are discussed. On-sitesingle event latch-up protection is becoming more relevant as more projects utilise low-costcomponents, potentially sensitive to radiation. Two circuits for such protection are verifiedand validated. Comparing these two solutions illuminate the diversity of on-site single eventlatch-up protection. The first of the circuits was developed for single event effects testingof electronic circuits. The circuit-board implements the functions required for an on-sitelatch-up protection, and was validated in both heavy ion and laser radiation hardness assur-ance tests. The test campaigns helped identify parameters relevant to single event latch-updetection and protection. The second solution explored was an integrated circuit developedby Integrated Detector Electronics AS. This circuit, the IDE3466, is implemented with aradiation-hardened design, and represents a safer, proprietary, but also more costly solutionfor on-site single event latch-up protection. The circuit was verified in the laboratory, as wellas programmed for an experimental use case expanding its functionality beyond its intendedapplication to include current sampling. The prospect of offering such a circuit commerciallyis also discussed by examining test results and the present commercial market.

Acknowledgements

I would like to direct my gratitude to Ketil Røed, Timo A. Stein and Dirk Meier, for theirsupervision and help along the way. Introducingme to this newworld within electronics hasgiven me so much. A big thanks goes to the people at IDEAS for their assistance in the workwith the IDE3466 ASIC. I would also like to thank Sohail Mahmood for the cooperationduring our two radiation test campaigns. Last but not least, I must thank my dearest Rikkefor her patience.

i

Contents

I Introduction 1

1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Goal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Thesis Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

II Theoretical Background 3

1 Radiation Effects in Electronic Circuits . . . . . . . . . . . . . . . . . . . 31.1 Cumulative Effects . . . . . . . . . . . . . . . . . . . . . . . . . 31.2 Single Event Effects . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Particle Radiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42.1 Energy Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42.2 Heavy Charged Particles . . . . . . . . . . . . . . . . . . . . . . 42.3 Neutrons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

3 Radiation Environments . . . . . . . . . . . . . . . . . . . . . . . . . . 53.1 Atmospheric & Terrestrial Environments . . . . . . . . . . . . . 53.2 The Space Environment . . . . . . . . . . . . . . . . . . . . . . 6

4 Stopping Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94.1 Linear Energy Transfer . . . . . . . . . . . . . . . . . . . . . . . 104.2 Modelling Tools . . . . . . . . . . . . . . . . . . . . . . . . . . 10

5 From Irradiation to Single Event Latch-up . . . . . . . . . . . . . . . . . 115.1 Neutrons and Protons Triggering Latch-up . . . . . . . . . . . . 115.2 Single Event Latch-up Formation . . . . . . . . . . . . . . . . . . 125.3 Thyristor Operation . . . . . . . . . . . . . . . . . . . . . . . . 135.4 Micro Latch-ups . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6 Countermeasures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146.1 Process Level Latch-up Countermeasures . . . . . . . . . . . . . . 156.2 Layout Level Latch-up Countermeasures . . . . . . . . . . . . . . 176.3 System Level Latch-up Countermeasures . . . . . . . . . . . . . . 176.4 Temperature and Supply Voltage . . . . . . . . . . . . . . . . . . 186.5 Remarks on other Radiation Effects . . . . . . . . . . . . . . . . 19

7 Radiation Hardness Assurance Testing of Electronic Components . . . . . 197.1 Single Event Latch-upMonitoring . . . . . . . . . . . . . . . . . 197.2 Cross Section Calculation . . . . . . . . . . . . . . . . . . . . . . 207.3 LET as a Function of Incident Angle . . . . . . . . . . . . . . . . 207.4 Calculating Expected Events in an Environment . . . . . . . . . . 217.5 Laser Radiation Testing as an Alternative Method . . . . . . . . . 217.6 Latent Damage to Irradiated Circuits . . . . . . . . . . . . . . . . 22

iii

Contents

8 Scaling and Future Trends . . . . . . . . . . . . . . . . . . . . . . . . . . 228.1 Scaling of other Radiation Effects . . . . . . . . . . . . . . . . . . 23

9 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2410 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

III Single Event Latch-up Test Circuit 25

1 Objective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 Design, Production & Assembly . . . . . . . . . . . . . . . . . . . . . . 27

3.1 Component Selection . . . . . . . . . . . . . . . . . . . . . . . 273.2 DesignMethod . . . . . . . . . . . . . . . . . . . . . . . . . . . 283.3 Production and Assembly . . . . . . . . . . . . . . . . . . . . . 28

4 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284.1 Verification of Requirements . . . . . . . . . . . . . . . . . . . . 304.2 Performance withMaster Unit . . . . . . . . . . . . . . . . . . . 31

5 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345.1 Proposals for a Future Circuit . . . . . . . . . . . . . . . . . . . . 345.2 Replacing the Master System . . . . . . . . . . . . . . . . . . . . 345.3 Adjusting the Master System . . . . . . . . . . . . . . . . . . . . 355.4 Supply Line Resistance . . . . . . . . . . . . . . . . . . . . . . . 365.5 RS485 Connector . . . . . . . . . . . . . . . . . . . . . . . . . 36

6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

IV Radiation Tests 39

1 Objective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392 University Test Equipment . . . . . . . . . . . . . . . . . . . . . . . . . 39

2.1 SAMPAASIC . . . . . . . . . . . . . . . . . . . . . . . . . . . 402.2 SAMPATest-board . . . . . . . . . . . . . . . . . . . . . . . . . 402.3 Single Event Upset System . . . . . . . . . . . . . . . . . . . . . 402.4 Single Event Latch-up System . . . . . . . . . . . . . . . . . . . 412.5 Verification of Latch-up System Before Tests . . . . . . . . . . . . 42

3 Heavy ion SEE test of the SAMPAASIC . . . . . . . . . . . . . . . . . . 443.1 Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443.2 Facility Equipment . . . . . . . . . . . . . . . . . . . . . . . . . 443.3 Adjustments to University Equipment . . . . . . . . . . . . . . . 443.4 Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463.5 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463.6 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

4 Laser SEE test of SAMPAASIC . . . . . . . . . . . . . . . . . . . . . . . 514.1 Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514.2 Facility Equipment . . . . . . . . . . . . . . . . . . . . . . . . . 514.3 Adjustments to University Equipment . . . . . . . . . . . . . . . 524.4 Voltage Regulation Characterisation . . . . . . . . . . . . . . . . 524.5 Attempts to Find the Sampling Rate Bottleneck . . . . . . . . . . 53

iv

Contents

4.6 Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534.7 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544.8 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

5 A Note on the System’s Sampling Rate . . . . . . . . . . . . . . . . . . . 596 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

V IDE3466’s Latch-up Protection 61

1 Objective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612 The IDE3466 ROIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

2.1 IDE3466 SEL DetectionModule . . . . . . . . . . . . . . . . . . 613 Common Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634 Tests of the IDE3466 SELDM . . . . . . . . . . . . . . . . . . . . . . . . 65

4.1 Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654.2 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

5 Tests of the SELDMApplication . . . . . . . . . . . . . . . . . . . . . . 695.1 Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 695.2 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

6 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 746.1 The IDE3466 SELDM . . . . . . . . . . . . . . . . . . . . . . . 746.2 Remarks on the SELDMMeasurements . . . . . . . . . . . . . . 746.3 The IDE3466 SELDM as a part of the RADEM Instrument . . . . 756.4 The SELDM Experimental Application . . . . . . . . . . . . . . 756.5 Proposals for the SELDM Experimental Application . . . . . . . . 766.6 Comparisons with SELTC . . . . . . . . . . . . . . . . . . . . . 776.7 The IDE3466 SELDM as a Circuit Offering . . . . . . . . . . . . 78

7 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

VI Conclusion 81

Appendix 82

A SELTC Layout and Schematics . . . . . . . . . . . . . . . . . . . . . . . 83B C++ Program for SELTC Testing . . . . . . . . . . . . . . . . . . . . . . 91C Oscilloscope Measurement of the SELTC’s Detection Delay . . . . . . . . . 93D Python Application for SELTCReadout . . . . . . . . . . . . . . . . . . 95E C++ Program for Python Comparison . . . . . . . . . . . . . . . . . . . 99F IDE3466 SEL DMCharacterization SPI code . . . . . . . . . . . . . . . . 103G IDE3466 SELDM Experimental Application Code . . . . . . . . . . . . . 105H Oscilloscope Measurements of the IDE3466 SELDM . . . . . . . . . . . . 109I Measurement Data of the IDE3466 SELDM internal DAC . . . . . . . . . 113

Abbreviations 115

References 116

v

List of Figures

1 Annual sales in the global semiconductor market. Plotted using data fromSIA [13]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2 Illustration of the particle energies needed to penetrate the Earth magneto-sphere. ©IEEE 1988 [28], reprinted with permission. . . . . . . . . . . . . 5

3 Energetic particle precipitation in the Earth atmosphere creating neutronsat ground level. ©IEEE 2003 [25], reprinted with permission. . . . . . . . 6

4 Simulation of particle fluxes in near-earth (interplanetary) space at maxi-mum solar activity. Made using CREME96 [37, 38], which accounts fortrapped protons, solar energetic particles and cosmic rays. . . . . . . . . . . 7

5 Illustrationof theVanAllenbelts present aroundEarth. Picture fromNASA’sLangley Research Center [40]. . . . . . . . . . . . . . . . . . . . . . . . 8

6 Observed variation in cosmic ray particles, caused by solar activity. ©IEEE2008 [44], reprinted with permission. . . . . . . . . . . . . . . . . . . . . 8

7 Flux of protons with Ekin ≥ 10MeV at 500 km altitude, generated withSPENVIS [42]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

8 LET in a carbon absorber as a function of the incident particle’s kinetic en-ergy. Irradiated particles from top to bottom: xenon, krypton, argon, oxy-gen and helium. ©2012 Elsevier [64], reprinted with permission. . . . . . . 11

9 Cross sectionofCMOSstructure irradiatedby ionisingparticles. OneNMOS(left) and PMOS (right) device shown. . . . . . . . . . . . . . . . . . . . 12

10 Parasitic BJTs present in a CMOS structure. One NMOS (left) and PMOS(right) device shown. Adapted from Shoga & Binder [74]. . . . . . . . . . 13

11 Parasitic thyristor in n-well CMOS, with high and low potential connectedthrough PMOS and NMOS transistors. Adapted from Troutman [73]. . . 14

12 Current-voltage characteristic of a PNPN junction, representing the idealthyristorwithout substrate andwell resistances. ©IEEE 1998 [77], reprintedwith permission. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

13 N-well minority carrier guard ring collecting charges in bulk (top) and epi-taxial layer (bottom) CMOS. ©IEEE 1998 [77], reprinted with permission. . 15

14 Thyristor holding voltage as a function of anode-to-cathode (NMOS-to-PMOS) spacing for different epitaxial layer thickness. ©IEEE 1996 [72],reprinted with permission. . . . . . . . . . . . . . . . . . . . . . . . . . 17

15 Typical latch-up sensitivity curveplotting cross section as a functionofheavy-ion LET. ©IEEE 2003 [20], reprinted with permission. . . . . . . . . . . . 21

vii

List of Figures

16 Damage inmetal layer of an integrated circuit after a single event latch-up of2 A, seen as metal spheres on conductors. ©IEEE 2002 [11], reprinted withpermission. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

17 Circuit diagram of the SELTC. Thick grey lines indicate bus signals. SELTCpower inputs (from supply) on the left, and power outputs (to DUT) onthe right. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

18 Flowchart describing the design process. . . . . . . . . . . . . . . . . . . 29

19 Printed circuit board ready for component assembly. . . . . . . . . . . . . 30

20 Assembled single event latch-up test circuit (SELTC01). . . . . . . . . . . . 31

21 Plot of a 10 Hz sine wave sampled by the SELTC acquisition of one channel. 33

22 Plot of a 1 Hz sine wave sampled by the SELTC acquisition of six channels. . 33

23 Block diagram of set-up used for both radiation tests. . . . . . . . . . . . . 40

24 DUT and SOC FPGA boards mounted in the chamber rack during theheavy-ion test. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

25 Set-up of functionality tests of the SELModule. . . . . . . . . . . . . . . 43

26 Custom long length cable made for the SELTC’s outputs. . . . . . . . . . . 43

27 Vacuum chamber at the UCLHIF. . . . . . . . . . . . . . . . . . . . . . 45

28 The UCLHIF vacuum chamber’s connector panel. . . . . . . . . . . . . . 45

29 Plot of the SAMPAv4current drawduring xenon-124 irradiation ions. Sup-ply lines from top to bottom: test-board 2.5 V, digital 1.25 V, analogue 1.25V, ADC-reference 1.10 V. . . . . . . . . . . . . . . . . . . . . . . . . . . 47

30 Plot detail of the SAMPA v4 2.5 V supply line current during xenon-124irradiation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

31 Plot detail of the SAMPA v2 digital supply line current during chromium-53 irradiation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

32 Plot of the SAMPA v2 digital supply line current during chromium-53 ir-radiation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

33 The control GUI of the Pulsys laser system. . . . . . . . . . . . . . . . . . 51

34 The irradiation chamber of the Pulsys laser system. . . . . . . . . . . . . . 52

35 Laser irradiation scan of the SAMPA v2 sensitive area. 1 µm resolution. . . 56

36 Laser irradiation scan of the SAMPA v2 sensitive area. 500 nm resolution. . 56

37 Substrate location of the SAMPA v2 automatic scans. . . . . . . . . . . . . 57

38 Single even latch-up threshold of the SAMPA v2, plotted against supplyvoltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

39 Substrate surface of SAMPA v4. . . . . . . . . . . . . . . . . . . . . . . . 58

40 Substrate surface of SAMPA v2. . . . . . . . . . . . . . . . . . . . . . . . 58

41 The bare IDE3466 die. . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

42 Circuit diagram of the IDE3466 SELDM. . . . . . . . . . . . . . . . . . . 63

43 Block diagram of a typical SELDM application. . . . . . . . . . . . . . . . 63

viii

List of Figures

44 IDEAS laboratory equipment used to interface the IDE3466. 1: LabFECboard, 2: power supply, 3: cable for LU-flag, 4: cable for SPI, 5: Pi, 6: SELAand SELB connection, 7: RADEM test-board with ROIC. . . . . . . . . . 64

45 Plot of shunt voltage versus supply sink current at each DAC step. . . . . . 6746 Plot of shunt voltage versus DAC step. . . . . . . . . . . . . . . . . . . . 6847 Flowchart describing the C++ program. . . . . . . . . . . . . . . . . . . . 6948 Flowchart describing a single incremental loop within the C++ program. . . 6949 Plot of sample delay caused by writing buffered data within the SELDM

application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7150 Plot showing incremental, decremental and averaged current calculated by

the SELDM application. . . . . . . . . . . . . . . . . . . . . . . . . . . 7251 Plot showing effect of using rolling average on data from the SELDMappli-

cation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7352 Delay caused bywriting to file in the SELDMapplication, at approxiamtely

440 ms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

53 Software single event latch-up detection delay of the SELTC. . . . . . . . . 93

54 Propagation delay measured from SELB1 input to LU1 output. . . . . . . . 10955 Propagation delay measured from SELB2 input to LU2 output. . . . . . . 11056 Propagationdelaymeasured fromSELB1 input to (externally buffered)GLU

output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11057 Propagationdelaymeasured fromSELB2 input to (externally buffered)GLU

output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11158 Propagation delay measured from SPI CLK input to LU1 output. . . . . . 11159 Detection delay of the SELDM application’s single event latch-up check. . . 112

ix

List of Tables

1 Maximum energy for various particle species found in space. ©IEEE 2003[25], reproduced with permission. . . . . . . . . . . . . . . . . . . . . . 7

2 Spacecraft orbits and their relevant radiation environment. Altitude valuesfromNASA’s Earth Observatory [39]. . . . . . . . . . . . . . . . . . . . 8

3 Countermeasures against single event latch-ups. . . . . . . . . . . . . . . . 16

4 RHBD libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5 Method for calculating the expected number of events from radiation hard-ness assurance test results . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6 Functional requirements for the single event latch-up test circuit. . . . . . . 26

7 Performance requirements for the single event latch-up test circuit. Samplesper second are indicated by S/s. . . . . . . . . . . . . . . . . . . . . . . . 26

8 Design requirements for the single event latch-up test circuit. . . . . . . . . 26

9 Operational requirements for the single event latch-up test circuit. . . . . . 27

10 Main components of the final single event latch-up test circuit. . . . . . . . 27

11 Specifications of the final single event latch-up test circuit. . . . . . . . . . 29

12 Compliance matrix listing requirements either not fully verified or met bythe current SELTC version. . . . . . . . . . . . . . . . . . . . . . . . . . 30

13 Proposed revisions of the single event latch-up test circuit board. . . . . . . 30

14 Sampling rate measurements of the SELTC interfaced by a C++ programrunning on the Raspberry Pi SoC. . . . . . . . . . . . . . . . . . . . . . . 32

15 An I2C read-operation’s CPU usage on the Raspberry Pi SoCmeasured us-ing ticks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

16 Through-software SEL detection delay measurements of the SELTC. . . . . 32

17 Measures to reduce the supply line resistance of the SELTC. . . . . . . . . 36

18 University equipment used for SEE tests. . . . . . . . . . . . . . . . . . . 39

19 Voltage regulation on the SAMPA test-board. . . . . . . . . . . . . . . . . 41

20 Difference in idle current draw during SEU tests performed the SAMPA v4digital supply line. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

21 Modifications done to Python program before performing radiation testswith the SELTC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

22 Sampling rate using Python to log shunt and bus voltages of four SELTCchannels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

23 Available particle cocktails at the UCLHIF. . . . . . . . . . . . . . . . . . 44

24 Setup of the SELTC during heavy-ion test. . . . . . . . . . . . . . . . . . 46

25 Results from heavy-ion test of the SAMPA v2 ASIC. . . . . . . . . . . . . 49

xi

List of Tables

26 Set-up of the SELTC for the laser test campaign. . . . . . . . . . . . . . . 5227 Typical LDO settings for varying DUT supply during laser irradiation. . . . 5328 Sampling rate after emitting various functions from the Python program. . 5429 Laser system beam parameters used during ASIC irradiation. . . . . . . . . 5430 Laser systemparameters usedduring automatic irradiation scanof the SAMPA

ASIC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5531 Single event latch-up thresholds found during laser irradiation of SAMPA

ASICs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5532 SELTC performance comparison of Python and equivalent C++ code. . . . 59

33 IDE3466 SELDM circuit parameters expected after simulation and design. . 6234 Test equipment used for work with the IDE3466 ROIC. . . . . . . . . . . 6435 Tests performed on the IDE3466 SELDM. . . . . . . . . . . . . . . . . . 6536 SELDM detection delay measurements. Output τ denotes the time con-

stant of the digital transition. . . . . . . . . . . . . . . . . . . . . . . . . 6637 Selection of IDE3466 SELDM characterisation values. . . . . . . . . . . . 6638 Current ranges of various shunt resistors, using the step voltagemodel found

through linear regression, and the simulated DAC step voltage. . . . . . . . 6739 The IDE3466 SELDM alternative application’s current measurement devi-

ation. DAC steps are denoted as s, shunt voltage slope as a, and shunt voltagebias as c. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

40 Parameters utilised in the IDE3466 SELDM application. . . . . . . . . . . 7041 Tests performed to benchmark the SELDM current-logging application. . . 7142 Current-logging application performance measurements . . . . . . . . . . 7243 Comparison of the 3D Plus LCL and the IDEAS IDE3466 SELDM. . . . . 79

44 Shunt voltage and supply current for each IDE3466 DAC step. . . . . . . . 114

xii

I Introduction

This chapter presents the motivation for examining single event latch-up protection solu-tions, the main goal of the thesis and summaries of each chapter’s contents.

1 Motivation

Integrated electronic circuits1 are ubiquitous inmodern electronics. Most circuit boards andsystems contain a plethora of integrated circuits performing different functions. The growthof annual sales in the global semiconductormarket is shown inFig. 1. As demandspushpricesand requirements these circuits evolve rapidly, increasing availability and application areas.Generic integrated circuits are present inmany harsh radiation environments on and aroundearth. Such environments and their particle radiation have been found to cause functionalfailures as well as permanent damage to semiconductor circuits2. Therefore, understandingas to how radiation can cause damage and how to protect against failure becomes increasinglyimportant.

1970 1980 1990 2000 2010 20200

100

200

300

400

500

Year

Sale

s [

Bill

ion U

SD

]

Global Semiconductor Sales 1978-2017

Figure 1: Annual sales in the global semiconductor market. Plotted using data from SIA [13].

1Semiconductor circuits of high density, implemented using conductors and isolators on doped silicon.[1]2See references [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12] for an historical overview of such radiation effects

1

I Introduction

2 Goal

Themain goal of this thesis is to explore single event latch-up protection circuits. The workwill contribute to future projects intended to operate in harsh radiation environments de-veloped by the University of Oslo (UiO). The first objective towards this goal is the develop-ment of a low-cost protection circuit. The circuit shall double as a single event latch-up testcircuit, in order to simplify radiation tests performed by the university and its partners. Thecircuit was to be validated at 2 radiation test campaigns. The second objective is the verifi-cation and application of a single event latch-up protection circuit developed by IntegratedDetector Electronics AS (IDEAS). This circuit is implemented in silicon using various radia-tion hardening techniques. It should therefore represent the high-end of protection circuits,both in terms of size, radiation tolerance and performance. Together, these two objectiveswill give insight into the variety of on-site single event latch-up protection circuits, providinga neutral perspective on single event latch-up protection for future circuit development atUiO and beyond.

3 Thesis Contents

Chapter I contains the introduction to the thesis.Chapter II summarises research on single event latch-up, providing a theoretical back-

ground for the rest of the thesis. In detail, the chapter covers the physicalmechanisms behindsingle event latch-up, countermeasures of various abstraction levels, radiation test methods,and single event latch-up in relation to technology scaling.Chapter III documents the productionof a circuit boardmademainly for testing the single

event effects sensitivity of components. The board was used in the radiation tests of chapterIV.

Chapter IV presents single event effects test campaigns performed to find the single eventeffects sensitivity and characteristics of an integrated circuit. The circuit-board documentedin the chapter III was used to detect and remove single event latch-ups.Chapter V covers work done with the IDEAS IDE3466 integrated circuit, and specifically

the single event latch-up detectionmodule it contains. Various parameters of themodule aremeasured, before it is experimented with in a typical use case scenario, exploring its potentialas a standalone commercial offering.Chapter VI summarises the work done during the master thesis, drawing an overall con-

clusion and discussing future possibilities.

2

II Theoretical Background

This chapter will cover relevant theoretical material and research on single event latch-up(SEL) in electronic circuits. Acting as an introduction to the chapter, radiation effects inelectronic circuits are summarised, followed by definitions relevant to particle radiation. Ra-diation environments, particle interaction and single event latch-up formation are then ex-plained, before various countermeasures and sensitivity testingmethods are evaluated. Tech-nology scaling and its relation to single event latch-up is discussed before concluding.

1 Radiation Effects in Electronic Circuits

Radiation effects are seen in electronic circuits hit by ionising radiation transferring energy tothe circuit [14]. A circuit’s response to radiation varies greatly, both in terms of incident radi-ation and circuit type. Radiation effects are divided into cumulative and single event effects.This thesis focuses on the single event effects, and specifically the permanent, potentially de-structive, effect called single event latch-up.

1.1 Cumulative Effects

Cumulative effects consist of total ionising dose (TID) and displacement damage (DD) [15].These effects worsen with increased exposure [15], making them especially relevant for pro-longed spacemissions. TID typically concerns trapped charges in transistor oxides [16], whileDD typically concerns changes in the semiconductor crystal lattice as a result of non-ionisingnuclear interaction [15]. These effects are actively prevented by shielding, and/or annealingi.e. baking the semiconductor at high temperatures [17, 18].

1.2 Single Event Effects

Single event effects in electronic systems are caused by the interaction of an energetic particlewith the system’s electronic components [19]. Single event effects (SEEs) are stochastic, asonly a single particle is needed to induce an effect within a circuit. These radiation effectswere discovered in the early 1970s [2, 3, 4], and are classified according to their consequence[20]. The top-level division is into non-destructive and (potentially) destructive SEEs [20].Non-destructive SEEs, also called soft errors[5], are removable and do not cause permanentdamage to the circuit [5]. A commonnon-destructive SEE is single event upset (SEU), whichresults in logical bit-flips [21]. These bit errors are recoverable by rewriting the affected bit[21]. Commondestructive SEEs are single event latch-ups, single event burnouts, single eventgate ruptures and single event snapbacks [20].

3


Single event latch-up occurs in complimentary metal-oxide semiconductor (CMOS) cir-cuits hit by a single ionising particle [2, 3, 20, 22]. Today, 98 percent of newly designed digi-tal systems utilise a CMOS process [1]. The consequence of single event latch-up in CMOScircuits can be thermal failure and/or localised metal fusion [20], eventually leading to non-functional components and system failure [6, 7, 8]. The following particles can theoreticallytrigger latch-up [23, 24]: heavy ions i.e. alpha particles, protons, neutrons, and high-energyphotons. AsCMOS technology is widespread, and these particle types exist inmany environ-ments [25, 26], single event latch-up is a phenomenon important for engineers to understandand counteract. Single event latch-ups are further explained in section 5.

2 Particle Radiation

According to Knoll [27] we can divide particle radiation into two, "charged particulate ra-diation" and "uncharged radiation". Each of these contain two subcategories, "charged par-ticulate radiation" containing fast electrons and heavy charged particles, and "uncharged ra-diation" containing neutrons and electromagnetic radiation. This thesis will focus on heavycharged particles, as these are especially capable of triggering single event latch-ups. Howheavy charged particles trigger single event latch-up will be described in section 5. Knoll [27]is the main source of the material presented in this section.

2.1 Energy Units

Aparticle’s kinetic energy is usually defined by the unit electron volt, or eV. Electron volts areequivalent to Joules (1 eV = 1.602 · 10−19 J). The energy of one 2e charge alpha particleaccelerated by a 1 V-potential equals 2 eV. Radiation energies up to several GeV are commonin space scenarios, as will be shown in section 3.2. Fig. 2 from Stassinopoulos [28] shows thekinetic energies needed to penetrate Earth’s magnetosphere.

2.2 Heavy Charged Particles

According toKnoll, heavy chargedparticles include all energetic ionswithmass of one atomicmass unit ormore. This includes protons, alphaparticles, fissionproducts, aswell as productsof many other nuclear interactions.

2.3 Neutrons

Neutrons are often divided into slow and fast neutrons. Slow and fast defines the kineticenergy of the neutron, with slow being below a few eVs, and fast up to hundreds of MeVs.Thermal neutrons are an example of slow neutrons. A thermal neutron is slowed down,or "thermalised" by a moderator to a kinetic energy of 0.025 eV. Even at this kinetic energy,the thermal neutrons can cause excitation within an absorber: when irradiated by thermalneutrons, a boron-10 absorber will decay into lithium-7 and an alpha particle. The kineticenergy of this alpha particle can be 1.47 MeV, or higher if lithium-7 reaches its ground state.

4

3 Radiation Environments

Figure 2: Illustration of the particle energies needed to penetrate the Earth magnetosphere. ©IEEE1988 [28], reprinted with permission.


One can divide the natural radiation environments into terrestrial, atmospheric, and space[25, 28]. Human made radiation environments are called artificial environments, and in-clude the particle accelerator like that of the Large Hadron Collider (LHC) at CERN (Con-seil Européen pour la Recherche Nucléaire) [29]. The radiation environment of the LHC isknown to induce single event effects in standard, COTS (CommercialOff The Shelf) compo-nents [30, 31]. Almost all radiation environments contain either neutrons or heavy-chargedparticles [25, 30]. Different environments contain different types of particle radiation species[25], and some are thereforemore prone to trigger latch-up in circuits than others [32]. Thisnecessitates considering the intended environment when working with electronics. Inter-planetary space and Earth’s inner radiation belt are two examples of radiation environmentscontaining an abundance of particle radiation [32], and consequentially, both environmentshave been found to cause system failures in the past [8].

3.1 Atmospheric & Terrestrial Environments

Particle radiation seen at ground level is mainly the remainder of energetic particle precipita-tion [25, 26]. Fig. 3 taken from Barth [25] shows particle precipitation and its decay. Heavycharged particles passing Earth’s magnetic field are usually deflected or trapped within it, butsome particles manage to enter the atmosphere. These particles, mainly galactic cosmic rays(GCRs) and at times solar energetic particles (SEPs), decay or slow down when interactingwith atmospheric particles [25], resulting in heavy ions, protons, neutrons, electrons, pions,and muons. As a result, the charge and mass of these particles decrease during their descent.Before reaching ground level, the particle precipitation will reach an altitude where the rateof ionising particles is at amaximum, known as theRegener–Pfotzermaximum [33], located

5


at approximately 20 km. The atmospheric radiation is especially relevant to commercial andmilitary aircraft, and has been found to cause data error in airborne circuits [34]. When theprecipitation reaches ground level, its particles have experienced 6-7 interaction generations,and most of them have decayed into low-mass particles, like neutrons [26]. As previouslymentioned in section 2.3, neutrons can interact with absorbers, causing them to emit par-ticles of notable kinetic energy. As a result, neutrons are capable of triggering single eventeffects in electronic circuits [10, 24, 35]. This emphasises the importance of testing electron-ics for the ground level radiation environment too, even though few directly ionising parti-cles are present. Indeed, the first research paper [36] mentioning radiation induced failuresin electronics predicted that terrestrial cosmic rays would infer a limitation on the packingdensity of semiconductor devices.

Figure 3: Energetic particle precipitation in the Earth atmosphere creating neutrons at ground level.©IEEE 2003 [25], reprinted with permission.

3.2 The Space Environment

For simplification, the term spacewill here include all environments fromorbital to interstel-lar space. The flux of various particles (1 ≤ Z ≤ 28) in near-earth space is plotted in Fig. 4.Note that high-energy particles are rare, while low-energy particles are common. Maximumparticle energies found in the space environment [25] are listed in Tab. 1.

GCRs and SEPs in the Earth magnetosphere see the magnetic field act upon them due tothe Lorentz force [25]. Some of these charged particles are trapped by the magnetic field[28], creating radiation belts also known as Van Allen belts, shown in Fig. 5. The centre ofthe inner belt is located at approximately 2500 km above sea level, while the outer belt is at

6


Table 1: Maximum energy for various particle species found in space. ©IEEE 2003 [25], reproducedwith permission.

Particle Type Maximum Energy

Trapped Electrons 10’s of MeVTrapped Protons &Heavy Ions 100’s of MeVSolar Protons ~GeVSolar Heavy Ions ~GeVGalactic Cosmic Rays ~TeV

100

101

102

103

104

105

Kinetic Energy (MeV/nucleon)

10-9

10-7

10-5

10-3

10-1

101

103

Flu

x (

m2-s

-sr-

Me

V/n

uc)-1

1-H4-He12-C14-N16-O56-Fe

Figure 4: Simulation of particle fluxes in near-earth (interplanetary) space at maximum solar activ-ity. Made using CREME96 [37, 38], which accounts for trapped protons, solar energeticparticles and cosmic rays.

approximately 20000 km [25]. The inner belt is dominated by protons, and the outer byelectrons as shown in Fig. 5. Usually, satellite orbits are classified according to altitude, seeTab.2 which shows the division into low earth orbit (LEO), medium earth orbit (MEO) andhigh earth orbit (HEO) [39].

As a result of the misalignment of Earth’s magnetic dipoles, and rotational axis, the in-nermost Van Allen belt is notably closer to ground level over South America [25]. This area,which contains anunusual amount of particle radiation for its altitude, is known as the SouthAtlantic Anomaly (SAA) [41]. In the area proton rich radiation is found at altitudes as low as200 km, according to SPENVIS [42] and the utilised "AP8"model. As a result, LEO satellitestravelling through the anomaly see single event-related failures in disproportionate numbers[8, 41]. When protons interact with matter, nuclear collisions can create secondary particlescapable of large energy transfers, further described in section 5. A SPENVIS [42] simulationof the flux of protons at 500 km altitude is shown in Fig. 7, illustrating the South AtlanticAnomaly. The simulated altitude of 500 km is approximately the altitude of the Interna-tional Space Station in LEO [43].

7


Table 2: Spacecraft orbits and their relevant radiation environment. Altitude values from NASA’sEarth Observatory [39].

Orbit Altitude Environment Particles

LEO 180-2000 km Inner belt & SAA Trapped p+ & e−

MEO 2000-36000 km Van Allen belts Trapped e− & p+

GEO ≈36000 km Solar rays, GCR e−, p+, heavy ions

Figure 5: Illustration of the Van Allen belts present around Earth. Picture fromNASA’s Langley Re-search Center [40].

Themain source of radiation in our solar system is the Sun, and its intensity varies with anapproximate cycle of 11 years [44]. In addition to the solar radiation, GCRs of high kineticenergies originating from outside the solar system are also present. Within the heliosphere,the GCRs are found to be anti-correlated with the solar activity because of the Sun’s proxim-ity [25]. This effect can be seen in Fig. 6 from Bourdarie [44].

Figure 6: Observed variation in cosmic ray particles, caused by solar activity. ©IEEE 2008 [44],reprinted with permission.

8

4 Stopping Power

Figure 7: Flux of protons withEkin ≥ 10MeV at 500 km altitude, generated with SPENVIS [42].

4 Stopping Power

Aheavy charged particle entering an absorber transfers energy to it through interaction withthe absorber electrons and nuclei [27, 45]. In integrated circuits (ICs), the absorber is usuallysilicon crystal in addition to conductors and dielectricmaterials [46], where the dielectric cancontain the previously mentioned neutron-sensitive boron. Researchers have worked withparticle interaction since the turn of the 20th century. Bohr [47], Bethe [48], Bloch [49]and Fermi [50] provided the basis needed for today’s models and calculations of particle in-teraction. Stopping power, as shown in the Bethe-Bloch formula [27] of Eq. 1, representsan ionising particle’s rate of energy loss along its path, either by means of excitation and ion-isation of the absorber medium [27, 48]. Particles with a higher charge Z exhibit a largerstopping power due to increased ionisation. Particles of higher kinetic energyEkin, or veloc-ity v, will exhibit a smaller stopping power due to the reduced duration of the interactionsand ionisation. When the incident particle has been slowed down to a low veloctiy, it willstart exchanging charges with the absorber medium, making other stopping forces like non-ionising energy loss (NIEL) and secondary reactionsmore prominent [27]. The Bethe-Blochis therefore imprecise at lower particle energies [27].N represents the density of the absorber,whileA is the absorber’s atomic number. With exception ofA, the expression for the scalarB is only evaluated for relativistic particles. The unit for the incident particle’s kinetic en-ergy is MeV, or MeV/amu if divided by the particle’s atomic mass [51]. Stopping power, S isdeclared in units of MeV/cm, or MeV·cm2/mg if divided by the absorber’s density [27].

9


S = −dE

dx=

4πe4Z2

m0v2NB (1)

where

B ≡ A [ ln(2m0v

2

I)− ln(1− v2

c2)− v2

c2]

and

S ∝ z

v2given the same absorber.

4.1 Linear Energy Transfer

The rate of energy transfer can also be denoted as linear energy transfer (LET) [52], alsoknown as electronic stopping power [53]. LET is often utilised in stead of stopping powerwhen describing heavy charged particles that cause single event effects [54, 55, 56], as it isalmost equal to the energy that generates electron-hole pairs within the absorber [57]. Asdefined in Eq. 2, LET is the linear rate of energy deposited within the absorber. A linearenergy transfer will disregard other stopping forces like non-ionising energy loss (NIEL) andsecondary reactions [27, 58], and LET therefore excludes some of the stopping forces. Theperspective of something being deposited within the absorber is oftenmore convenient thantraditional stopping power, especially when using silicon detectors.

LET = |S| = dE

dxis the linear energy transfer. (2)

where

LET ∝ z

v2given the same absorber.

⇒ less kinetic energy per nucleon yields larger LET.

4.2 Modelling Tools

LET is often calculated with models using the particle’s incident kinetic energyEkin, chargeZ and atomic number A, together with the properties of the absorber medium [53]. Ex-amples of models utilising data records together with stopping theory are SRIM [59], theNIST databases [60], and MSTAR [61, 62]. There has been uncertainty in the calculationsof these models, both for heavier particles [53], and lower incident kinetic energies [63]. Atlower kinetic energies, the particle will start recombining with the absorber, reducing energylost through ionisation. Consequently, NIELwill becomemore prominent at lower energies[58]. Fig. 8 shows a the calculation of LET with a relatively new model by Javanainen [64].

10

5 From Irradiation to Single Event Latch-up

The data correlate with the Bethe-Bloch formula at higher energies and down until someMeV/amu, where they reach the Bragg peak1 and the LET decreases due to recombination.

Figure 8: LET in a carbon absorber as a function of the incident particle’s kinetic energy. Irradiatedparticles from top to bottom: xenon, krypton, argon, oxygen and helium. ©2012 Elsevier[64], reprinted with permission.


A particle’s capability to trigger single event latch-up is dependent on the number of excesscharge carriers it releaseswithin the silicon substrate [20]. Thenumber of generated electron-hole pairs correspondswith the energy transferred to the circuit. In silicon, the energy neededto generate one electron-hole pair, also known as the ionisation energy, is approximately 3 eV[27]. Ergo, a higher LET throughout the charged particle’s interaction, i.e. xenon in thepreviously shown Fig. 8, indicates a greater capability to trigger single event latch-ups.

5.1 Neutrons and Protons Triggering Latch-up

It is tempting to draw the conclusion that neutrons will not be able to trigger latch-ups, asneutrons have no charge. The same is true for protons as their mass is small compared toheavier ions. However, neutrons [6, 24] as well as protons [67] have been found to triggerlatch-up in integrated circuits. Even thermal neutronswith theirminute kinetic energies havebeen found to trigger single event effectswhen interactingwithboron-10 inside integrated cir-cuits [68]. Instead of direct ionisation, these particles indirectly ionise the absorber through

1The peak of the Bragg curve, a plot of the stopping power versus penetration depth [27, 65]. The Bragg peakis utilised extensively by proton therapy [66].

11


secondary particles emitted by inelastic nuclear collisions [10, 69, 70]. The secondary particlecan be an alpha particle, and thus a charge-less particle like a neutron is able to cause a singleevent latch-up in a circuit. Increasing incident angle is found to increase the the probabil-ity of single event latch-ups when irradiating protons [6, 71]. Increasing the incident anglelengthens the particle track, and thus, the probability of a nuclear collision.

The probability of single event latch-up, or cross section, from protons has been foundto be approximately 10−5 as compared to heavy ions [72]. As shown earlier, protons andother light particles are more prominent in the natural radiation environments than heavierions. Fig. 4’s simulation found H-1 ions, or protons, to be of approximately 104 higher fluxthan Fe-56 in the near-earth radiation environment. An evenmore proton-rich environmentlike the inner Van Allen belt should see the difference in proton flux compared to heavy ionssurpass the difference in cross section. If this is the case, the number of proton-triggeredlatch-ups will surpass that of heavy ions.

5.2 Single Event Latch-up Formation

The formation of a single event latch-up in a bulk CMOS circuit is described chronologicallyin the list below [20, 23, 73]. The particle’s (direct or indirect) interaction with (n-well, bulkCMOS) silicon substrate, leaving electron-hole pairs is shown in Fig. 9. After the ionisation,a single event latch-up has the same characteristic as a traditional latch-up [23, 73], which canbe triggered by othermeans such as electrostatic discharge (ESD). To understand single eventlatch-up better we will look at both the triggering and the latched "thyristor" operation thatfollows. The parasitic bipolar junction transistors (BJTs) that create the thyristor is shownin Fig. 10, and the equivalent circuit diagram when the CMOS is connected as an inverterin Fig. 11. A CMOS inverter [1] connects the n-channel MOSFET’s (NMOS) source andbody to the negative rail (VSS), and the p-channel MOSFET’s (PMOS) source and body tothe positive rail (VDD).

Figure 9: Cross section of CMOS structure irradiated by ionising particles. One NMOS (left) andPMOS (right) device shown.

The single event latch-up occurs as follows:

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1. An incident particle irradiates the silicon of the CMOS substrate, generating electron-hole pairs along its path.

2. If the device is powered, the electron-hole pairs will flow towards the positive and neg-ative voltage rails as dictated by their polarity.

3. The charges travel through pn-junctions within the substrate on their way to the sup-ply rails.

4. If the current is large enough, parasitic BJTs will be biased, effectively turning on aparasitic thyristor, seen in Fig. 10 and 11.

5. The result is a low-impedance current path acting as a short between the voltage rails,limited in theory only by the resistances within the substrate.

6. If the voltage rails is larger than the thyristor "holding voltage" the BJTs will draw largecurrents, increasing thedissipatedpower inboth substrate and conductors, potentiallyleading to thermal failure.

Figure 10: Parasitic BJTs present in a CMOS structure. One NMOS (left) and PMOS (right) deviceshown. Adapted from Shoga & Binder [74].

5.3 Thyristor Operation

Thyristors have been used since the 1950s in high-current switching applications [75, 76],and are also known as PNPN diodes, or silicon-controlled rectifiers. A circuit diagram of theparasitic thyristor present in CMOS technology is shown in Fig. 11. In this configuration,the NMOS transistor is referenced to VSS and PMOS transistor to VSS. If one removes theresistances from this circuit it represents the ideal thyristor.The current-voltage characteristics of an ideal thyristor is shown in Fig. 12 by Hargrove

[77]. The thyristorworks in a regenerative fashion [73], with the accumulated current of onetransistor feeding into the base of the other and then amplified by the respective gain β. Theconnection acts as a short between VDD and VSS, as long as the BJTs are biased in saturation

13


VDD

RNWELL

RPSUB

VSS

Figure 11: Parasitic thyristor in n-well CMOS,with high and low potential connected through PMOSand NMOS transistors. Adapted from Troutman [73].

[73]. The voltage drop needed to bias the BJTs is shown by the dashed lines from VS to VH

in Fig. 12’s plot. When the circuit is biased leading, the current will rise to its maximum. It isfound that biasing only one of these pn-junctions fully is sufficient to accomplish a latch-up[72], meaning the holding voltage can be smaller than two pn-junction drops. The holdingvoltage of the parasitic thyristor in bulk CMOS has been found to be as low as 1 V at roomtemperature [78].

5.4 Micro Latch-ups

In larger integrated circuits, single event latch-ups can happen in separate parts of the circuit[72]. Single event latch-ups happening in the various locations, can each increase the currentin a latched state. If the thyristor current of these circuits are limited by the power supply, orcountermeasures alike those listed in section 6 are used, then the total current can be found toincrease with discrete steps for each single event latch-up [79]. These events, represented bydiscrete current steps, are called micro latch-ups [79, 80]. Micro latch-ups have been foundto correlate with bursts of SEUs when occurring in memory circuits [79].

6 Countermeasures

Countermeasures against single event latch-up distinguished by the level at which they are in-troduced [73, 81]. Process countermeasures are implemented by altering the semiconductorproduction process; layout countermeasures are implemented by altering the design of the

14

6 Countermeasures

Figure 12: Current-voltage characteristic of a PNPN junction, representing the ideal thyristorwithoutsubstrate and well resistances. ©IEEE 1998 [77], reprinted with permission.

integrated circuit; system countermeasures are implemented with an already produced cir-cuit within the intended system. A selection of countermeasures are listed in Tab. 3. Most ofthese bringwith them an area and/or cost increase. The effective and often recommended so-lution [23, 73] of combining guard rings in layoutwith an epitaxial layer process is illustratedin Fig. 13 by Hargrove [77], where minority charge carriers are deterred by an underlying,highly doped substrate and/or collected by a guard ring.

Figure 13: N-well minority carrier guard ring collecting charges in bulk (top) and epitaxial layer (bot-tom) CMOS. ©IEEE 1998 [77], reprinted with permission.

6.1 Process Level Latch-up Countermeasures

Process countermeasures usually aim tomitigate latch-ups by decoupling the free charge car-riers from the parasitic BJTs [3, 73]. The exception to this is diffusion [73], which rather aimsto spoil the gain of the BJTs. Diffusion is not used much at modern production nodes as itaffects performance [73]. Circuits implementing process-level countermeasures are called ra-

15


Table 3: Countermeasures against single event latch-ups.

Technique Implementation Explanation Ref.

Silicon-on-insulator ProcessUse insteadof bulk CMOS.

[82, 83]

Epitaxial ProcessDecouple BJTs with thinepitaxial layer on highlydoped substrate.

[73, 84]

Diffusion. ProcessSpoil BJT gainby reducingcarrier lifetime.

[73]

Trench ProcessIsolate p- and n-channelswith dielectric trench.

[77]

Guard rings LayoutProvide low-impedancepath to supply voltagefor charge carriers.

[73, 83]

Spacing LayoutIncrease transistor spacing,lowering BJT gain.

[23]

IC watchdog Layout/systemIntegrated monitoring ofrail, de-latching if currentis larger than threshold.

[85]

PCB watchdog SystemMonitoring IC supply,de-latching if current islarger than threshold.

[11, 20]

Temp. decr. Process/layout/system Reduce heat/power. [74, 86]

Supply decr. Process/layout/system Design for Vsup < Vholding . [24, 77]

diation hardened by process (RHBP). Generally, process-level countermeasures increase fab-rication cost, especially the silicon-on-insulator process which is 10-15 percent costlier thanCMOS [81]. It is worth mentioning that the effectiveness of process-level countermeasuresare dependent on the specific CMOS technology, and how these scale [87] which is discussedfurther in section 8

An example is the epitaxial layer, a thin, lightly doped silicon layer deposited (by meansof epitaxy) on a highly doped substrate [88], where semiconductor circuit’s can be imple-mented. The highly doped substrate below the layer can act upon charge carriers in the epi-taxial layer, e.g. deterring minority charge carriers [73]. The thinness of the epitaxial layershould also lead to a lower energy transfer, on account of fewer interactions within the epi-taxial layer and thus circuit. It is also worth mentioning that an epitaxial layer increases thethyristor holding voltage [72, 77], meaning the parasitic thyristor needs a larger voltage to be

16

6 Countermeasures

biased leading. The effect of implementing an epitaxial layer on holding voltage is shown inFig. 14 from Johnston [72]. All of these properties should be beneficial against single eventlatch-up, making the epitaxial wafer a recommended process-level countermeasure [3, 89].

Figure 14: Thyristor holding voltage as a function of anode-to-cathode (NMOS-to-PMOS) spacingfor different epitaxial layer thickness. ©IEEE 1996 [72], reprinted with permission.

6.2 Layout Level Latch-up Countermeasures

Layout techniques alter the integrated circuit’s topology, mainly to lead charges away fromthe parasitic thyristor [73]. Circuits using these techniques are called radiation hardened bydesign (RHBD). RHBD libraries maintained by various companies are listed in Tab. 4.

A commonRHBDtechnique used against latch-up are guard rings [73, 46], whichwere il-lustrated in Fig. 13. A guard ring contactmakes the driving potential available in the substrateand/or well. By collecting the free charge carriers, less current is available for the parasiticthyristor and its BJTs, reducing the chance of latch-up. Implementing guard rings increasesthe area of the integrated by 10-15 percent [81] and as a result, the cost. If implemented on anepitaxial layer, guard rings are even more effective [77]. As previously shown in Fig. 13, thehighly doped substratewill determinority carriers, leading them to the guard ringswithin thethin, epitaxial layer. Another layout-level countermeasure is to increase the anode-to-cathodespacing [72]. In addition to lowering the BJT gain, this increases the holding voltage of theparasitic thyristor, as seen in Fig. 14 by Johnston [72].

6.3 System Level Latch-up Countermeasures

Finding components that are designed, tested andqualified for harsh radiation environmentsis not always easy, especially not within budget. Using COTS components instead will createthe need for system-level latch-up countermeasures. System-level countermeasures typicallymonitor the supply current for large values, and power cycle once a high-current state (latch-up) is detected [20]. This will turn off the thyristor’s BJTs. Such circuits are known as watch-

17


Table 4: RHBD libraries

Organisation Library Ref.

ESA DARE (0.18um) [90]

CERN 0.25um for LHC [91]

IDEAS 0.35um CMOS [92, 93]

BAE 0.15um [94]

Ramon 0.18um& 0.13um [95]

Cobham 600nm-90nm [96]

MicrochipMH1RT (0.35um),ATC18RHA (0.18um),ATMX150RHA (0.15um SOI)

[97]

ATK 0.35um [98]

STMicro 65nm [99]

dog circuits and can be implemented with various discrete components [11, 20] as shown inchapter III, or as a single integrated circuit [85, 100] as discussed in chapter V. Together withradiation hardness assurance testing, this countermeasure method represents a flexible andlow-cost solution to single event latch-up. Typical systems can be low-cost such as CubeSats.

It shouldbenoted, thatwhile this technique canbe sufficient to removehigh-current latch-ups, there are somedrawbacks. In complex integrated circuits [72], the current drawdependson which modules are in use. As a result, the current may increase in smaller, discrete jumps,called micro latch-ups [79], making single event latch-ups difficult to detect [72]. It’s there-fore an advantage if the component has multiple supply pins, making individual latch-upthresholds possible. It is also an advantage if the monitored lines have a regulator indepen-dent of the watchdog circuit. If not, voltage drops from the increase in current can turnoff the monitoring circuit, leaving the system unprotected. Another downside to this typeof countermeasure is the possibility of latent damage to the monitored component, causedby undetected latch-ups or latency in the latch-up removal [11]. This is described further insection 7.6.

6.4 Temperature and Supply Voltage

Two important single event latch-up countermeasures are adjustments to temperature andsupply voltage. In order to lower single event latch-up sensitivity, both temperature [74, 86]and supply voltage [70, 78]may be decreased. Decreasing temperature will lower the currentgain of the circuit’s parasitic BJTs [1], thus increasing latch-up formation time and decreasingmaximum current. Temperature effects on single event latch-up sensitivity are shown in Fig.15 from Sexton [20] under section 7.

18

7 Radiation Hardness Assurance Testing of Electronic Components

Decreasing the supply voltage will decrease the capability of the circuit to push and main-tain the latched current through the parasitic thyristor. If the supply is below the thyristorholding voltage in bulk CMOS, found to be approximately 1.1 V at room temperature [78],single event latch-up should in theory disappear. Lowering either can be done by changingthe process, layout or system set-up. For example, updating the process technology node ofa specific circuit will see a decrease in both supply voltage and power usage [46, 87], withtemperature most likely following.

6.5 Remarks on other Radiation Effects

Many of the aforementioned countermeasures will alter a circuit’s response to other radia-tion effects as well. Depending on the type of system, radiation environment and missionduration a system will be susceptible to some effects more than to others. One has to pri-oritise protecting against radiation effects that will pose the largest risk. For instance if oneconsiders TID or DD to be the biggest concern, it would not be advisable to add dielectricisolation like that of a silicon-on-insulator or trenches, as these trap charges and thus increasethe total ionising dose [82, 101]. If non-destructive SEEs like SEUs are a concern, one shouldnot lower the supply voltage, as this will increase the SEU cross section [10, 102], and thusincrease the soft error rate.

7 RadiationHardness Assurance Testing of Electronic

Components

The sources used for this section are Schwank [103] for heavy ion tests, the European Co-operation for Space Standardisation (ECSS) [54, 104] for test methods, and Dodds [71] forproton irradiation tests.

Radiation sensitivity of a circuit is tested by irradiating the circuit with particles of typesand energies either adhering to test standards [54, 104], or of similar energy transfers as theintended environment. The circuit is then monitored for effects, registering deviation fromthe expected circuit behaviour. In the case of SEE tests, the irradiating particles are typicallyprotons or heavy ions. Heavy ions are usually characterised byLET,while protons are usuallydenoted by kinetic energy. As previously mentioned, LET is usually calculated with uncer-tainty, and this is also true for the LET reported by the test facilities [105]. Typical heavy ionflux used during SEE testing 104-106 particles/cm2s [103, 56], while examples of heavy ionLET values are 1 to 60 MeV·cm2/mg [55, 56]. When testing standard, COTS components,one should note that different batches of components may see different radiation test results[106], as different processes yield slightly different circuits on account of wafer variations.

7.1 Single Event Latch-upMonitoring

Testing for single event latch-ups, the most commonmonitoring method is to measure sup-ply line current, and classify currents above a threshold as events. The supply line must bepower-cycled at these events, turning off the driving potential of the parasitic thyristor. It isimportant tomeasure the total circuit dead time, as the particles irradiated during this period

19


should be removed from the sensitivity calculation [72]. One should also test the circuit atthe maximum operating temperatures expected during the system’s lifetime, as higher tem-peratures increase the circuit’s latch-up cross section. This was shown in Fig. 15 from Sexton[20].

7.2 Cross Section Calculation

The goal is a graph of the circuit’s sensitive area as a function of energy, as shown in Fig. 15from Sexton [20]. The sensitive area is called the cross section σ, and has the unit cm2. Thecross section indicates the probability of an event at the respective energy. The circuit is irra-diated with a flux of particles while recording all events. At each energy value, the numberof events together with total number of irradiated particles, or fluence, provide the basis ofthe cross section at the respective LET, as shown in Eq. 3. If few cross section measurementsare made at each LET, one should include the counting error as shown in Eq. 4 [27]. Thelocation of a particle within a particle beam is random [27], therefore the empirical σ is thecross section’s expectation value. If several cross sectionmeasurements aremade at each LET,one should rather include the standard deviation of the measurements [105]. From the crosssection graph one can extract two parameters used to characterise a circuit’s single event effectsensitivity [20, 103]: the LETthr, which denotes the LET at which the circuit stops experi-encing the SEE, and σsat, the saturation cross section, which denotes the maximum crosssection found during the test. The cross section graph will asymptotically approach boththese values, as shown in Fig. 15.

σ(LET ) =nSEE

Fcm2 ± σe (3)

where

σe = 100 ·

√

(

√nSEE

nSEE)2 + (

√F

F

2

% is the counting error (4)

and F is the fluence, or number of irradiated particles. (5)

7.3 LET as a Function of Incident Angle

Changing the angle of incidence is found to increase the cross section when irradiating withheavy ions [71, 107]. Consequently, altering the incident angle is used during radiation hard-ness assurance tests to increase the "effective LET" of heavy ions [103]. Calculating this ef-fective LET is traditionally done by multiplying the calculated, vertically incident LET withits increased particle track [108], as shown in Eq. 6. Golke [108] also points out that this Eq.is only valid when the particle terminates outside the main substrate, for example for thinsubstrates like an epitaxial, or smaller incident angles. If this is not the case, one should usea more complex Eq. one to avoid errors. Schwank [chwank_radiation_2013] recommendslimiting the incident angle to 45

20

7 Radiation Hardness Assurance Testing of Electronic Components

Figure 15: Typical latch-up sensitivity curve plotting cross section as a function of heavy-ion LET.©IEEE 2003 [20], reprinted with permission.

LETeff =LET

cos θ(6)

where θ is the angle referenced to vertical irradiation

7.4 Calculating Expected Events in an Environment

After the cross section characteristic is found, it is possible to calculate the expected failuresusing freely available tools [37, 42, 109]. This makes it possible to determine whether the cir-cuit is suited for the a certain environment. Amethod for calculating the expected number ofevents is listed in Tab.5. As the cross section curves found from radiation hardness assurancetests are discrete, and contain few values, they are usually fitted. The Weibull-distribution isoften used for this purpose [105], but it can also be fitted to a log-normal function [110]. Assoft errors is possible to correct by implementing error-correction code [111], one may tol-erate such failures. On the other hand, one single event latch-up can be sufficient reason toreplace the component or system, because of its destructive nature.

7.5 Laser Radiation Testing as an AlternativeMethod

In the 1990s a new radiation testmethodwas developed [112, 113, 114], utilising a pulsed laserto generate charges within silicon. These pulses, lasting picoseconds [115], ionise the sub-strate through excitation of electrons beyond the band-gap energy [116] Once the electron-hole pairs are present, the circuit will respond as if it was irradiated by an ionising particle.

21


Table 5: Method for calculating the expected number of events from radiation hardness assurance testresults

# Method Tool Result

1 Beam-test σ-formula Sensitivity-vs-LET2 Modelling SPENVIS [42] or CREME [37, 38] Flux-vs-Energy3 Modelling SRIM [109] or Bethe-Bloch Flux-vs-LET4 Calculation Flux ·Tmission Fluence-vs-LET5 Calculation Convolution of σ& fluence curves Expected events

The laser differs from classical beam tests in two aspects: firstly, it is capable of irradiatingwith sub-micrometer precision [113]. This makes it possible to locate the sensitive compo-nents within a circuit. Calculating the cross section of an energy can therefore be done byscanning the entire circuit and finding the sensitive area precisely. One would expect this toproduce a result with smaller error than calculating the expected value from a particle beam.Secondly, there has not yet been done as much research and modelling of laser interaction[117], therefore the energy of a laser beam is not as easily translated to a radiation environ-ment. It is possible to empirically translate incident laser energy to LET, by finding the LETconversion factor [117, 118]. This conversion factor needs data from both a laser and heavyion test, using for example both threshold energies.

7.6 Latent Damage to Irradiated Circuits

If possible, a visual inspection with a microscope should be done of the integrated circuitafter it has experienced single event latch-ups. The circuit’s metal traces can rapidly fuse to-gether during latch-up events [11]. Single event latch-up can occur in areas of the circuitwith conductors under-dimensioned for larger currents, leading to relatively large dissipa-tions of power. A microscopic image of metallisation damage found on conductors after asingle event latch-up is shown in Fig. 16 from Becker [11]. The circuit was a processor withmany possible latch-up paths, complicating single event latch-up monitoring. In order forsuch damage to occur, the circuit only needs to be in a latched state for a short period. Ac-cording to Becker’s experiments [11], such damage can form as quickly as 60 µs, but also asslowly as 18 ms. Therefore, a test system with latency in its detection and power cycling mayallow for permanent damage. Newer, more complex circuits further complicate this issue, asthey enable latch-up currents of various sizes, or micro latch-ups [72, 79].

8 Scaling and Future Trends

When technology processes scale in size, it affects the electrical & physical characteristics ofcircuits [87]. As a consequence, the response to ionising radiation is also affected. Under-standing radiation effects scaling is complicated, as not every feature of CMOS scales propor-tionally with technology size. scaling theory [87], eachCMOS technology generation shouldsee a doubling of transistor density. As a result, one expects [87] a 30 percent reduction of

22

8 Scaling and Future Trends

Figure 16: Damage in metal layer of an integrated circuit after a single event latch-up of 2 A, seen asmetal spheres on conductors. ©IEEE 2002 [11], reprinted with permission.

gate delay, 50 percent reduction of switching power consumption, as well as a 30 percent de-crease in lateral and vertical dimensions. Today, specialised transistor structures like FinFETs[119] complicate these technology node parameters.

Single event latch-up sensitivity is strongly influenced by these changes. For example,threshold and supply voltages decrease to maintain efficiency and performance [87, 120],which should decrease the single event latch-up sensitivity, especially if the supply is lowerthan the thyristor holding voltage [20, 24], as this should remove latch-ups. Reducing tran-sistor size should also see the sensitive circuit area decrease, given the same circuit layout isimplementedwith a doubled transistor density. Charge collection depth should also decreasewith the vertical scaling [121], reducing the number of collected charges in the substrate.

However, single event latch-up scaling is not necessarily that simple. The thyristor hold-ing voltage is found to scale down with technology nodes [77], cancelling the advantage ofsupply voltage reduction. Modern CMOS technology nodes are usually defined by the min-imum distance between transistors [87], and manufacturers are therefore prone to prioritiselateral scaling. The vertical dimension, including isolation, well, and substrate might there-fore not scale synchronously. Neither is it clear that an increase in transistor density will leadto smaller circuit areas. Rather, the tendency seems to be an increase in total transistor countand functionality, worsening single event latch-up sensitivity [72]. Denser circuits can alsoexpect an increase in temperature, and following, an increase in single event latch-up sensi-tivity [74, 86]. All of these properties make it challenging to predict single event latch-up asCMOS technology scales.

8.1 Scaling of other Radiation Effects

As mentioned above, threshold voltages decrease when technology scales [120]. This willincrease leakage currents caused by the total ionising dose’s breakdown of gate oxides [122].A decrease in technology size is found to increase single event upsets [102]. For example, alower threshold voltages should increase SEU sensitivity, as fewer charges are needed to turnon theMOSFET and flip a bit [10, 102]. In addition, increasingmetallisation has been foundto correlate with single event upsets [35]. Increasing a circuit’s complexity naturally tends to

23


increase the number of metal layers, as well as bits within a circuit, and this could explainan increase in errors, however, one would expect the number of errors per bits to remainunchanged. The number of single event transients (charge pulses that travel through signalpaths) are found to increase with operating frequency [123]. As gate delay is reduced foreach technology node [87], it is reasonable to assume single event transients (SETs) increaseas well.

9 Summary

Ever since humans started exploring space, we have gathered data on radiation and its ef-fects on circuits and systems. The radiation environment in our solar system, and especiallyaround Earth has proven to contain a significant amount of radiation. This radiation, eventhough it usually has little kinetic energy, is capable of inducingmany kinds of failuremodes.After its introduction, CMOS circuits have been found to be vulnerable to radiation, evento neutrons on ground level. Some of the reason for this is that the internal structure ofthe CMOS substrate form a parasitic BJT circuit, equivalent to a circuit traditionally usedfor high-current switching. Free charges released by radiation can turn this circuit on, effec-tively shorting the power supply if its biased. Large amounts of power can then dissipatein substrates and conductors originally dimensioned for much smaller currents, leading toburn damage. After the smoke cleared, researchers found ways to protect against this incon-venient property of CMOS. Particles like neutrons are quite difficult to stop, and as a re-sult, the protectionmethods either involve changing the technology process, or dealing withelectron-hole pairs freedwithin the substrate. After decades of research, single event latch-uphas become a well understood radiation effect in electronic circuits. However, as integratedcircuits become more intricate in their design and architecture, understanding single eventlatch-up is mademore challenging, creating the need for continued development in this fieldof research.

10 Conclusion

When developing systems for various radiation environments, implementing effective pre-ventive measures in an integrated circuit’s layout or fabrication process represents a costlyoption. Commercial demand for radiation-hard components is relatively low compared tostandard COTS components. If COTS components are used, engineer’s need to understandradiation effects like single event latch-up, and how protect against them. For example, ra-diation tests are essential to ensure correct operation when using such components. Afterexecuting protection and testing, it is possible to produce low-cost radiation-hard systems.The relative cost of radiation tests will be small if the system is to be produced on a largescale, and especially compared to launching a system sensitive to radiation. Solutions for sin-gle event latch-up protection circuits, intended both for radiation testing and system-levelprotection, are discussed further in this thesis.

24

III Single Event Latch-up Test

Circuit

This chapter documents the development of a circuit board intended for radiation hardnessassurance testing, named the single event latch-up test circuit (SELTC). A circuit diagram isshown in Fig. 17. The specifications of the device are listed in section 4 Tab. 11. Schemat-ics and layout are found in appendix A. The circuit board was developed from August toOctober 2017.

Shunt Connector

LDOSWITCH Rsh

INA3221

Master Unit Connector

485UART RS-485

PWR1PWR2PWR3PWR4PWR5PWR6

DUT

IO

I/O

PWR1PWR2PWR3PWR4PWR5PWR6

4:6

1:3

654

I2C

RJ45

Figure 17: Circuit diagram of the SELTC. Thick grey lines indicate bus signals. SELTC power inputs(from supply) on the left, and power outputs (to DUT) on the right.

1 Objective

Theobjective of thisworkwas to create a circuit simplifying single event latch-up testing. Thecircuit is to be used by the electronics group at the University of Oslo (UiO) Department ofPhysics [124]. The group that develops electronics for rockets, satellites, as well as CERNprojects. In the longer perspective, the objective was to provide insight into low-cost singleevent latch-up protection circuitry for future system developments.

25

III Single Event Latch-up Test Circuit

2 Requirements

The circuit was to be used in SEE radiation tests at a heavy ion facility in November 2017and January 2018, further documented in chapter IV. System-level latch-up protection, asdocumented in chapter II section 6.3 were used as a basis for the requirements of the circuit,together with latch-up protection solutions of previous master theses [125, 126]. Section4.2.2 of the ESCC-25100 standard [104], and the generic radiation test scenario as explainedin chapter II section 7 were also taken into account. Tabs. 6, 7, 8 and 9 list the requirements.The division of requirements is inspired by the ECSS-E-ST-10-06C standard [127]. Primaryrequirements are indicated by shall, while secondary requirements are indicated bymay.

Table 6: Functional requirements for the single event latch-up test circuit.

# Description

F.1 The module shall measure current supplied to the DUT.F.2 The module shall have power cycle capability on the DUT supply.F.3 The module shall measure external shunts.F.4 The module may measure bus voltages supplied to the DUT.F.5 The module may have voltage regulation.F.6 The module may have long-range communication.F.7 The module may be radiation tolerant.

Table 7: Performance requirements for the single event latch-up test circuit. Samples per second areindicated by S/s.

# Description

P.1 The module shall measure current with at a minimum sampling rate of 100 S/s.P.2 The module shall switch off a latched supply line in less than 100 ms.P.3 The module may monitor voltages below 1 V.

Table 8: Design requirements for the single event latch-up test circuit.

# Description

D.1 The module shall be smaller than 200 cm2.D.2 The module shall be made with readily available, low-cost components.D.3 The module shall have standard electronics test-points and headers.

26

3 Design, Production & Assembly

Table 9: Operational requirements for the single event latch-up test circuit.

# Description

O.1 The module shall be connected in series with the DUT supply.O.2 The module shall be operated as slave.O.3 The module shall be controlled by a generic master unit.

3 Design, Production&Assembly

Following the requirements listed, a modular circuit was designed with COTS componentsusing the CADSTARprogram suite [128]. Main components used in the design are listed inTab. 10.

Table 10: Main components of the final single event latch-up test circuit.

Component Reference Comment Datasheet

Current measurement device INA3221 Three channels [129]Load switch TPS22990 Low-voltage [130]LDO device TPS7A85 Avail. on two DUT lines [131]Supply connectors Microfit Limits max. current [132]

3.1 Component Selection

For current measurements, the 3-channel, INA3221 [129] (INA) was chosen. This chip ismade for shunt and bus voltage over a shunt resistance, and utilises an I2C-interface. Themeasurement is done with an internal ADC (Analog-to-Digital Converter), with a defaultconversion time of 1 ms. The three channel set-up reduce the board area needed, andmake itpossible to connected three of these in a triple module redundancy (TMR) fashion. The ca-pability to measure bus-voltage is also valuable, as it enables measuring the thyristor holdingvoltage of a SEL-sensitive circuit.

Resetting the power line is essential tomake single event latch-ups non-destructive. There-fore, n-channel load switches [130] were added to each line. The switching time of NMOSis faster than that of PMOS transistors, and switching time should be as low as possible in atest scenario to avoid latent damage as well as instant destruction of the IC. The specific loadswitch was chosen by account of its low-voltage capability. By using a bias it can accomplishswitching voltages as low as 0.6 V, which should be below most thyristor holding voltages.Another advantage is its small package of 2 mm by 3 mm.

In order to quantitatively find the holding voltage, a low-dropout regulator (LDO) wasadded to two of the supply lines. The TPS7A85 LDO [131] was chosen on account of itsoutput voltage being adjustable down to 0.8 V. The LDO output voltage is set via pins con-nected either to ground or high-impedance. For this purpose, a DIP switch is used at oneLDO, while the other is connected to the master unit I/O header.

27


Radiation test equipment is not always close to the test operators. For the purpose of eas-ing communication with the test system, a RS485 transceiver [133] was added to the board,connecting two differential RS485-lines enabling full duplex communication. The masterunit can send and receive commands from the operator via an UART interface, with therange benefit of RS485. The operator system must possess an equivalent transceiver circuit.The RS485 signals are sent through a RJ45 connector and Cat 5e cable, as this was perceivedas a cheaper option to the proprietary RS485 connectors. The RS485 uses shielded twistedpairs, which should be covered by using a STP Cat 5e cable.

Standard 2.54 mm headers are added to increase ease of use. A master I/O header wasmade pin-compatible and equivalent to the main Raspberry Pi Soc (Rasp. Pi) header [134].The master header is a 2 x 20 2.54 mm pin-header, and gives the master unit access to theI2C line, LDO control pins, and the 3.3 V supply of the Rasp. Pi. In case of a SEU- and/orfunction-test, two DUT I/O headers can connect master and DUT unit. These headers areconnected one-to-one on the SELTC, like a feed-through. The purpose is to reduce the num-ber of cables going to the DUT, as interconnects can be sparse in tests using vacuum cham-bers, such as heavy ion tests. The DUT I/O header connecting the DUT also contains theSELTCpower outputs, enabling use of one cable, e.g. a flat-cable, to connect both power andI/O. The SELTC power outputs can also be connected using microfit connectors [132]. Insome set-ups, one needs shunt resistors placed on the DUT test-board. To accommodate forexternal shunt resistor measurements, a header provides access to the INA shunt nodes. Theshunt resistors on-board should then be disconnected, with exception of two lines where ajumper can be used. Utilising an external shunt renders the respective power line useless, asthe current will be led through the external shunt. The advised set-up is to turn off linesmeasuring external shunts. If SELTC’s power cycling is still needed, one can utilise one of theother power lines connected through a 0Ω on-board resistor.

3.2 DesignMethod

The design followed the work flow shown in Fig. 18. The board’s routing alternates betweenhorizontal and vertical directions for each layer. The printed circuit board (PCB) is designedusing four layers and a maximum line-width of 1 mm.

3.3 Production and Assembly

The PCB without components is shown in Fig. 19. The board was produced by the UiOelectronics laboratory, using standardFR4 substrate. Five boardswere ordered, togetherwithenough components for mounting two systems. The surface mounted devices were placedmanually, and a vapour re-flow oven was used to solder them in place.

4 Results

The design files sent for production are shown in appendixA. Parameter values of this designare listed in Tab. 11. The board was also validated during the heavy ion and laser radiationtests of chapter IV. The mounted PCB is shown in Fig. 20.

28

4 Results

SpecificationComponentselection

Schematics& layout

Spec.satisfieed?

Proeduction, assembly &testing

No No

Yes

Yes

Requirement

Req.satisfieed?

FinisheedPCB

Figure 18: Flowchart describing the design process.

The board can be interfaced by many master units, e.g. a Raspberry Pi SoC, but also FP-GAs and other micro-controllers in general. Up to six power supply lines can be fed throughthe board, utilisingmicrofit [132] connectors as inputs and outputs. All lines can be indepen-dently switched on/off with a digital signal. Three of the supply lines are connected to threeINA-circuits in parallel, enabling TMR. The board itself can be supplied by 3.3 V- and 5 V-pins for itsmain and bias supply, respectively, as supplied by aRaspberry Pi SoC. Jumpers areused for various options: bypassing LDOs, connecting board supply through motherboard,or connecting external shunt resistors. To connect the supply outputs to the DUT, one canuse either the microfit connectors or the standard 2.54 mm I/O header.

Table 11: Specifications of the final single event latch-up test circuit.

Parameter Value Comment

Vshunt 163.8 mV MaximumVline 0.6 V - 5.5 V Maximum = Vbrd,bias

Iline 8.5 A MaximumVbrd,bias 3 V - 5.5 V To LDOs & SWsVout,ldo 0.8 V - 3.95 V Ch. 6Vbrd,supply 3 V - 5.5 V SELTC supplyRsupply 70 mΩ MeasuredRreturn 25 mΩ Measured

29


Figure 19: Printed circuit board ready for component assembly.

4.1 Verification of Requirements

All primary requirements listed in Tabs. 6, 7, 8 and 9 are met by the current design. Somesecondary requirements are not fully met or verified. These requirements are listed in thecompliance matrix of Tab. 12 compliance matrix. Proposed revisions are listed in Tab. 13.

Table 12: Compliance matrix listing requirements either not fully verified or met by the currentSELTC version.

# Status Type

F.5 LDO not verified on one of two channels SecondaryF.6 RS485 transceiver not verified because of PCB damage SecondaryF.7 Assumed not met as a consequence of Req. D.2 Secondary

Table 13: Proposed revisions of the single event latch-up test circuit board.

Part Revision Comment

INA Switch + & - nodes Neg. current measurements-”- Separate INA at ext. shunt header Avoid occupying power linesLDO Place DIP-switch one both lines High-impedance I/OSilk screen Renumber at ext. shunt header Numbers indicating INA ch. incorrect

30

4 Results

Figure 20: Assembled single event latch-up test circuit (SELTC01).

4.2 Performance withMaster Unit

For the validation results of the circuit controlled by a master running a Python 3 program,see chapter IV’s radiation tests, specifically 2.5. The Raspberry Pi 3 SoC [135] running Rasp-bian [136] was chosen as a master unit because of its low cost, availability and large numberof open source libraries. After evaluating the results from the radiation tests, a newC++ pro-gram was developed with the hope of improving the measured performance. A simplifiedversion of the C++ program is listed in appendix B. The program uses the bcm2835 library[137] forGPIO-access, the linux/i2c-dev library [138] for I2C communication and the chronolibrary [139] for timekeeping. An Agilent 6705B power supply was used to provide variouscurrents through the SELTC shunt resistors. With exception of this supply, the set-up wasequal to the one shown in chapter IV Fig. 25.The system accomplishes sampling rates of up to 2 kS/s, as shown in Tab. 14. Plots of

sampled sine waves are shown in Figs. 21 and 22. Note that the system in Fig. 22 samples a 1Hz wave at a decreased rate as a result of measuring six channels, as opposed to sampling a 10Hzwave at one channel in Fig. 21. To evaluate the computation time of the I2C readout loop,clock tick usage was measured. A single I2C readout was found to use 20 µs of Rasp. Pi’scomputation time, as shown in Tab. 15. The (through-software) latch-up detection delay,found to be approximately 3 ms, is shown in Tab. 16. Oscilloscope screens displaying thevariation of these measurements are shown in appendix C.

31


Table 14: Sampling rate measurements of the SELTC interfaced by a C++ program running on theRaspberry Pi SoC.

Channels per block Parameter Value Comment

1Mean rate 1.9 kB/s Blocks per secMin delay 0.5 ms Between samplesMax delay 45.5 ms Between samples

2Mean rate 570 B/s Blocks per secMin delay 1.7 ms Between blocksMax delay 33.4 ms Between blocks

6Mean rate 77 B/s Blocks per secMin delay 5.9 ms Between blocksMax delay 90.9 ms Between blocks

Table 15: An I2C read-operation’s CPU usage on the Raspberry Pi SoC measured using ticks.


ttick 1 µ s f = 1 MHzTicks 1952919 N = 100000Ticks ≈ 20 N = 1tµC ≈ 20 µ s N = 1

Table 16: Through-software SEL detection delay measurements of the SELTC.

Data Delay [ms] Equiv. rate [kS/s]

Min 0.5 2.0Mean ≈3 0.34Max 10 0.1

32

4 Results

250 300 350 400 450 5000

200

400

600

800

1000

Time [ms]

Curr

ent [m

A]

Measurement of 0.5A 10Hz sine wave

Figure 21: Plot of a 10 Hz sine wave sampled by the SELTC acquisition of one channel.

1500 2000 2500 3000 3500 4000

0

200

400

600

800

1000

Time [ms]

Curr

ent [m

A]

Measurement of a 0.5A 1Hz sine wave

Figure 22: Plot of a 1 Hz sine wave sampled by the SELTC acquisition of six channels.

33


5 Discussion

In this section various aspects of the circuit are discussed, with an overall aim of giving recom-mendations for future work. As the SELTC also was tested during the radiation tests, resultswill be partially reference to this chapter, specifically chapter IV section 2.5 and 5.

All primary requirements were met by the design. The system removes SELs within mil-liseconds, fulfilling the performance requirement of 100 ms maximum latency. The same istrue for the sampling rate, with 2000 S/s being well above requirement of 100 S/s.Only one of the requirements were not met, namely radiation tolerance. This secondary

requirement is not met because of the prioritised, primary requirement of utilising low cost,readily available components. Following this requirement, all SELTC components areCOTScomponents, of which none are rad-hard [129, 130, 131, 132]. Therefore, one cannot predictthe radiation tolerance of the SELTC system. Utilising the SELTC in mixed-field radiationtest facilities like CHARM [140] may cause single event upsets in the I2C registers of theINA circuits. In turn this may lead to erroneous single event latch-up detection. Assumingthe probability of SEUs in a given environment is low enough, it is advisable to use the threeTMR power lines together with error-correction code.

5.1 Proposals for a Future Circuit

A SEL protection circuit better suited for harsh radiation environments e.g. space or parti-cle accelerators can be developed. Using analogue components, one could create a currentmonitoring circuit with an instrumentation amplifier connected to the shunt nodes. Thereare many such instrumentation amplifiers available [141]. Connecting the amplifier to a rad-hardmaster unit would reduce the risk of SEUs, as opposed to using the digital, COTS INA-circuit. On the other, such a set-up would increase the system cost, and the master wouldhave to contain an ADC. The output of the amplifier would feed the ADC, providing thebasis of a current estimate. Such a systemwould be limited in sampling rate by the ADC andmaster unit.If a current estimate is not needed one could replace the ADC with a rad-hard compara-

tor, whose output would function as a SEL flag, much like the circuit described in chapter V.Given this flag is fed directly to load switches or interrupt pins, it would be possible to detectand remove single event latch-ups with low latency. Low latency SEL removal will reducethe probability of latent damage, found to form as quickly as 16 µs [11]. There are compo-nents available performing these functions [142], but not many are rad-hard [85, 100]. Then-channel load switches of the SELTC could be replaced with p-channel devices. These tra-ditionally carry charges slower than n-channel devices [1], which might give them a higherradiation tolerance. This property of p-channel devices is made evident by the gate-widthoptimisation ofCMOS inverters [143], where the PMOShave up to twice theNMOSwidth-to-length ratio [1].

5.2 Replacing theMaster System

If possible, future systems are recommended to utilise master units running bare metal, low-abstraction programs in order to reduce the risk of damage from SELs. The consequence

34

5 Discussion

of overhead created by e.g. an operating system (OS) may be reduced sampling rate and in-creased latency in the SEL removal. As previously mentioned, latency in SEL removal hasbeen found to cause circuit damage [11].

Using high abstraction languages like Python [144] or Ruby [145] on a SELTC masterunit can cause a slow sampling and SEL detection, as seen in section 5 of chapter IV, werethemean sampling rate was found to increase by a factor of 13 when utilising a C++ programinstead of an equivalent Python program.

The C++ programs of lower abstraction still display a notable variation in sampling rate,even outside writing to file. When the master system runs an OS, in our case a RaspberryPi SoC running Raspbian, it has to perform peripheral housekeeping tasks. The overheadcreated by running an OS is evident when comparing ticks to real-world execution, see Tab.15 of section 4.2. Execution time is approximately 25 times slower than standalone proces-sor computation time. Handling many peripheral functions cause the program to manageits resources, delegating certain time slots to the program. On the other hand, an OS alsosimplifies hardware access and management, making development of programs easier.

5.3 Adjusting theMaster System

There are ways to increase the sampling rate independent of master system, for example util-ising a fast-mode I2C interface with a clock frequency of 400 kHz, not the default 100 kHz[146]. The theoreticalmaximum sampling rate of a looping single channel I2C readout usingthe default 100 kHz clock is 3.7 kS/s, as shown in Eq. 7. Changing the I2C clock frequencyto its maximum, 400 kHz [146], increases this to 14.8 kS/s, as shown in Eq. 8. The I2C spec-ifications of the INA circuit [129] provide the bit-count of this calculation. Note that theserates represent a read with no peripheral code, and therefore the upper limit of SELTC’s sam-pling rate. Also note that INA’s default conversion time of 1.1 ms should be lowered for suchapplications.

fs,max =fclk,I2Cm · n

where n is the number of bits per I2C-read including acknowledge bits,

andm is the number of I2C-reads per sample.

fs,max =100 · 103

1 · 3 · (8 + 1)= 3.7 kS/s when fclk = 100 kHz (7)

fs,max =400 · 103

1 · 3 · (8 + 1)= 14.8 kS/s when fclk = 400 kHz (8)

Another recommendation is to use threads. A sampling rate with lower deviation couldbe accomplishedwith thismodification. Themaximum sampling delay found to be between35 and 45 ms in section 4.2 was caused by periodically writing a buffer to file. In chapter IVsection 2.5 the maximum delay cause by writing to file when running Python was found to

35


be 400ms. These delays could be lowered considerably by performing file-writing in separatethreads, using for example a circular data buffer for data synchronisation.

5.4 Supply Line Resistance

The resistance found through the SELTC, listed in section 4Tab. 11, will cause a voltage dropfrom supply to the DUT, especially during latch-ups or other high current states. Supply ca-bles will introduce similar resistances. A 1 A current through a total of 200 mΩ resistancewill cause a 200 mV voltage drop which might cause the voltage to go below the DUT’s op-erating limits. However, during SEL testing the circuit can remain an idle state, and the re-sulting voltage offset at idle operation be compensated for. Given the main power supplyis connected serially, the master unit may also regulate the DUT supply voltage by utilisingexternal SELTC bus voltage measurements. Proposed measures for lowering the supply lineresistance are listed in Tab. 17.

Table 17: Measures to reduce the supply line resistance of the SELTC.

# Description

1 Use short, low-impedance supply cables to SELTC and DUT.2 Increase the width of SELTC power traces.3 Reduce the length of SELTC power traces.4 Replace headers with smaller, surface-mounted options to reduce PCB length.

5.5 RS485 Connector

The RS485 set-up has not been verified because of damage to the PCB. The characteristicimpedance of the RS485 circuit is slightly mismatched to the Cat 5e cable. A RS485 termi-nation usually has 120Ω characteristic impedance, as opposed to the 100Ω of Cat 5e cables.This may cause decrease in range on account of increased reflections [147]. Given the RS485differential output is matched to 120 Ω [148, 133], one gets the voltage standing wave ratio(VSWR) shown inEq. 9. AVSWRof 1.2 is considered amatch inRF-circuits [147]: aVSWRof 1 is a perfect match and no reflections on the line, while infinite is full mismatch with thewave being reflected. The RS485 set-up should therefore in theory work fine.

VSWR =1 + |Γ|1− |Γ|

where

|Γ| = |ZL − ZS

ZL + ZS| = |100− 120

100 + 120| = 0.091

⇒ VSWR =1 + 0.091

1− 0.091= 1.2 (9)

36

6 Conclusion

6 Conclusion

A current-monitoring circuit with single event latch-up protection capability, named the sin-gle event latch-up test circuit, has been designed, manufactured and successfully verified.The board enables monitoring, handling and logging of single event latch-ups during radi-ation tests. The circuit board fulfilled all of its primary requirements when interfaced by aRaspberry Pi 3 SoC. Further, the circuit has been validated in two radiation test campaigns.The circuit was developed for heavy ion radiation tests, while utilising low-cost components.Consequentially, the circuit should be used in low-radiation environments unless it has beenspecifically tested beforehand. Radiation test facilities where the beam is not confined to theDUT are not recommended. In such environments where SEUs are a concern, the circuitoffers TMR-connected INA-circuits, enabling error correction code. The circuit also imple-ments an adjustable LDO capable of generating voltage as low as 0.8 V, making it possible tostep DUT voltages past the typical CMOS thyristor holding voltage of 1 V [78]. The masterunit of the SELTC is recommended to run a bare metal, low-abstraction program, i.e. a ded-icated micro-controller running a sampling program written in C. The memory unit shouldbe either high-capacity, or external, utilising a separate controller. In such cases, the SELTCshould be capable of sampling currents at rates of up to 15 kS/s, with SELs removed as fast as70 µs.

37

IV Radiation Tests

Two radiation tests were performed using the SELTC, with the goals of qualifying version 4of the SAMPA ASIC for ALICE (A Large Ion Collider Experiment) at CERN. A heavy iontest was performed in November 2017, and a laser test in January 2018, covered in sections3 and 4. The test campaigns were lead by Sohail Musa Mahmood, a PhD candidate at theElectronics group atUiO,who also contributed to thedesignof the SAMPAASIC[149, 150].Previous versions of the ASIC had been tested at proton [151, 152] and heavy ion facilities,proving quite sensitive for single event latch-up.

1 Objective

The main objective of this chapter is to validate the SELTC and its performance during radi-ation testing. Secondly, the objective is to document the test methods of each radiation testcampaign. To accomplish this, each radiation campaign will be presented in its own section,containing test objectives, methods, results and discussion.

2 University Test Equipment

The set-up is illustrated in Fig. 23. The set-up for each radiation test was equal if one lookspast the facility equipment. The facility equipment, and any equipment adjustments aredocumented under sections 3.2 and 4.2. The equipment’s main functionality was to moni-tor single event upsets and latch-ups. The 2 systems are explained in detail in the followingsections 2.3 and 2.4. The devices brought to the tests are listed in Tab. 18.

Table 18: University equipment used for SEE tests.

Device Qty. Purpose Comment

PC 2 Monitor SSH to FPGA& SELTCSOC FPGA dev. brd. 1 SEU system Altera Cyclone VASIC test-board 1 Housing Connected to FPGARaspberry Pi SoC 1 SEL system Model 3BSELTC 1 SEL system RS485 not mountedR&SHameg HMP2020 1 Power USB interfaceHameg HM7042-3 1 Power Not used for laser testCustom cable assemblies - Power See section ??

39

IV Radiation Tests

Power supply

R. Pi FPGA

SEL PC SEU PC

DUT BRDSEL TC

Chamber

Vsh[1,2,3,4]

USB

ETH

ETH

P1V7

P5V0

P1V7

P5V0

Figure 23: Block diagram of set-up used for both radiation tests.

2.1 SAMPAASIC

The SAMPA ASIC [149, 150], the DUT of these tests, is produced with a 130 nm TSMCCMOS technology [153], and has an operating voltage of 1.25 V. The ASIC consists of 32channels, each containing a charge sensitive amplifier and 10 bit ADC, followed by a digitalsignal processor with I2C and a scalable low-voltage signalling interface. SRAM circuits areused as memory. The ASIC is a part of the plans for ALICE’s upgrade [154, 155], and isintended as the new front end readout electronics at the Time Projection Chamber as wellas the Muon Chamber. A rule of thumb [30] in these radiation environments, is that singleevent effects can be triggered if a device’s LETthr is lower than 15MeV·cm2/mg.

2.2 SAMPATest-board

The SAMPA ASIC had previously been mounted and wire-bonded on a proprietary test-board, which includes voltage regulators, high-density connectors and mounting holes. Thehigh-density connector is made to interface with a SOC FPGA development board. Thevoltage regulators provide 1.1 V, 1.25 V and 2.5 V to the board, see Tab. 19. The test-boardhas a hole in the PCB, exposing parts of the ASIC substrate. This substrate area contains theassumed sensitive area, allowing for the laser irradiation described in section 4. The DUTtest-board together with the FPGA board is pictured in Fig. 24 from the heavy-ion test.

2.3 Single Event Upset System

The single event upset detection and testing system was also used in previous tests. An SOCFPGAdevelopment boardwas used inside the radiation chamber to communicate with vari-ous registers and modules of SAMPA’s digital circuitry. The SOC FPGA, which runs Linux,was connected to a control computer through an Ethernet switch, and to the DUT board

40


Figure 24: DUT and SOC FPGA boards mounted in the chamber rack during the heavy-ion test.

Table 19: Voltage regulation on the SAMPA test-board.

Board input ASIC rail

1.7 V 1.25 V digital-”- 1.25 V analogue-”- 1.10 V ADC-reference5.0 V 2.50 V FPGA-interface

through a high-capacity I/O-connector. The SOC can run various programs to test circuitrywithin the chip, some utilising GUI software [156]. Tab. 20 lists the different single eventupset test programs, and their effect on the digital supply line’s idle current draw.

2.4 Single Event Latch-up System

The single event latch-up system consisted of the single event latch-up test circuit controlledby a the Raspberry Pi SoC (Rasp. Pi) running Python, which in turn was connected via SSHto a PC functioning as monitor and storage. The monitored shunt resistors were connectedexternally, behind the test-board’s regulators. The Rasp. Pi ran a Python program to logcurrent and bus voltage. The program is copied and modified from one used in previousSAMPA radiation test campaigns [151, 152], originally developed by the bachelor studentFredrik Winje. Limited time before the radiation testing was an argument for keeping thehigh-abstractionPythonprogram. Therewas also a goal of keeping the test system equivalent

41

IV Radiation Tests

Table 20: Difference in idle current draw during SEU tests performed the SAMPA v4 digital supplyline.

# Description Idig

0 Idle current ≈ 380 mA1 Built-in memory test ≈ 580 mA2 Shift-register test ≈ 140 mA3 I2C-register test ≈ 380 mA

to that of previous radiation tests. Therefore, the program keptmost of its functionality, likepower supply control and data logging, even though these functions were redundant withthe SELTC. Additions to the original program are listed in Tab. 21. Code from the programrelevant to the SELTC, is listed in appendix D.

Table 21: Modifications done to Python program before performing radiation tests with the SELTC.

# Modification

1 Capability to log data from several channels per I2C address2 Configurable shunt voltage SEL thresholds3 Logging of SELs4 Turning off supply lines a certain duration in case of SEL

2.5 Verification of Latch-up System Before Tests

The single event latch-up system was verified before travelling to the heavy ion test. ThePythonprogram, listed in appendixD, logs results file, orderingdata into timestamped "blocks"containing bus and shunt voltage values from all sampled channels. Test runs of the programwere performed, resulting in the measurements listed in Tab. 22. The test set-up is shown inFig. 25. The Rasp. Pi ran via SSH, with program and log-files located in a mounted folder.The program sampled the bus and shunt voltages of four channels, as per the intended set-upused for the heavy ion radiation test. The mean sampling rate was measured from the totalnumber of data blocks and elapsed time. Each block contain four channels of shunt and busvoltage measurements, equalling 12 · 4 · 2 = 96 bit of raw data per block. These are quiteslow sampling rates, and could allow for damage to the circuit. However, the previous ver-sion of the SAMPA ASIC (SAMPA v2 ) was found to survive prolonged periods latch-up,indicating a prolonged delay like 400 ms does not cause permanent damage to the circuit.

In order to ensure the correct supply voltages were delivered to the device, a test was per-formed using the expected cabling of the heavy-ion facility, as mentioned in section 3.2. Thetest resulted in a calculated supply resistance of approximately 270 mΩ on the supply side,and 210 mΩ in the return path. Especially the BNC feed-through of the heavy-ion chamberadded to the already mentioned 70 mΩ resistance of the SELTC. A proprietary supply cablemade for the SELTC, shown in Fig. 26, added 45 mΩ. Tests showed this total resistance was

42


still acceptable, as the test-board regulators kept the voltage somewhat stable in all states ex-cept running of the built-in memory test, where it had to be adjusted to 1.75 V due to thevoltage drop.

Table 22: Sampling rate using Python to log shunt and bus voltages of four SELTC channels.


Mean rate 7.1 B/s Blocks per secMin. delay 111 ms Between samplesMax. delay 400 ms Between samples

Figure 25: Set-up of functionality tests of the SELModule.

Figure 26: Custom long length cable made for the SELTC’s outputs.

43

IV Radiation Tests

3 Heavy ion SEE test of the SAMPAASIC

This section documents the objectives, methods, and results related to the SELTC from theheavy-ion radiation test performed atUniversité catholique de Louvain (UCL) inNovember2017. With the new version of the SAMPAASIC one expected the high single event latch-upsensitivity of previous version to be mitigated.

3.1 Objectives

Theobjective of the heavy-ion testwas to qualify version 4of the SAMPAASIC (SAMPAv4)for operation in ALICE, with regards to both single event upsets and latch-ups. A previousversion of the SAMPA ASIC was also brought to the test, with the intention of verifyingprevious test results with the new single event latch-up system.

3.2 Facility Equipment

The heavy ion facility (HIF) at UCL contains a cyclotron irradiating a radiation chamber op-erated at vacuum [157], and thus it was built with a cable feed-through. The near-vacuumpressure ensures low energy loss during travel from cyclotron to DUT, increasing accuracyof the energy approximations. The test set-up had to be adjusted for this cable feed-through,see section 3.3. The cable feed-through as well as the mounting rack could be easily accessedby opening the vacuum chamber, as shown in Fig. 27. The chamber and cyclotron was con-trolled by an operator, while a LabVIEWHTMLwindowdisplayed beamproperties like ionelement, ON/OFF, flux, reached fluence, LET and incident angle. The heavy ions that wereavailable [56] are shown in Tab. 23.

Table 23: Available particle cocktails at the UCLHIF.

M/Q Ion Energy [MeV] Range [um Si] LET [MeV/mg/cm2]

3.25 13 C 4+ 131 269.3 1.33.14 22 Ne 7+ 238 202.0 3.33.37 27 Al 8+ 250 131.2 5.73.33 40 Ar 12+ 379 120.5 10.03.31 53 Cr 16+ 513 107.6 16.03.218 58 Ni 18+ 582 100.5 20.43.35 84 Kr 25+ 769 94.2 32.43.32 103 Rh 31+ 972 88.7 45.83.54 124 Xe 35+ 995 73.1 62.5

3.3 Adjustments to University Equipment

The single event latch-up test circuit supply channel set-up is shown in Tab. 24. The mainsupply lines which kept the ability to power cycle are marked "main". "External" indicateexternal shunt measurement, and that the internal resistor is disconnected.

44

3 Heavy ion SEE test of the SAMPA ASIC

Figure 27: Vacuum chamber at the UCLHIF.

AcustomDSUB25-cable was used between the SELTC test-board, to connect the externalshunt nodes through the chamber feed-through shown in Fig. 28. The shorter supply cableswere used from power supply to SELTC, as these were close to each other on the test bench.The longer, three-phase cables were used from SELTC to DUT board. This longer supplycable was connected to a banana-to-BNC converter before being fed through the vacuumchamber, and inside the chamber BNC-to-test-board cables were used.

In addition to these adjustments, a power resistor and one-wire temperature sensor wasbroughtwith, in order to regulate andmeasure the test-board temperature. SohailMahmoodwrote a logging-program for the sensor, which was to run on the Rasp. Pi of the single eventlatch-up system.

Figure 28: The UCLHIF vacuum chamber’s connector panel.

45

IV Radiation Tests

Table 24: Setup of the SELTC during heavy-ion test.

I2C Address Ch. Bus Shunt [mΩ] Note

0x40 1 1.25 V None External 50mΩ0x40 2 1.10 V None External 50mΩ0x40 3 1.25 V None External 50mΩ0x41 1 1.70 V main 100 Internal0x41 2 2.50 V None External 100mΩ0x41 3 5.00 Vmain 0 Nomeas.

3.4 Method

The radiation test facility was operated by an on-site operator. Once the different boards andsystems were connected and mounted, one specified the wanted ion, flux and fluence. Theoperator went across the lab to change the ion, and after around ten minutes the cyclotronwas ready. After turning it on, it ran until the specified fluence was achieved. One couldalso stop it manually at any time. The single event upset system ran its various tests, whilethe single event latch-up system monitored the supply line continuously. The test-board’swere one at a time, as changing would require pumping the vacuum chamber in addition tochanging board and reconnecting cables.

The heavy ion radiation test startedwith chromium-53 at anLETof 16MeV·cm2/mg, andincreased iteratively to the maximum LET of 62.5 MeV·cm2/mg using xenon-124. Tiltingwas performed in an attempt to increase the effective LET to 125MeV·cm2/mg. In addition,attempts were made to increase temperature and supply voltage, to increase the potentialsingle event latch-up cross section. In case no SEL was found, the focus would be on singleevent upsets and finding its threshold and saturation cross sections. If there was extra timeavailable after both single event latch-up and single event upset tests, the previous version ofthe SAMPAwould be tested, enabling comparison of data with previous campaigns.

3.5 Results

The new version of the SAMPA chip proved immune to SEL at the highest LET energiesavailable atUCL.Tilting theDUT and increasing temperature to 87 Cdid not trigger latch-ups. It was deemed too time-consuming to increase the supply voltage in an controlled way,as the test-board regulator were not characterised for this beforehand. Most of the currentslogged by the SELTC looked like the plot in Fig. 29, where the circuit was irradiated withxenon-124 at an LET of 62.5 MeV·cm2/mg. However, there were some oddities in the datalogged. The 2.5 V supply line experienced a slight current increase of a 3 mAwhen the beamwas turned on, and decreased back to its initial value when the beam was turned off, whichmight indicate collected charges from the ionisation. However, the 2.5V supply line is for thetest-board components interfacing the SEU-system’s FPGA, andnot relevant for the SAMPAASIC. In addition, the digital 1.25 V supply line’s current draw seemed to alternate between388mA and 408mA as shown in Fig. 30. The I2C-register test was being run during the runplotted in this figure. The variation seems almost digital, like a square pulse, and might be a

46


single event effect of some kind. During this test run, the current alternates 28 times. If thisis a single event effect, it yields the cross section shown in Eq. 10.

σ(LET ) =nSEE

F=

28

10022635= 2.79 · 10−6 cm2 ± 18.9 % (10)

100 200 300 400 500 600 7000

100

200

300

400

Time from beam start [s]

Curr

ent [m

A]

Log of parameter during beam

Ch. 1.1 current

Ch. 1.2 current

Ch. 1.3 current

Ch. 2.2 current

Figure 29: Plot of the SAMPA v4 current draw during xenon-124 irradiation ions. Supply lines fromtop to bottom: test-board 2.5 V, digital 1.25 V, analogue 1.25 V, ADC-reference 1.10 V.

The previous version of the ASICwas irradiatedwith an LET of 16MeVcm2/mg and fluxof 21 particles/cm2s. There was only time for one full run at this energy, and the SAMPA v2ASIC experienced single event latch-up 34 times, yielding the cross section 4.05 · 10−3 cm2

found in Eq. 11. Note that this ASIC seemed to be damaged, as it was not possible to com-municate with it and the idle current sometimes short-circuited after reset. For the durationof this test run however, the idle current seemed to stay stable after reset. The full resultsand parameters are listed in Tab. 25. The low sampling rate allowed the current rise beyondthe set threshold within one sample, and consequentially there is some uncertainty to themeasurements of latch-up formation time, current slope andmaximum current. Plots of thedigital supply current are shown in Figs. 31 and 32.

σ(LET ) =nSEE

F=

34

8398= 4.05 · 10−3 cm2 ± 17.1 % (11)

47

IV Radiation Tests

100 150350

360

370

380

390

400

410

420

430

440

450


Cu

rre

nt

[mA

]

Log of parameters during beam

Ch. 1.3 current

Figure 30: Plot detail of the SAMPA v4 2.5 V supply line current during xenon-124 irradiation.

110 120-200

0

200

400

600

800


Cu

rre

nt

[mA

]


Ch. 1.3 current

Figure 31: Plot detail of the SAMPA v2 digital supply line current during chromium-53 irradiation.

48


Table 25: Results from heavy-ion test of the SAMPA v2 ASIC.


Events 34 Registered SELsMean off-time 1.2 s ± 0.2 sFlux 21.25 p/s Low valueBeam time 436 sFluence, raw 9265 p Logged by facilityFluence 8398 p Subtracted off-timeσ 4.05· 10−3 cm2 Excl. counting errorσe ± 17.1 % Counting error: Ch. II Sec. 7.2tformation 110 ms - 180 ms Based on 6 samplesdidt 1.4 A/s - 2.3 A/s Based on 6 samplesimax 650 mA Based on 6 samples

0 50 100 150 200 250 300 350 400 450-200

0

200

400

600

800


Cu

rre

nt

[mA

]


Ch. 1.3 current

Figure 32: Plot of the SAMPA v2 digital supply line current during chromium-53 irradiation.

49

IV Radiation Tests

3.6 Discussion

The single event latch-up cross section found in this test campaign is 22 percent larger thanthe one previously found1 at the same LET (and facility), however the analysis of the previ-ous test results is not finished. The deviation of the two measurements can be caused by thecounting error of 17 percent. In addition, the fluence and beam energy calculations of thefacility have an unknown uncertainty. It is worth noting that only one LET was tested, sothe value might deviate from an expectation value. The execution of off-time by the SELTC-based system is also uncertain, as the sampling rate of the program is the basis of the time-keeping. If the off-time time fluence is not removed from this tests calculations, the deviationis reduced to 10 percent.

Another ground for scepticism in the cross section calculation is thementionedASICdam-age, seemingly affecting the current draw and digital functionality. It seemed the ASIC wassomewhat stable during the test run, as seen in Fig. 32, where the idle current deviates amaximum 50 mA from the normal draw. However, the ASIC might have reset into a high-current state registering as a latch-up. Also, the ASIC operated at shorted currents whenverifying it before the test run. These shorted currents cause temperature to rise, increasinglatch-up cross section with it. The origins of this damage could be damage to wire-bondsunder transport, or latent damage from previously experiencing latch-ups. The ASIC hasbeen irradiated with heavy-ions several times, and as result of this internal conductors mighthave shorted partially as a result of high-temperatures. This was previously mentioned inchapter II section 7.6. As the idle current was unstable, the latch-up threshold was increased,increasing the latency of latch-up removal, which in turn worsens such latent damage [11].The Python program’s low sampling rate has some consequences for the data. The off-

time at the supply-line experiencing latch-up ends up with quite low precision. The pro-gram should have probably shut off all channels and gone into a timekeepingmode. Instead,the Python program samples the other channels while the latched channel off and checkingthe elapsed time each iteration. The low sampling rate, and thus low precision of the off-time made it necessary to use low flux values. 15000, 10000 and 5000 particles/cm2s createdevents quicker than the system could mitigate, meaning the precision of the off-time wouldbe decisive for the resulting cross-section’s uncertainty. This is of course worsened by testinga circuit of such high sensitivity. The low sampling rate also makes it hard to measure thelatch-up formation characteristics precisely. The latch-up currents measured rose from idleto latched within one sample. The formation and rise times reported in section 3.5 are there-fore at the mercy of the mean sampling rate. It is hard to define a maximum latch-up currentallowed by this system, for example if the latch-up response of the SAMPA ASIC was of aneven higher rise time, the maximum current would also be larger.

1Priv. communication, Sohail Mahmood, February 2018.

50

4 Laser SEE test of SAMPA ASIC

4 Laser SEE test of SAMPAASIC

This section documents the objectives, methods, and results related to the SELTC from thelaser radiation test performed in January 2018.

4.1 Objectives

The main objective of the test was to precisely locate the SEL-sensitive areas of the previousSAMPA ASIC version (v2), as well as finding single event upset and latch-up laser energythresholds. The present version of the SAMPA ASIC (v4) was also to be tested for singleevent upset and latch-up. It was expected that single event upsets would be induced in bothASICs, while single event latch-up was only expected in SAMPA v2.

4.2 Facility Equipment

The Institut d’electronique single-photon laser facility at Université de Montpellier (UM)was used for this test. The facility has a laser radiation test system provided by Pulscan calledPulsys [158]. The system is shown in the pictures of Fig. 34. This system was used for infra-redmappingof theDUT’s substrate, laser irradiation, and automatic scansbasedon the infra-redmap. It containsmicroscopes, amotorizedmounting rack, a laser source and is controlledby a GUI control-program [158]. The GUI program is shown during an automatic scan inFig. 33. The system uses a 3.3 V, active low trigger signal to detect events. The incidentenergy on theDUT is calculated by the systemwith an accuracy of±5 percent. The durationof automatic scans correlate with pulse frequency, step size, and scanning area, but not theevent flag as the system is capable of receiving delayed trigger signals. Therefore, the singleeven latch-up detection does not have to be as quick as the laser pulse frequency. How thesystemaccomplishes this is unknown, itmight retrace its steps according to the delay to rescanareas were the ASIC was latched.

Figure 33: The control GUI of the Pulsys laser system.

51

IV Radiation Tests

Figure 34: The irradiation chamber of the Pulsys laser system.

4.3 Adjustments to University Equipment

The connection between the Rasp. Pi and SELTC was changed to a flat-cable, utilizing the3.3 V from the Rasp. Pi for SELTC’s main supply. The LDO on board was used for powerregulation from 5 V to 1.7 V, meaning only one output was used from the main power sup-ply. Unlike the heavy-ion test, the temperature was not measured. As a result of these twochanges, only one power supply was needed. The SELTC set-up is shown in Tab. 26. Themain supply lines which kept the ability to power cycle are marked "main". "External" indi-cate external shunt measurement, and that the internal resistor is disconnected. In order tointerface the laser system, a trigger output indicating a single event latch-ups was added. Thistrigger was to be used as the basis of the operator’s monitoring as well as the event flag of theautomatic scan.

Table 26: Set-up of the SELTC for the laser test campaign.

I2C Address Ch. Bus Shunt [Ω] Note

0x40 1 1.25 V None External 50mΩ0x40 2 1.1 V None External 50mΩ0x40 3 1.25 V None External 50mΩ0x41 1 2.5 V None External 100mΩ0x41 2 5 Vmain 0 Feed-through0x41 3 1.7 V main 0 Feed-through

4.4 Voltage Regulation Characterisation

The test-board’s post-regulator voltage was characterised in order to control the voltage lev-els delivered to the DUT. The measurements aimed to map LDO-setting to DUT supply

52


voltage. A selection of the resulting regulation settings are listed in Tab. 27. There is littledeviation between the bus voltagemeasured by SELTC’s INA-circuits and the supply voltagemeasured at the test-board. The column “LDO setting” display bits of the respective DIP-switch positions: 0V8, 0V4, 0V2, 0V1, and 0V05. A value of one indicates connection toground, and an addition to the minimum output voltage of 0.8 V. Each test-board’s regula-tion was different, so the boards were independently characterised, with tables for idle andhigh current draws (represented by the built-inmemory test). The SAMPAASICwas foundto be dysfunctional when the supply voltage was below 0.95 V.

Table 27: Typical LDO settings for varying DUT supply during laser irradiation.

LDO setting LDO output INA bus DUT supply

10010 1.70 V 1.29 V 1.27 V10001 1.65 V 1.29 V 1.27 V10000 1.60 V 1.28 V 1.26 V01111 1.55 V 1.26 V 1.25 V01110 1.50 V 1.24 V 1.23 V01101 1.45 V 1.20 V 1.20 V01100 1.40 V 1.16 V 1.16 V01011 1.35 V 1.12 V 1.12 V01010 1.30 V 1.09 V 1.08 V

4.5 Attempts to Find the Sampling Rate Bottleneck

Before the laser tests, the single event latch-up detection delay, and thus sampling rate wasthought to limit the duration of the automatic scans. According to the operator this wasnot the case with the Pulsys system. However, the program was experimented with to findpossible bottlenecks restricting the sampling speed of the program. Different functions wereremoved, and sampling rate evaluated, resulting in Tab. 28. None of the functions resultedin a notably higher sampling rate when removed. It is reasonable to conclude the main causeof the low sampling rate is the Python interpreter, the Rasp. Pi’s OS tasks and/or the I2CPython-functions. It seems the only effective way to increase the sampling rate would be todevelop a program in a language like C++, but there was not enough time to implement sucha program before the test.

4.6 Method

The laser system was set to parameters showed in Tab. 29 and 30. To find the beam param-eters suitable for the ASIC, information on substrate thickness (175 µm) and its expectedsingle event latch-up saturation cross section was given to the laser system operator. The op-erator was an engineer from Pulscan. The SELTC system was utilised for indicating SELs,acting as a flag during automatic scans as well as signalling the operator duringmanual scans.

53

IV Radiation Tests

Table 28: Sampling rate after emitting various functions from the Python program.

Function removed Sampling rate [Blocks/s] Exclude?

None 7.35 NoThreads merged ≈7.5 NoThread for supply ≈7.5 NoSEL counting ≈8.5 NoKeyboard control ≈8 No

Table 29: Laser system beam parameters used during ASIC irradiation.


Pulse duration 30 ps Standard for SPA SEE testWavelength 1064 nm Standard for SPA in siliconRepetition rate 2 Hz to 100 Hz Laser pulse frequencySpot size 1.2 µm± 0.2µm 100X lensPulse energy 32 pJ to 1.035 nJ Incident DUT energy

4.7 Results

The SELTC indicated single event latch-ups in the expected circuit structure of SAMPA v2.No other areas of either the v2 or v4ASICwere found to be sensitive to single event latch-up.The single event latch-up thresholds are listed in Tab. 31. The lowest energy listed for the v2pedestal memory indicates latch-ups were not found, while the largest energy indicate theenergy at which latch-ups were still found. The energy threshold Eth is most likely withinthese values. To find the lowest possibleEth, the precision and perseverance of the operatorwas crucial. As the absorbed energy drops, so does the cross section, making the sensitive areadifficult to locate. The lowest SEL Eth value took minutes to find. The pedestal memorycircuit had some peripheral circuitry which was not sensitive.

Using empirical data of latch-up thresholds from the laser test and previous heavy ion test2

of the v2, it is possible to approximate theLETconversion factor relating incident laser energyand heavy ion LET for the SAMPA v2 circuit. The formula is shown in Eq. 12. The LETthreshold of the previous circuit was an approximate, with the cross section at this LET-value about 8000 times smaller than at saturation. Using this value and the 124 pJEth,laser

listed in Tab. 31, the ion-to-laser conversion factor of SAMPA v2 is found to be 37.6 pJ perMeV·cm2/mg, as shown in Eq. 13.

2Priv. communication, Sohail Mahmood, February 2018

54


Table 30: Laser system parameters used during automatic irradiation scan of the SAMPAASIC.

Parameter Value

Laser pulse frequency 10 HzStep length 1 µmSpot size 500 nm - 1 µmScan area 40 µm by 20 µmIncident energy 131 pJ - 1035 pJ

Table 31: Single event latch-up thresholds found during laser irradiation of SAMPAASICs.

Circuit Block Parameter Value Comment

Pedestal memory v2 SELEth 117 pJ - 124 pJ Manual scanData memory v2 SELEth > 690 pJ No SELs foundPedestal memory v4 SELEth > 1035 pJ No SELs found

Eth,laser = A · LETth,ion (12)

A = Eth,laser/LETth,ion

A =124 · 10−12

3.3 · 106A = 37.6 pJ per MeV·cm2/mg is the ion-to-laser factor (13)

Two automatic scans were donewithin a selected area of the SAMPA v2 pedestal memory,by utilising the SELTC to indicate SELs. The area is shown in Fig. 37. The first scan had aspot size of 1 µm, and is shown in Fig. 35, the second scan had a spot size of 500 nm, and isshown in Fig. 36. The scan with 1 µm spot took approximately 13 minutes, while the scanwith 500 nm spot took approximately 1 hour and 30 minutes.Inorder to see the effect of varying the supply voltage, the latch-up thresholdof the SAMPA

v2 pedestal memory was measured with 3 different LDO settings. The results are shown inFig. 38. During these tests the thyristor holding voltage was found to be between 1.14 V and1.10 V, as no single event latch-ups were recorded at 1.10 V.

55

IV Radiation Tests

Figure 35: Laser irradiation scan of the SAMPA v2 sensitive area. 1 µm resolution.

Figure 36: Laser irradiation scan of the SAMPA v2 sensitive area. 500 nm resolution.

56


Figure 37: Substrate location of the SAMPA v2 automatic scans.

1.12 1.14 1.16 1.18 1.2 1.22140

145

150

155

160

165

170

175

VDIG Supply [V]

Incid

en

t L

ase

r E

ne

rgy [

pJ]

PEDMEM SAMPA v2 SEL Energy Threshold

Figure 38: Single even latch-up threshold of the SAMPA v2, plotted against supply voltage.

57

IV Radiation Tests

4.8 Discussion

The change in supply voltage showed correlationwith single event latch-up theory: the latch-up sensitivity’s scaling downwith supply voltage, and the effect of going below the thyristor’sholding voltage. The thyristor voltage was found to be between 1.10 V and 1.14 V, and as doc-umented in section 4.3 the ASIC still functioned down to 0.95 V. One should attempt oper-ating between these values, for example at 1.05 V, considering the high sensitivity of the olderSAMPA version. However, as a general recommendation one should not use the SAMPAv2 at neither such operating voltages nor in harsh radiation environments. Using the ASICat low operating voltages can cause timing errors, while a harsh radiation environment cantrigger micro latch-ups or other radiation effects not found by these tests.

During the laser radiation tests, it was expected that theEthwould increase if the substratesurface had scratches and impurities. These impurities cause laser diffraction and reduce ab-sorbed energy within the substrate. The surface of SAMPA v2 was dirtier than SAMPA v4.The dirtiest spots found are shown in Fig. 39 and 40. However, no significant differencewerefound within identical memory circuits of the two SAMPA versions. The surface might nothave been dirty enough to see these effects.

Figure 39: Substrate surface of SAMPA v4. Figure 40: Substrate surface of SAMPA v2.

58

5 A Note on the System’s Sampling Rate

5 ANote on the System’s Sampling Rate

The effect of the low sampling rate on test measurements was previously discussed in section3.6. Tab. 28 documented ineffective attempts at increasing the sampling rate of the Pythonprogram. The fact that none of these changes saw a change in sampling rate indicate the issuelies within the abstraction, and maybe the Python interpreter.

For future tests using the single event latch-up test circuit, it advisable to use either a low-abstraction language and/or dedicated master unit with no peripheral tasks, as previouslyrecommended in chapter III section 5. To compare the Python program used in these testswith a functionally equivalent C-language program, the program listed in appendix E wasdeveloped. This program is similar to the SELTC benchmarking program from chapter IIIsection 4.2. However, it implements no buffer and a 4-channel readout like the Python pro-gram. This program is not totally equivalent, though, as it does not interface a power supplyserially. The C++ program proved to be around 13 times faster, referenced to the verificationof the Python program in section 2.5. The results are shown in Tab. 32.

Table 32: SELTC performance comparison of Python and equivalent C++ code.

Parameter Value, C++ Value, Python Comment

Mean rate 90 B/s 7.1 B/s Blocks per secMin. delay 8 ms 111 ms Between samplesMax. delay 34 ms 400 ms Between samples

In hindsight, one can see solutions to increase the sampling rate that should have beentested. For example a data buffer to reduce the number of file-writing operations, as writ-ing to file is generally resource-heavy. Another possibility is to sacrifice supply lines that areobserved to not experience latch-up, and only sample the ones that do.An increased time resolution might enable capturing latch-up formation signatures. Cur-

rent samples might then be used for pattern recognition, and given repeating latch-up pat-terns the system can be used for prediction, maybe lowering detection delay.

6 Conclusion

The radiation tests produced satisfying results, both in terms of SAMPA’s response to radia-tion and SELTC’s role as a single event latch-up testing circuit. The heavy-ion test validatedthe SAMPA ASIC for the ALICE radiation environment, while the laser test confirmed thecircuit area sensitive to single event latch-up. The laser test proved especially useful by con-firming single event latch-up theory in regards to thyristor holding voltage, and dependenceon supply voltage. Both tests validate of the SELTC as a single event latch-up test circuit.The utilisation of a Python program running in Raspbian OS on a Raspberry Pi proved theSELTC can be useful even when controlled by quite slow master units.

59

V IDE3466’s Latch-up Protection

The IDEAS IDE3466ROIC (Readout Integrated Circuit) [159, 160] contains a circuit mod-ule intended for detecting single event latch-ups, called the Single Event Latch-up DetectionModule (SELDM).This specific integrated circuitmodule is characterised in section 4. In ad-dition, the circuit is tested with a new program enabling current measurements using simpleinterface electronics in section 5.

1 Objective

The objective of this work is to evaluate the functionality and performance of the SELDMas an integrated solution for single event latch-up protection. Beyond verification tests, anexperimental program is developed and tested to examine the flexibility of the circuit. Theaim of this experiment is to show that iteratively finding the supply line current is possibleby utilising the SELDMand its SPI interface. In addition to complementing the comparisonwith the SELTCof chapters III and IV, such current samplingmakes it possible to determinethe correct latch-up threshold by measuring the idle current.

2 The IDE3466 ROIC

TheSELDMis implemented as a part of the IDE3466ROIC. IntegratedDetector ElectronicsAS (IDEAS) is a company located inOslo,Norway, specialised in front-end, ROICs for harshradiation environments. IDEAShas developed and verified [160] the IDE3466ROIC for theRad-Hard ElectronMonitor (RADEM) of ESA’s Jupiter IcyMoons Explorer (JUICE) [161].Themain applicationof the IDE3466 circuit is readout of siliconparticle detectors [159, 160].It contains 36 channels for this purpose, each consisting of a charge sensitive amplifier and22-bit particle counters. The ROIC also allows for analogue pulse-height spectroscopy. Particlecounters and other registers are interfaced through SPI. The ROIC was produced at AMSin a 0.35µm CMOS process, and implements guard rings on an epitaxial wafer1 to preventsingle event latch-up. The bare die is pictured in Fig. 41. The predecessor to the IDE3466is the IDE3465 [162]. More information of the IDE3466 ROIC can be found in Stein et al.[160].

2.1 IDE3466 SEL DetectionModule

Part of the IDE3466 project requirements was a circuit made for detecting latch-up eventson the ROIC supply line. JUICE [161] shall explore the Jovian system and will therefore en-

1IDE3466 Datasheet [159], available upon request.

61


Figure 41: The bare IDE3466 die.

counter the Jovian radiation environment. On its way it will travel [163, 161] through Earth’sradiation belts, the Venusian radiation environment, and interplanetary space. All these en-vironments contain particle populations capable of inducing single event latch-up amongmany other radiation effects, with the Jovian environment being especially harsh [164]. Thisis due to Jupiter’s strong magnetosphere, which causes its radiation belts to extend to it’smoons [165, 166]. One can expect the IDE3466ROIC to be immune to latch-up, on the basisofusing adesign librarypreviously radiation tested forheavy ionLETsup to 136MeV·cm2/mg[92, 93]. The IDE3466 itself will be radiation tested at a heavy-ion facility later in 20182.

The SELDM circuit has two channels, each containing a difference amplifier, followed bya comparator. The comparator reference is set by a 5-bit DAC which again is set by a SPIregister. A circuit diagram is shown in Fig. 42. The outputs of the comparators (LU1, LU2)act as SEL flags. The outputs are also routed through an OR-gate, providing a global latch-up pin (GLU). The circuit is intended for high-side shunt resistor current measurement, onthe IDE3466 digital and/or analogue 3V3-supply. The internal circuitry is powered by thepositive "SELA" input pin, limiting it to 3.3V. A typical application is shown in Fig. 43.The circuit should enable low-latency SEL removal, considering it is analogue from SELDMinputs to comparator output. The expected circuit parameters3 from design and simulationare listed in Tab. 33.

Table 33: IDE3466 SELDM circuit parameters expected after simulation and design.

Parameter Value Source

DAC LSB 3.2 mV Design documentCload 20 pF -”-Ibias 10 µA -”-tdetection <4 µs -”-Psupply 1.65 mW -”-Isupply 500 µA -”-

2Priv. communication, Dirk Meier, March 2018.3Priv. communication, Amir Hasanbegovic, March 2018

62

3 Common Equipment

DAC

SPI

Diff. Amp.

SELB1

SELA1 Comp.

OR

LU1

GLU

THR1[4:0]

LU2SELB2

SELA2

Figure 42: Circuit diagram of the IDE3466 SELDM.

3V3

LoadSwitch

SELA

SELB

LU

DetectionModule

Microcontroller

I/ORsh

ZL Rpd

Figure 43: Block diagram of a typical SELDM application.

3 Common Equipment

The equipmentusedduring thiswork is listed inTab. 34. NIRCAandRADEMare acronymsfor ESA projects where IDEAS has developed ROICs, and test-boards with these names areused for IC verification. The RADEM test-board contains a wire-bonded IDE3466, and isshown connected to the LabFEC and Raspberry Pi 3 SoC (Rasp. Pi) in Fig. 44. The test-board together with the LabFEC provide circuit connections, in order to simplify poweringand interfacing the IDE3466.

63


Table 34: Test equipment used for work with the IDE3466 ROIC.

Device Purpose

IDEAS IDE3466 DUTRaspberry Pi 3 SoC SPI masterNIRCA LabFEC InterfaceRADEMTest-board ROIC& peripheralsPC Rasp. Pi master through SSHAgilent 6705B Power supplyRIGOLDS1052E Oscilloscope

Figure 44: IDEAS laboratory equipment used to interface the IDE3466. 1: LabFEC board, 2: powersupply, 3: cable for LU-flag, 4: cable for SPI, 5: Pi, 6: SELA and SELB connection, 7:RADEM test-board with ROIC.

64

4 Tests of the IDE3466 SELDM


In this section methods and results from tests of the SELDM are described.

4.1 Method

The tests performed are listed in Tab. 35. The objective of this work is to explore the usecases of the SELDM. The circuit parameters found are measured on one circuit. The testsof the circuit’s functionality and parameters were done to increase understanding and easedevelopment. The SPI program developed to verify circuit functionality is listed in appendixF. The programwas also used to set the SPI-defined latch-up thresholdwhenmeasuring SPI-to-output delay. The Raspberry Pi 3 SoC was used as the SPI master.

Table 35: Tests performed on the IDE3466 SELDM.

# Description

1 General circuit functionality tests2 Indirect characterisation of DAC3 Input-to-output signal propagation delay4 SPI-to-output delay

The DAC was characterized by applying a regulated current through the RADEM test-board shunt resistor R28, nominally 220 mΩ. The shunt voltage was measured at the RA-DEM test-board header J3. With a latch-up threshold set through the SPI register SELTHR(address 0x181), the latch-up-flag output LU1was observed for changes. Manually increasingthe current, each DAC step’s flagging current was measured for both low-high and high-lowLU transitions, to account for hysteresis. Together with the step number and shunt voltage,the supply current is used as basis for the measurements. The supply was set to source 3.3V at SELA (positive, high-side node), while it was set as a regulated sinking current at SELB(negative, low-side node). This set-up enabled a regulated current value through the shuntresistor, while supplying the internal circuitry through SELA.

SPI-to-output delay was measured by changing the SPI latch-up threshold register to avalue that would trigger the LU-flag. The LU output and SPI CLK were monitored whilethe SPI operation was executed, by connecting input and output to the RIGOL DS1052Eoscilloscope. The last bit is written to the SPI register at the last rising edge of the SPI CLK.

For measuring input-to-output delay timing, stimuli were applied to a shunt voltage in-put of the circuit, while LU was monitored for value changes. The input stimuli connectedto the SELB input were current step pulses set by the sink power supply. The SPI-definedcomparator threshold was set to step 1, while the current increased from 0 to 300 mA. Bothchannels were tested, as well as the OR’ed GLU. Note that the GLU output is buffered atthe RADEM test-board.

65


4.2 Results

Delaysmeasured are listed inTab. 36. Note thatGLUoutput is buffered at theRADEMtest-board. Oscilloscope measurements used as the basis for these results are shown in appendixH. A selection of the characterisation values measured using the internal DAC are listed inTab. 37. Linear regression was performed to find the step voltage (shunt voltage versus step),as well the shunt resistance (shunt voltage versus sinked supply current). The step shuntvoltage linear regression also yielded the DAC bias voltage via the offset. See Figs. 45 and 46.An example of current ranges with the step voltage found in these measurements and theexpected step voltage are shown in Tab. 38. The DAC measurements are listed in appendixI.

Table 36: SELDM detection delay measurements. Output τ denotes the time constant of the digitaltransition.

Input Output Delay [µs] Output τ [µs]

SELB1 LU1 ≤ 2.0 ≈ 0.3SELB2 LU2 ≤ 2.0 ≈ 0.3SELB1 GLU ≤ 1.0 < 0.01SELB2 GLU ≤ 1.0 < 0.01CLK LU1 ≤ 1.7 ≈ 0.3

Table 37: Selection of IDE3466 SELDM characterisation values.

Parameter Value # of data points Comment

Vstep 3.0 mV 64 Linear regressionVbias 1.65 mV 32 LU: high-low (incremental)Vbias 1.30 mV 32 LU: low-high (decremental)Iseldm 470 µA 32 (ISELA − ISELB)Rsh 220.2 mΩ 64 Linear regressionRsh,3.2mV 235.0 mΩ 64 Assuming 3.2mV steps

66


0 100 200 300 400 5000

20

40

60

80

100

Sinking Current [mA]

Sh

un

t V

olta

ge

[m

V]

Step current mapping of the IDE3466 SEL DM DAC

Incremental

Decremental

Slope fit, incremental: a = 0.22019, c = -0.00008

Slope fit, decremental: a = 0.22023, c = 0.0001

Figure 45: Plot of shunt voltage versus supply sink current at each DAC step.

Table 38: Current ranges of various shunt resistors, using the step voltagemodel found through linearregression, and the simulated DAC step voltage.

Model [mV] Rsh [mΩ] Imin [mA] Istep [mA] Imax [mA]

3.0·step + 1.65150 33 60 1893100 16.5 30 946.5200 8.3 15 473.3

3.2·step50 0 64 1984100 0 32 992200 0 16 496

67


0 5 10 15 20 25 30 350

20

40

60

80

100

DAC step

Sh

un

t V

olta

ge

[m

V]

Step voltage mapping of the IDE3466 SEL DM DAC

Incremental

Decremental

Slope fit, incremental: a = 2.998, c = 1.6506

Slope fit, decremental: a = 3.000, c = 1.2972

Figure 46: Plot of shunt voltage versus DAC step.

68

5 Tests of the SELDM Application

5 Tests of the SELDMApplication

This section documents test methods and results related to the experimental application ofthe SELDMas a current-sampling circuit. This application is beyond the circuit the intendedarea of use. The work in this section is therefore purely experimental.

5.1 Method

A C++ program was written to use and test the SELDM circuit as a current measurementdevice. The code of the finished program is listed in appendix G. The bcm2835 library [137]is used for interfacing Rasp. Pi’s SPI and GPIO, while the chrono library [139] is used fortimekeeping. The general functionality of the program is shown in Fig. 47’s flowchart. Fig.48 shows a single "incremental" for-loop used to determine the current. Note that the lu[1]-variable is used to detect a falling edge at the LU-flag, as it stores the value read in the previousiteration.

Init- SPI- GPIO- File

IncrementalLoop[32 steps]

Iincr =

mapincr[step]

DecrementalLoop[32 steps]

Idecr =

mapdecr[step]

I =(Iincr + I

decr)/2

SEL?

Filewrite

GPIO fag

Yes

No

bufer loop

step loop step loop

bufer loop

while loop

Figure 47: Flowchart describing the C++ pro-gram.

Initfound = 0lu[0] = 1thr = 0

SPI writeThr = i

Shift lulu[1]=lu[0]

SPI writeThr = i

Delay uC1 us

Read lulu[0] = gpio

lu[0] != lu[1]

I = current[i]

for loop( i = 0; i < 32; i++)

Figure 48: Flowchart describing a single incre-mental loop within the C++ program.

The program relies on the results from section 4.2. As the main objective of the programwas to measure current, the conversion from binary value (DAC step) to current was per-formed at each sample. The "step-to-current"map, defined from the data in Fig. 45, was used

69


for this purpose, as it was found to have the lowest error, see Tab. 39. By taking advantageof the comparator’s hysteresis, a lower error than the expected 3.1 percent was accomplished.The DAC’s output was stepped through in both an "incremental" (low-high) and a "decre-mental" (high-low) fashion while reading the LU-flag at each iteration, as shown in Fig. 47.The currents found drawn from the maps are averaged into the final sample. The programcan also calculate current usingothermethods, such as using a linear fit between shunt voltageand DAC step. Another possibility is to use only one loop, and applying the correspondinglinear fit to estimate the current. TheDAC step from one loop can also be defined as the out-put, turning the progarm into a quasi ADC. The evaluated alternative methods (and theirmeasurement deviation) are listed in Tab. 39. The deviation is calculated between sampledcurrent and supply current "sinked away" from the SELB node.

Table 39: The IDE3466 SELDMalternative application’s currentmeasurement deviation. DAC stepsare denoted as s, shunt voltage slope as a, and shunt voltage bias as c.

Calc. method Loops Deviation Data points Comment

(min[s]+mde[s])/2 Both 2.5 % 34 m: current mapmin[s] One 3.3 % 18 Incr. loopa1·s Both 6.3 % 30 a1 = 3.0mVa2·s Both 3.4 % 30 a2 = 3.2mVa1·s+c1 Both 2.9 % 30 a1 = 3.0, c1 = 1.474Direct step One 3.13 % - Expected error of LSB

Parameters usedwhen running the program for these tests are listed inTab. 40. In additionto being based on the measurements of section 4.2, some are based on trial and error. Forexample, the SPICLKwas expected tohave anupper limit of 2.5MHz4, butwas found to stillfunction at 16MHz. Thebuffer lengthwas chosen tobe2000 samples, causing approximately40 ms delay every 475 ms. By increasing the buffer length to 16000 samples a delay of 310ms occurred after approximately 3200 ms. The mean sampling rates of the two set-ups wereapproximately equal. Therefore, a buffer of 2000 samples was chosen to lower themaximumdelay. A shorter delay is beneficial when monitoring SEEs, because of its stochastic nature.Fig. 49 displays the periodic delay caused by writing the buffer to file. The smaller spikes ofthis plot are most likely caused by the printing of data at the terminal.

Table 40: Parameters utilised in the IDE3466 SELDM application.

Parameter Value Effect Comment

SPI CLK 16MHz Increase S/s Higher than expectedBuffer N = 2000 Increase S/s Fewer file-writes"cout" interval N = 80 Readability fcout ≈ 2HzDelay 1 µs Correct LU-read Ref. Tab. 36

4Private communication, Amir Hasanbegovic, March 2018

70


0 500 1000 1500 2000 2500 3000

0

10

20

30

40

Time [ms]

Tim

e D

iffe

ren

ce

[m

s]

Delay between samples

Figure 49: Plot of sample delay caused by writing buffered data within the SELDM application.

The tests done to benchmark the SELDM application are listed in Tab. 41. Resource-usage measurements were performed to analyse the processor resources the program uses.The current sampling data was used to analyse the system’s real world performance, as well asto debug while developing the program. The same set-up was utilised for the measurementsof current data as in the DAC-test of section 4.1. In this case, the sinking output was setas a sine-curve of varying frequency. Timing test were performed to measure the latch-updetection delay through software. The result would provide basis for comparison of latch-up detection in software and hardware. The set-up and input stimuli of the delay test wasequal to the delay test of section 4.1. The time difference is measured from shunt currentjump to Rasp. Pi output signal indicating a latch-up.

Table 41: Tests performed to benchmark the SELDM current-logging application.

# Description

1 Deviation of current measurement2 Current sampling data analysis3 Resource-usage measurement using ticks4 Through-software latch-up detection delay

71


5.2 Results

The final program is capable of measuring currents with sampling rates of up to 5 kS/s, lead-ing to through-software SEL detection delays below 1 ms. See in Tab. 42. Plots of a 100 Hzsine wave of 150 mA amplitude and 150 mA offset sampled by the SELDM application areshown in Figs. 50 and 51. Fig. 52 shows an interval of data where the data buffer is writtento file. The idle time interval corresponds with the expected 40 ms listed in Tab. 42, as wellas the testing done previously in section 5.1. Oscilloscope measurements used as the basis forthe through-software delay are shown in appendix H Fig. 59.

Table 42: Current-logging application performance measurements


Samling rate ≈ 4.6 kS/s Average valueSample delay, max ≈ 40 ms Equiv. 25 S/sSample delay, min ≈ 190 µs Equiv. 5.26 kS/s(seconds pr tick 1 µs fclk = 1MHz)Ticks both loops 197 Incr. & decr.Ticks per buffer 427516 ≈ 214 per sampleSW detection delay ≈ 270 µs Equiv. 3.7 kS/s

405 410 415 420 425 430

0

50

100

150

200

250

300

Time [ms]

Curr

ent [m

A]

Effect of using 2 loops

Current, mean

Incr.

Decr.

Figure 50: Plot showing incremental, decremental and averaged current calculated by the SELDMapplication.

72


405 410 415 420 425 430

0

50

100

150

200

250

300

Time [ms]

Curr

ent [m

A]

Effect of rolling average

Current, mean

7 pt. average

Figure 51: Plot showing effect of using rolling average on data from the SELDM application.

400 450 500 550

0

1

2

3

4

5

Time [ms]

Fre

quency [kH

z]

Effect of sampling frequency on data

400 450 500 550

0

50

100

150

200

250

300

Curr

ent [m

A]

Figure 52: Delay caused by writing to file in the SELDM application, at approxiamtely 440 ms.

73


6 Discussion

In this section results from both sets of work are discussed: section 4’s measurements of theSELDM in its intended configuration, as well as the experimental work of section 5 utilisingthe SELDM beyond its intended application.

6.1 The IDE3466 SELDM

The SEL detection delay through the SELDM is approximately 2 µs. This is equivalent to,ormaybe even better than one of the few comparablemarket offerings, the 3DPlus LatchingCurrent Limiter (LCL), which offers a delay of 10 µs or less [100]. Using a buffer to reducethe load impedance of the LU-flag was found to halve the detection delay to 1 µs. Eitherway, the SELDM provides instant SEL detection well within the 60 µs Becker [11] foundempirically to be the minimum formation time of SEL damage.

It is worth noting the delay measurements might have been even lower had the test set-up been improved. As visible from appendix H’s figures, the square current pulse output ofthe power supply has a significant time constant caused by inductance and capacitance in thevarious connections. The values stated here are based on the worst-case starting point of thepulse. Therefore, an ideal pulse might have produced an even lower delay. The simulatedcircuit predicted a delay less than 4 µs, see Tab. 33. The measured 2 µs verified this valuewith a 2 µs margin.The current drawn by the SELDMwasmeasured to be 470µA.This is close to the resolu-

tion of the measurements, 10 µA. The simulation of the SELDM circuit predicted a 500 µAcurrent draw as shown in Tab. 33, meaning the value differs by 6 percent. Considering theresolution of the measurement cause a 2 percent error in itself, one can conclude the currentdraw is verified.

The DAC within the SELDM was designed for 3.2 mV steps. This step value displayedthe smallest deviation of the measurements listed in Tab. 39 (disregarding offsets). One canconclude the measurements verify the DAC LSB value.

6.2 Remarks on the SELDMMeasurements

It is worth mentioning that the DAC is only indirectly characterized, as the data analysedwas from the comparator output and/or amplifier input. The DAC output is not available,and neither is the amplifier output. The exact amplifier input voltage is not known either.The amplifier’s input pins and measurement probes seemed to be connected to the samepoint on the RADEM test-board, and the lines seemed to run parallel with little differencein length. However, one cannot know the input voltage of the amplifier without measuringon the IC pads or internally on the chip. The resistance it connects to on the supply linemight be slightly higher than the 220 Ω seen at the probes. This is also indicated by the235 Ω shunt resistance calculated assuming the DAC LSB voltage is 3.2 mV, see Tab. 37.Another possibility is the input conductors being of slightly different impedance, causing animbalance in the voltage drop, changing the voltage from the shunt.Using linear regression, the offset of the DAC steps were found be 3.0 mV with either a

1.65 mV or 1.30mV, representing high-low and low-high transistions respectively. However,

74

6 Discussion

using 3.0 mV by itself as a basis of estimating the current leads to a deviation larger than 3.2mV. Implementing the offset, the deviation of the 3.0 mV LSB value is lower than 3.2 mV,indicating the DAC might have been designed with a 3.0 mV LSB, while the comparatoradds offset to the LU-output, resulting in 3.2 mV being the correct LSB value. However,these measurements are close, as the 3.2 mV led to a 3.4 precent deviation while the 3.0 mV+ offset led to 2.9 percent. Both numbers are calculated from the same step data, and bothdisplay little deviation from the expected error of the LSB, 3.13 percent.

6.3 The IDE3466 SELDM as a part of the RADEM Instrument

The RADEM instrument will use the SELDM tomonitor the IDE3466 supply lines. Usingthe SELDM in a self-monitoring fashion places some demands on the circuit. The latch-upremovalmust happen before a high-temperature state is reached. The latch-up detection andflagging happens fast given properly defined thresholds, but the latch-up removal happensexternally. In addition, one cannot know the speed at which a single event latch-up reachesa destructive state within the circuit, or if it reaches it at all unless tested. The conductorswithin some parts of the circuit might be dimensioned in such a way that a high-temperaturestate is reached instantly. According to Becker’s experiments [11], damage from single eventlatch-up can form as quickly as 60 µs. Given the design library used for the IDE3466, onewould expect no latch-ups to occur at all. The IDE3466 radiation tests to be performed laterthis year will conclude whether or not the ROIC is single event latch-up sensitive. If it is,then one needs to take the circuit-specific single event latch-up characteristics into accountwhen designing a protection circuit, such that the system is capable of removing the latch-upbefore the IDE3466 is damaged.

6.4 The SELDM Experimental Application

The SELDM detection delay rely on a precise SEL threshold. Measuring the idle current ofthemonitored circuit can be performed by utilising the experimental SELDMapplication ofsection 5. If only one channel of the SELDM is utilised for SEL detection, the other can beused together with the program as a current sampling circuit, enabling measurements at 4.6kS with a deviation of 2.5 percent.

The different offsets found for low-high and high-low transitions when characterising theDAC confirm the comparator has a hysteresis. This ensures stable operation, as the sameinput signal cannot cause different output states. Utilising this feature, currents could beestimated with a lower deviation than the 3.13 percent that is expected from a 5-bit measure-ment, as previously described in section 5.1, namely 2.5 percent. However, this decrease indeviation is not significant. The deviation could have been lower if the hysterisis was larger.The voltage difference of the SELDMhysteresis, 0.35 mV, is approximately the difference ofthe two offsets found with linear regression, as shown in Eq. 14. The theoretical deviationof this hysteresis when utilised in the dual-loop is shown in Eq. 15. With a hysterisis closerto one half of the DAC step, the DAC steps of the two transitions (low-high and high-low)would be evenly spaced along the shunt voltage axis. It should then be possible to accom-plish close to 6-bit resolution, which could lower the minimum deviation to 1.57 percent, asshown in Eq. 16.

75


a1 · s+ c1 = 3.0 + 1.65

a2 · s+ c2 = 3.0 + 1.30

⇒ Vh ≈ | c2 − c1 | = 0.35mV (14)

Vh

a=

0.35

3.0= 0.117

σhyst = σlsb − σlsb ·Vh

aσhyst = 2.76 % (15)

where

σexp,lsb = 3.13%

Vh,half

a= 0.5

⇒ Vh,half = 1.5mV

⇒ σhyst,half = 1.57 % (16)

If the sampling rate of the program is the primary concern, and not the resolution, oneshould use for one loop instead of two. A sampling rate of 8.9 kS/s was accomplished whenmeasuring with one incremental (high-low transistion) loop, which is 1.93 times faster thanthe 4.6 kS/s accomplished using two. A measurement error of 3.13 percent should be ex-pected with this method.

6.5 Proposals for the SELDM Experimental Application

The delay caused by the writing to file can be solved in similar ways as those mentioned inchapter III’s discussion. The program can be implemented using two threads, using a circularbuffer to store the data and the extra thread for writing this buffer to file, the sampling rateshould stabilise at a higher value. It would also be possible to program twomicro-controllersrunning bare metal programs for each of these tasks, connected to the same memory. Itshould then be possible to achieve a mean sampling rate of 5 kS/s, the maximum samplingrate found with today’s solution, or even 10 kS/s if using only one incremental loop.

It is also possible to use the system in a more ADC-like fashion, only extracting the stepfound as a digital value. This will increase the sampling rate, as conversion from DAC valueto current is no longer required. t would be possible to compare the system to other ADCs.If the system had dedicated data treatment as mentioned above, the mean sampling rate of5-bit (one loop) measurements would be increased to approximately 10 kS/s. Using bothdirectional loops, a quasi 6-bit measurement sampled at 5kS/s would be feasible. However,using the SELDM as an ADC is beyond its intended use. By attempting to sample current athigh sampling rates, one could encounter metastability and other issues [167].

76

6 Discussion

By using the SPI bit count, 32, and the SPI CLK, 16 MHz, it is possible to calculate thetheoretical maximum sampling rates based on the SPI transaction, as shown in Eqs. 17 and18. These results represent the maximum sampling rates of the double loop and single loop(m = 64 andm= 32) programs, measured at 5 kS/S and 10 kS/s when running the peripheralapplications on top. The equations show what is the limit when operating like an ADC at a16 MHz SPI clock, if no issues like metastability are met.

n ·m · fs,max = fspi,clk

32 ·m · fs,max = 16 · 106

⇒ fs,max =16 · 10632 · 64 = 7812.5 S/s where m = 64 (17)

⇒ fs,max =16 · 10632 · 32 = 15625 S/s where m = 32 (18)

where n is the number of bits per SPI-write,

andm is the number of SPI-writes per sample.

6.6 Comparisons with SELTC

The single event latch-up detection delay of the discrete component-based SELTC is a far cryfrom that of the SELDM.The difference is approximately that ofmicroseconds andmillisec-onds. As the two SELDM input nodes draw little current, one can expect only a small dropin the supply line voltage. In these aspects, the SELDM is a lot better than the SELTC.It may be more interesting to evaluate the performance of the two circuits when sampling

current. Both circuits were interfaced by a Raspberry Pi 3 SoC running a C++-program inRaspbian. The SELDM-based measurements are about twice as fast when sampling oneshunt resistor, and if only one loop is used, it is about 4 times faster, with a mean of 8.9 kS/scompared to 1.9 kS/s for the SELTC. However, the SELTC samples with 12 bits and a two’scomplement, more than doubling the resolution of the experimental SELDM-based system.Choosing between a quasi 6-bit 4.6 kS/s, or 5-bit 8.9 kS/s to a 12-bit 1.9 kS/s system is notclear cut, and depends on the user’s need. One should also recall that the SELDM circuit wasnot designed current measurement, only SEL detection.It is reasonable to think that the SELDM program will scale to several channels propor-

tionally, given the channels are connected to the same SPI-core. Using the IDE3466 GLUoutput, the loopwould only have to run oncemore per channel, as the address is within eachSPI write. Given several circuits are available on the same SPI-connection, the sampling ratecan be derived from dividing the one channel sampling rate on the wanted number of chan-nels. Note that IDE3466 hosts two SELDM circuits. At least, one can assume the SELDMapplication would would scale better than the I2C-based SELTC application. As a result ofthe overhead of the I2C-protocol [129], new SELTC channels reduce the sampling rate sig-nificantly: from 1.9 to 0.57 kS/s when increasing from one to two channels within the sameI2C readout chip, as shown in chapter III section 4.2.

77


6.7 The IDE3466 SELDM as a Circuit Offering

The work of this chapter verify the intended function of the IDE3466 SELDM as a latch-up detection circuit for the RADEM instrument. In addition, the work show the circuit isapplicable as a current measurement system. However, if the SELDM is to be produced asits own ASIC or intellectual property (IP), it should see some modifications.

The main supply pin would be disconnected from the SELA input and to an indepen-dent ASIC pad. This would mean the circuit is independent of the bus voltage present atthe shunt resistance, as the difference amplifier should ideally not be affected by it. Supplylines of higher voltage, like those present in satellite systems using solar arrays, could then bemonitored by the circuit.

The difference amplifier’s output should be routed to a separate ASIC output. This ana-logue output (relative to the gain) can be sampled by the external system as fast as it is capable.

Another recommendation for a standalone ASIC is to implement more channels. Thiswould make it possible to measure shunt resistances distributed various locations within alarger system. This should work fine as long as the 2 conductor lines are kept equal length,minimising differences in the line resistance. It should be possible to implement 4, 8 or 16channels without it noticeably increasing the size of the packaged chip.

The defining factor in terms of board area would be the number of external componentsrequired. Today’s circuit implements a SPI interface, setting the latch-up threshold by us-ing a SPI register and a DAC. This could be modified and added to the new SELDMASIC,meaning few peripheral components are needed, only the shunt resistors and possibly loadswitches. Another alternative is to use an external resistor to set the comparator thresholdreference. This might be in series with an internal voltage divider. Using such a solutionwould make the chip easier to use, but increase the required circuit area.

The LU-flag’s 20 pF capacitive load, shown in section 2.1 Tab. 33, could be lowered todecrease the output’s rise time, as a lower parallel capacitance should lower the time constant.Another way to decrease rise time is to buffer the LU-flag output with voltage followers, aswas done on the RADEM test-board for the GLU-flag.

One should also evaluate whether or not to add load switches internally. This will causethe the supply line to travel via the ASIC before or after the shunt resistor. The specificationsof the power switch would limit the supply line range. In addition, the requirement to routevia the SELDM would make it difficult to use it for measurement distributed throughouta system. However, it would simplify development for the customer, and make it possibleto determine the complete latch-up removal delay. In the case of using an integrated loadswitch it should be considered to use an integrated shunt resistor as well, as this would sim-plify development further. The previously mentioned 3D Plus Latching Current Limiter[100] implements both of these features, and is one of the few commercially available cir-cuits within this field. Tab. 43 shows a comparison of the present SELDM and the 3D PlusLCL.

One of the SELDM’s most important features as a single event latch-up monitor is its in-herent radiation hardness. Consequentially, the results of the IDE3466 radiation tests per-formed later in 2018 are pivotal, not only for theRADEMmission, but also for the prospectsof a dedicated latch-up detection ASIC or IP.

78

7 Conclusion

Table 43: Comparison of the 3D Plus LCL and the IDEAS IDE3466 SELDM.

Function LCL SELDM

Detection flag ! !

Detection delay < 10 µs > 1 µs

Adj. threshold ! !

Threshold resolution 100 mA Self-defined

Regulated supply ! xShunt resistor Internal ExternalLoad switch Internal External

SPI threshold x !

Ext. res. -”- ! x

RHBD ! !

RHBP ? !

SEL LETthra 80Mev·cm2/mg 136Mev·cm2/mg

aSELDM value based on previous tests of the IDEAS design library [92, 93]

7 Conclusion

The IDE3466 SELDM has proven to be a useful circuit in itself. Its basic functionality pro-vides single event latch-up detection and possibly removal within microseconds. Comparedto the SELTC, this shows the advantage of using a comparator based integrated circuit forlatch-up detection. Interfacing the circuit is easy as-is, and using a controller system it is pos-sible to program the SELDM as a circuit monitor functioning similarly as the SELTC, andwith comparable performance. This current sampling applicationmakes it possible to deter-mine the idle current draw, and set a threshold value that ensures fast acting latch-up detec-tion. However, it should be noted that using the SELDM to measure current is beyond itsintended use, enabled by the experimental work of this thesis.The 2-channel SELDM running the current logging application can be connected in par-

allel to one shunt, using one channel for current sampling and the other for low-latency latch-up detection. If a standalone integrated circuit is made, the application areas can be extendedfurther. It is possible to create a low-power device capable of measuring on a wide range ofsupply lines simultaneously. This IC can be used as the main single event latch-up detec-tion device of a bigger system, with shunt resistors distributed throughout. The latch-upthreshold can be implemented either with a similar SPI-core as today’s solution, or externalresistors setting the comparator input through an internal voltage divider. There are few cir-cuit’s made for rad-hard single event latch-up protection in today’s market, and the few thatare present show that there is room for competitors to satisfy market needs.

79

VI Conclusion

The work of this thesis provide a perspective on single event latch-up protection circuits.The variety of circuitry related to on-site single event latch-up protection is shown throughimplementation and validation of solutions utilising circuit-boards and integrated circuits.In addition, the work covers two radiation campaigns conducted by the writer and SohailMahmood. These radiation test campaigns qualified a previously latch-up sensitive ASICfor the upgrade of the ALICE detector at CERN, using the single event latch-up test circuitdeveloped as a part of this thesis. In addition to providing valuable test results for CERN,these campaigns validate the design of the test circuit. As a last piece of work, the IDE3466ROIC and its module made to detect single event latch-ups on the ROIC’s supply line hasbeen verified by performing new laboratory measurements. The IDE3466 is to be used inthe upcoming JUICE mission to Jupiter’s harsh radiation environment, meaning this singleevent latch-up detection circuit’s correct function can be quite important. The work of thisthesis contribute to this end, as well as expanding the circuit’s functionality to include char-acterisation of idle current draw and setting the latch-up threshold, even logging the currentin-flight.

81

A SELTC Layout and Schematics

This appendix contains layout and schematics made for the first version of the SELTC

83

A SELTC Layout and Schematics

84

B C++ Program for SELTC Testing

This appendix contains a listing of the C++ programmade run on the Raspberry Pi to inter-face the SEL Test Circuit.

#include <unistd.h> // Needed for I2C port#include <fcntl.h> // Needed for I2C port#include <sys/ioctl.h> // Needed for I2C port#include <linux/i2c−dev.h> // Needed for I2C port#include <stdio.h> // Needed for printf#include <stdint.h> // Needed for fixed−width integers#include <sys/time.h> // Needed for calendar time type#include <chrono> // Needed for system timer access#include <ctime> // Needed for chrono’s ::now timer access#include <fstream> // Needed for writing to file#include <iostream> // Needed for cout#include <bcm2835.h> // Needed for GPIO BCM2835/Pi access. Locally installed library.using namespace std;

int main()

int file_i2c, length;int16_t readout;int32_t i;int buffer[60] = 0;int buffer_size = 2000;double shunt_voltage[buffer_size] = 0;

int sel = 0;double sel_time = 0;double off_time = 100;int sel_check = 1;double current_limit = 20; // mA limit

ofstream logfile;

timeval startup;tm * start_local;char start_string[32];double timer[buffer_size] = 0;

//−−−−− START−TIME OF PROGRAM−−−−−

gettimeofday(&startup,NULL);start_local = localtime(&startup.tv_sec);strftime(start_string, 32, "%a, %d.%m.%Y %H:%M:%S", start_local);

//−−−−− OPEN FILE ANDWRITE HEADER −−−−−

logfile.open("log.txt", ios::trunc);logfile

<< "Starttime: " << start_string << "\n"<< "Frequency of clock: " << chrono::high_resolution_clock::duration::period::den<< "\nTime [ms]\tShunt voltage [V]]\n";

logfile.close();

//−−−−− INIT uC −−−−−

if ( !bcm2835_init() ) printf("bcm2835_init() failed, did you run as root?\n");bcm2835_gpio_fsel( RPI_GPIO_P1_26 , BCM2835_GPIO_FSEL_OUTP ); // Physical output pin # for software SEL detection (CE1)

//−−−−− OPEN THE I2C BUS −−−−−

char *filename = (char*)"/dev/i2c−1";if ((file_i2c = open(filename, O_RDWR)) < 0)

//ERROR HANDLING: you can check errno to see what went wrongprintf("Failed to open the i2c bus");return 1;

int addr = 0x41; //<<<<<The I2C address of the slaveif (ioctl(file_i2c, I2C_SLAVE, addr) < 0)

printf("Failed to acquire bus access and/or talk to slave.\n");

91

B C++ Program for SELTC Testing

//ERROR HANDLING; you can check errno to see what went wrongreturn 1;

//−−−−− WRITE BYTES−−−−−

// Setting addressbuffer[0] = 0x01;length = 1; //<<< Number of bytes to writeif (write(file_i2c, buffer, length) != length) //write() returns the number of bytes actually written, if it doesn’t match then an error occurred (e.g. no response from

→ the device)

/* ERROR HANDLING: i2c transaction failed */printf("Failed to write to the i2c bus.\n");

//−−−−− READ BYTES−−−−−

length = 2; //<<< Number of bytes to readauto tp1 = std::chrono::high_resolution_clock::now(); // Reference timepointwhile(1)

for ( i = 0; i < buffer_size; i++ )

if (read(file_i2c, buffer, length) != length) //read() returns the number of bytes actually read, if it doesn’t match then an error occurred (e.g. no response→ from the device)

//ERROR HANDLING: i2c transaction failedprintf("Failed to read from the i2c bus.\n");

else

auto tp2 = std::chrono::high_resolution_clock::now();std::chrono::duration<double, std::milli> interval_ms = (tp2− tp1);timer[i] = interval_ms.count();readout = buffer[0];readout = ( ( readout & 0xFF00 ) >> 8 ) | ( ( readout & 0x00FF ) << 8 );shunt_voltage[i] = ( ( readout & 0x7FF8 ) >> 3 ) * 0.00004;bcm2835_delayMicroseconds(1);

if( sel_check == 1 )

if( ( (1000/0.1114)*shunt_voltage[i] > current_limit ) && ( sel == 0 ) )

sel = 1;sel_time = timer[i];

if( ( sel == 1 ) && ( ( timer[i]− sel_time ) < off_time ) )

bcm2835_gpio_set( RPI_GPIO_P1_26 );if( ( sel == 1 ) && ( ( timer[i]− sel_time ) > off_time ) )

sel = 0;bcm2835_gpio_clr( RPI_GPIO_P1_26 );

if( ( i % 40 ) == 0 )

cout<< "Time: " << timer[i]<< "\tVoltage [mV]: " << 1000*shunt_voltage[i] << "\tCurrent [mA]: " << 1000*shunt_voltage[i]/0.1114 << "\r";

logfile.open( "log.txt", ios::app );for ( i = 0; i < buffer_size; i++ )

logfile<< timer[i] << "\t"<< shunt_voltage[i] << "\n";

logfile.close();

92

C OscilloscopeMeasurement of

the SELTC’s Detection Delay

Figure 53: Software single event latch-up detection delay of the SELTC.

93

D Python Application for SELTC

Readout

This appendix contains a shortened listing of the python application used at the radiationeffects tests of chapter IV, as well as in the evaluationmentioned in the same chapter’s section2.5. This listing excludes code used to interface the power supply.

import serialimport timefrom datetime import datetimeimport cursesfrom ina3221 import ina3221import sysfrom threading import Threadimport RPi.GPIO as GPIO # for control of switches on SEL−mon through GPIOimport os # for flush og os.sync (begge for kontinuerlig utskrivning av buffer)

# ==================================================# = INA3221 writer to file =# ==================================================

class ina3221_writer:def __init__(self, address, channels, ina):

self.address = addressself.channels = channelsself.ina = ina#~ self.ina[x].configuration(config)

def writer(self):

try:inn = int(time.time())chmeas = [4]chstat = [2]#~ measurements = [] # this variable was used to test speed of one I2C readout (measurements) per channel instead of two (bus_ & shunt_voltages)bus_voltages = ([],[])shunt_voltages = ([],[])SEL = Falsenumber_of_SELs = ([],[])ina_header = ""single_channel = ""filename_time = time.strftime("%Y−%m−%d%H:%M:%S")filename = "_".join([filename_time,"ina_log.txt"])hfilename= "_".join([filename_time, "hmp_log.txt"])file = open(filename, "a+") #opens writeable filehfile = open(hfilename, "a+") #opens hmp writeable filefor i in range(len(address)):

for j in range(channels[i]):single_channel = "".join(["Bus voltage ", str(hex(address[i])), "−", str(j+1), "[V] ; ", "Shunt voltage ", str(hex(address[i])), "−", str(j+1), "[mV] ;

→ ", "# of SELs ; "])ina_header += single_channelnumber_of_SELs[i].append(0)

file.write(’#%s ; %s ; %s %s ; %s \n’ % (’Time [UTC]’, ’Timer’, ina_header, "ch1 ON/OFF", "ch2 ON/OFF"))hfile.write(’#%s ; %s ; %s ; %s ; %s ; %s \n’ % (’Time [UTC]:’, ’Timer’, ’ch1 voltage [V]’, ’ch1 current [A]’, ’ch2 voltage [V]’, ’ch2 current [A]’))

while True: # main logging looput = int(time.time())diff = ut− innutctime = datetime.now().strftime("%Y−%m−%d%H:%M:%S.%f")[:−4]text = ’%s ; %4d ; ’ % (utctime, diff) #beginning of text string to be written to file

for j in range(len(address)): # Get and treat data for each ina addressbus_voltages[j][:] = self.ina[j].get_bus_voltages(int(channels[j])) # Get bus voltagesshunt_voltages[j][:] = self.ina[j].get_shunt_voltages(int(channels[j])) # Get shunt voltages#~ measurements[:] = self.ina[j].get_measurements(int(channels[j])) # get bus & shunt voltages. 2 lists concatenated as [bus + shunt], so "

→ measurements" is 2*[channels] long

95

D Python Application for SELTC Readout

if auto_off:if SEL:

if (int(time.time())−SEL_start_time) > off_time: # Check if switches have been off for user−defined off−timeGPIO.output(sw_select, 1)SEL = False # If automatic switch−off is enabled, the program will check for SEL and turn of TPS load switches

for k in range(int(channels[j])):if abs(shunt_voltages[j][k]) > shunt_mV_limits[j][k]: # True = user−defined SEL

GPIO.output(sw_select, 0) # Turn off all switches (defined in sw_list)SEL = Truenumber_of_SELs[j][k] += 1 # Increase count of SELs by 1SEL_start_time = int(time.time()) # Counting for user−defined off−time started

else: # Counts SELs if auto_off = Falsefor k in range(int(channels[j])):

if (abs(shunt_voltages[j][k]) > shunt_mV_limits[j][k]) & (SEL == False):number_of_SELs[j][k] += 1SEL = TrueGPIO.output(ttl_trigger, 0) # TTL trigger for laser facility instruments

if (abs(shunt_voltages[j][k]) < shunt_mV_limits[j][k]) & (SEL == True):SEL = FalseGPIO.output(ttl_trigger, 1)

for l in range(len(shunt_voltages[j])):text += ’%3.3f ; %3.3f ; %2d ; ’ % (bus_voltages[j][l], shunt_voltages[j][l], number_of_SELs[j][l])

#~ for l in range(len(measurements)): # this was used to evaluate one i2c readout#~ text += ’%3.3f ; %2d ; ’ % (measurements[j], number_of_SELs[j][0])

chstat = stat()text_display(text + "ch1 %s ; ch2 %s" % (chstat[0], chstat[1])) #display textstring on curser windowfile.write(text + " %s ; %s\n" % (chstat[0], chstat[1])) #write text string to filefile.flush()os.fsync(file)chmeas = meas() #returns hmp2020 measured valueshfile.write(’%s ; %4d ; %s ; %s ; %s ; %s ; \n’ % (utctime, diff, chmeas[0], chmeas[1], chmeas[2], chmeas[3]))hfile.flush()os.fsync(hfile)time.sleep(0.005) #[s] delay

except KeyboardInterrupt:file.closehfile.closepass

# ==================================================# = These lines defines methods to be used for the hmp2020# ==================================================

### LINES EXCLUDED FROM LISTING ###

# ==================================================# = Threads for the two loop programs =# ==================================================def runWriter(address, channels):

# Initialising tps229900GPIO.setwarnings(False)GPIO.setmode(GPIO.BOARD) # Physical pin−numbering usedGPIO.setup(sw_list, GPIO.OUT) # All pins connected to switches are set as R.Pi outputs, sw_list defined in mainGPIO.setup(ttl_trigger, GPIO.OUT) # TTL trigger for laser lab instruments set as R.Pi outputGPIO.output(sw_list, 0) # Disable all switchesGPIO.output(sw_select, 1)

# Initialising ina3221ina = []for i in range(len(address)):

ina.append(ina3221(int(address[i]), False))writer = ina3221_writer(address, channels, ina) #initiates writer class with the list of ina runners and filename to be written to

writer.writer() #starts the writer function in the writer class

def runSerial():### LINES EXCLUDED FROM LISTING ###

# ==================================================# = Main function and where to change inits =# ==================================================if __name__ == "__main__":

# Settings for SEL control on SEL monitor boardsw_list = [18, 22, 29, 32, 31, 33] # Pi GPIO−header physical pin locations of SW enable pinsttl_trigger = 19 # Physical SPI−MOSI pin number, used as ttl_trigger for laser lab isntrumentssw_select = [31,33, 19] # Selection of load switch channels to use, as well as ttl_trigger physical pin

96

shunt_mV_limits = ([18,8,20],[150]) # Shunt (milli)voltage limits for load switch turn off.# PS! The number of limits in the first list must equal the number in channels[1] (below), and so on

auto_off = True # Set true or false for auto offoff_time = 0.1 # Off−time [s] after I>I_limit

address = [64,65] # ina i2c addresses used. 65 = 0x41 => PWR4−6 lines on SEL−monitor. could be "sys.argv[x]" if named as xth argument when calling scriptchannels = [3,1] # could be "sys.argv[x]". Number of ina channels to measure at each address mentioned in "address" => 1 = ch1, 2 = ch1 & ch2, 3 = ch1, ch2 & ch3

# PS! Number of items in "address" list and "channels" (above) list must equal

# Settings for power supply### LINES EXCLUDED FROM LISTING ###

#~ Se fil 2018−01−11 10:18:27 for dette oppsettet:#~ t1 = Thread(target = runWriter(address, channels)) #ina writer#~ t1.setDaemon(True)

#~ Se fil 2018−01−11 10:30:52 for dette oppsettett2 = Thread(target = runSerial) #hmp2020 controller threadt2.setDaemon(True)t2.start()t1 = Thread(target = runWriter(address, channels)) #ina writer

97

E C++ Program for Python

Comparison

This appendix contains a listing of theC++program equivalent to the pythonprogram listedin the previous appendix D. This program was used for evaluation purposes in section 5.

#include <unistd.h> // Needed for I2C port#include <fcntl.h> // Needed for I2C port#include <sys/ioctl.h> // Needed for I2C port#include <linux/i2c−dev.h> // Needed for I2C port#include <stdio.h> // Needed for printf#include <stdint.h> // Needed for fixed−width integers#include <chrono> // Needed for system timer acces#include <ctime> // Needed for converting time to localtime(), and chrono’s ::now timer access#include <sys/time.h> // Needed for high−resolution calendar time#include <bcm2835.h> // Needed for GPIO BCM2835/Pi access. Locally installed library.#include <iostream> // Needed for cout#include <fstream> // Needed for writing to fileusing namespace std;

int main()

const int devices = 2;const int channels[2] = 3, 1;

int file_i2c, length, h, i, j, k;int buffer[60] = 0;int addr;int16_t readout;int buffer_size = 1;

int sel = 0;double sel_time = 0;double off_time = 100; // [ms] off time in case of I>limitint sel_check = 0;//double current_limit = 20; // mA limit

double voltage_shunt[2][3][buffer_size] = 0; // shunt 40 uV => LSBdouble voltage_bus[2][3][buffer_size] = 0; // bus 8 mV => LSBdouble limit[2][3] = // SEL current threshold0.3, 0.3, 0.3,0.4;double shunt_resistance = 0.1114;

ofstream logfile;






<< "Starttime: " << start_string << "\n"<< "Frequency of clock: " << chrono::high_resolution_clock::duration::period::den<< "\nTime [ms]\tB1\tS1\tB2\tS2\tB3\tS3\tB4\tS4\tB5\tS5\tB6\tS6\n";

logfile.close();

//−−−−− OPEN THE GPIO LOAD SWITCH −−−−−

if ( !bcm2835_init() ) printf("bcm2835_init() failed, did you run as root?\n");

99

E C++ Program for Python Comparison

bcm2835_gpio_fsel( RPI_GPIO_P1_26 , BCM2835_GPIO_FSEL_OUTP ); // Physical output pin # for SEL flagging

//−−−−− OPEN THE I2C−1 BUS−−−−−

char *filename = (char*)"/dev/i2c−1";if ((file_i2c = open(filename, O_RDWR)) < 0)

//ERROR HANDLING: you can check errno to see what went wrongprintf("Failed to open the i2c bus");return 1;

auto tp1 = std::chrono::high_resolution_clock::now(); // Reference timepoint

while ( 1 )

for ( h = 0; h < buffer_size; h++ )

auto tp2 = std::chrono::high_resolution_clock::now();std::chrono::duration<double, std::milli> interval_ms = (tp2− tp1);timer[h] = interval_ms.count();for ( i = 0; i < devices; i++ ) // Loop for devices/addresses

//−−−−− OPEN I2C ADDRESS −−−−−

addr = 0x40 + i; //<<<<<The I2C address of the slaveif ( ioctl( file_i2c, I2C_SLAVE, addr ) < 0 )

printf("Failed to acquire bus access and/or talk to slave.\n");//ERROR HANDLING; you can check errno to see what went wrongreturn 1;

for( j = 0; j < channels[i]; j++ ) // Loop for channels at device

for( k = 0; k < 2; k++) // Loop for bus and shunt register readout

//−−−−− WRITE REGISTER ADDRESS POINTER BYTE −−−−−

//Reading alternated between shunt and bus voltage by k, and between channels by jbuffer[0] = ( 0x01 + k ) + ( j*2 ); //0x01 = shunt_ch1 voltage register, 0x02 = bus_ch1 voltage register, 0x03 = shunt_ch2, 0x04 = bus_ch2length = 1; //<<< Number of bytes to writeif ( write( file_i2c, buffer, length ) != length ) //write() returns the number of bytes actually written, if it doesn’t match then an error

→ occurred (e.g. no response from the device)

/* ERROR HANDLING: i2c transaction failed */printf("Failed to write to the i2c bus.\n");

//−−−−− READ REGISTER BYTES −−−−−

length = 2; //<<< Number of bytes to readif ( read( file_i2c, buffer, length ) != length ) //read() returns the number of bytes actually read, if it doesn’t match then an error occurred (e.

→ g. no response from the device)

//ERROR HANDLING: i2c transaction failedprintf("Failed to read from the i2c bus.\n");

else

readout = buffer[0];readout = ( ( readout & 0xFF00 ) >> 8 ) | ( ( readout & 0x00FF ) << 8 );readout = readout >> 3;if ( readout > 0xFFF )

/* Negative value from two’s complement */readout−= 0x2000;

if( k == 0 )

readout =− readout;voltage_shunt[i][j][h] = ( readout * 0.000040 );

else

voltage_bus[i][j][h] = ( readout * 0.008 );

if( sel_check == 1 )

if( ( (1000/0.1114)*voltage_shunt[j][k][h] > limit[j][k] ) && ( sel == 0 ) )

sel = 1;sel_time = timer[h];

if( ( sel == 1 ) && ( ( timer[h]− sel_time ) < off_time ) )

bcm2835_gpio_set( RPI_GPIO_P1_26 );

100

if( ( sel == 1 ) && ( ( timer[h]− sel_time ) > off_time ) )


if ( (h % 4) == 0 )

cout<< "Time: " << timer[h]<< "\tB1: " << voltage_bus[0][0][h]<< "\tS1: " << voltage_shunt[0][0][h]<< "\tB2: " << voltage_bus[0][1][h]<< "\tS2: " << voltage_shunt[0][1][h]<< "\tB3: " << voltage_bus[0][2][h]<< "\tS3: " << voltage_shunt[0][2][h]<< "\tB4: " << voltage_bus[1][0][h]<< "\tS4: " << voltage_shunt[1][0][h]<< "\r";

for ( h = 0; h < buffer_size; h++ )

logfile.open("log.txt", ios::app);logfile

<< timer[h] << "\t"<< voltage_bus[0][0][h] << "\t"<< voltage_shunt[0][0][h] << "\t"<< voltage_bus[0][1][h] << "\t"<< voltage_shunt[0][1][h] << "\t"<< voltage_bus[0][2][h] << "\t"<< voltage_shunt[0][2][h] << "\t"<< voltage_bus[1][0][h] << "\t"<< voltage_shunt[1][0][h] <<"\n";

logfile.close();

101

F IDE3466 SEL DMCharacterization

SPI code

This appendix contains a listing of the code used to characterize the basic circuit functionalityof the IDE3466 SEL DetectionModule.

//−−−−− PROGRAM FOR USING SPI WITH R.PI 3 (MASTER) AND VATA466 (SLAVE)−−−−−

#include <stdio.h> // Needed for printf#include <bcm2835.h> // Needed for SPI HW access#include <sstream> // Needed for convert command line argumentsusing namespace std;

int main( int argc, char* argv[] )

uint16_t i;int limits[] = 0;char32_t spi_address_writebit = 0;char readback[3] = 0;char writeword[] = 0;const uint32_t length = 4; // SPI registers are 4 bytes long

//−−−−− SETUP OF WORD TOWRITEistringstream iss1(argv[1]); // First argument written after ./(...) is used for SELth_1iss1 >> limits[0];istringstream iss2(argv[2]); // Second argument written after ./(...) is used for SELth_2iss2 >> limits[1];

spi_address_writebit = ( (0x185 << 23) | (1 << 22) ) & 0xFFC00000;writeword[0] = ( spi_address_writebit & 0xFF000000 ) >> 24;writeword[1] = ( spi_address_writebit & 0x00C00000 ) >> 16;writeword[2] = ( ( ( limits[1] << 5 ) | limits[0] ) & 0xFF00 ) >> 8;writeword[3] = ( ( limits[1] << 5 ) | limits[0] ) & 0x00FF;

//−−−−− INIT−−−−−

if ( !bcm2835_init() ) printf("bcm2835_init() failed, did you run as root?\n");if ( !bcm2835_spi_begin() ) printf("bcm2835_spi_begin() failed, did you run as root?\n");

//−−−−− SPI SETUP −−−−−

bcm2835_spi_setDataMode(BCM2835_SPI_MODE0); // CPOL = 0, CPHA = 0bcm2835_spi_setBitOrder(BCM2835_SPI_BIT_ORDER_MSBFIRST);bcm2835_spi_setClockDivider(BCM2835_SPI_CLOCK_DIVIDER_256); // 512 = 781.25kHz, 256 = 1.5625MHz (on RPI3 according to lbcm2835 => testing

→ showed 512 = 488kHz, 256 = 980kHz, 128 = 1.92MHzbcm2835_spi_chipSelect(BCM2835_SPI_CS0);bcm2835_spi_setChipSelectPolarity(BCM2835_SPI_CS0, LOW); // Whether the chip select pin is to be active HIGH or LOW

//−−−−− SPI WRITE/READ (FULL DUPLEX) −−−−−

bcm2835_spi_transfernb(writeword, readback, length); // Overwritten value is read out on MISO−line, into "readback" (run 2 times to confirm value)

printf("Writeword to SPI: 0x%X\n",(writeword[0] << 24) | (writeword[1] << 16) | (writeword[2] << 8) | writeword[3]);

printf("readback0: 0x%X\nreadback1: 0x%X\nreadback2: 0x%X\nreadback3: 0x%X\n", readback[0], readback[1], readback[2], readback[3]);

//−−−−− CLOSE CONNECTION−−−−−

bcm2835_spi_end();bcm2835_close();

103

G IDE3466 SELDM Experimental

Application Code

This appendix contains a listing of the code used to approximate current with IDE3466SELDM.

//−−−−− PROGRAM FOR USING SPI WITH R.PI 3 (MASTER) AND VATA466 (SLAVE)−−−−−

#include <stdio.h> // Needed for printf#include <bcm2835.h> // Needed for SPI and GPIO BCM2835/Pi access. Locally installed library.#include <sstream> // Needed for convert command line arguments

// Is sstream really needed? For bcm2835.h functions maybe?#include <iostream> // cout#include <fstream> // Needed for writing to file#include <sys/time.h> // Needed for high−resolution timer containing date etc#include <ctime> // Needed for converting time to localtime()#include <chrono> // Testing new timerusing namespace std;

int main( int argc, char* argv[] )

int limit = 0; // Inital limit written to SELTHR1&2. Between 0 and 31 (DAC 5 bit)int incremental_step, decremental_step, i;int buffer_size = 2000; // 2 full loops: 2000, 1 full loop: 4000, 1 loop w jumpout: 8000int edge_detect[2] = 0;int found_step = 0; // Starting point = 0. Incremental loop iterates from (found_step) for safetyint found_curr = 0;

double shunt_resistance = 0.22;double current_map[2][32] = // Index [0][x]: incremental values. Index [1][x]: decremental values.

0.00482, 0.01930, 0.03340, 0.04755, 0.06157, 0.07569, 0.08945, 0.10345, 0.11731, 0.13135, 0.14505, 0.15890, 0.17286, 0.18633, 0.19983, 0.21352, 0.2272,→ 0.24086, 0.2535, 0.26806, 0.28123, 0.29493, 0.30809, 0.32144, 0.33492, 0.34833, 0.36165, 0.37483, 0.38789, 0.40110, 0.41397, 0.42745,

0.00335, 0.01785, 0.03171, 0.04603, 0.05997, 0.07417, 0.08798, 0.10186, 0.11567, 0.12993, 0.14371, 0.15759, 0.17123, 0.18508, 0.19869, 0.21218, 0.2257,→ 0.23945, 0.2530, 0.26658, 0.27952, 0.29345, 0.30688, 0.32013, 0.33350, 0.34720, 0.36003, 0.37350, 0.38634, 0.39978, 0.41288, 0.42589

;double current[2][buffer_size] = 0;

int sel_check = 0; // Optinal SEL check. Needs variables below declared.int sel = 0;double sel_time = 0;double off_time = 100; // ms off if SELdouble sel_current_thr = 0.2;

char32_t spi_address_writebit;char readback[] = 0;char writeword[] = 0;const uint32_t length = 4; // SPI registers are 4 bytes long

ofstream logfile;






<< "Starttime: " << start_string << "\n"<< "Frequency of clock: " << chrono::high_resolution_clock::duration::period::den<< "\nTime [s]\tI [A]\tI+ [A]\tI− [A]\n";

logfile.close();

105

G IDE3466 SELDM Experimental Application Code

//−−−−− SETUP OF WORD TOWRITE

spi_address_writebit = ( (0x181 << 23) | (1 << 22) ) & 0xFFC00000;writeword[0] = ( spi_address_writebit & 0xFF000000 ) >> 24;writeword[1] = ( spi_address_writebit & 0x00C00000 ) >> 16;writeword[2] = ( ( ( limit << 5 ) | limit ) & 0xFF00 ) >> 8;writeword[3] = ( ( ( limit << 5 ) | limit ) & 0x00FF );

// Word to write to SPI = [address=9bits][Write/NotRead=1bit][Data=22bits]// Data = [12 zeros][SELTHR2=5bits][SELTHR1=5bits], where SELTHR1 is iterated in current loop, and the corresponding LU1 is checked

//−−−−− INIT−−−−−

if ( !bcm2835_init() ) printf("bcm2835_init() failed, did you run as root?\n");if ( !bcm2835_spi_begin() ) printf("bcm2835_spi_begin() failed, did you run as root?\n");

//−−−−− GPIO SETUP−−−−−

bcm2835_gpio_fsel( RPI_GPIO_P1_22 , BCM2835_GPIO_FSEL_INPT ); // Physical input pin # for LU1/2 flag ("BCM25" between SPI CE0 and MISO)bcm2835_gpio_fsel( RPI_GPIO_P1_18 , BCM2835_GPIO_FSEL_OUTP ); // Physical output pin # for software SEL detection ("BCM24", 2 above #22)

//−−−−− SPI SETUP−−−−−

bcm2835_spi_setDataMode(BCM2835_SPI_MODE0); // CPOL = 0, CPHA = 0bcm2835_spi_setBitOrder(BCM2835_SPI_BIT_ORDER_MSBFIRST);bcm2835_spi_setClockDivider(BCM2835_SPI_CLOCK_DIVIDER_16); // See "technical−parameters.txt" for measurements of speedsbcm2835_spi_chipSelect(BCM2835_SPI_CS0);bcm2835_spi_setChipSelectPolarity(BCM2835_SPI_CS0, LOW); // Whether the chip select pin is to be active HIGH or LOW

//−−−−− INITIAL SPI WRITE/READ (FULL DUPLEX)−−−−−

bcm2835_spi_transfernb( writeword, readback, length ); // Overwritten value is read out on MISO−line, into "readback" (run 2 times to confirm value)auto tp1 = std::chrono::high_resolution_clock::now();

//−−−−− LOOP FOR SHUNT MEASUREMENTS−−−−−

while(1)

for( i = 0; i < buffer_size; i++ )

found_curr = 0;edge_detect[0] = 1; // Expect LU1 edge to go from 1 to 0 in incremental loopfor( incremental_step = found_step; incremental_step < 32; incremental_step++)

bcm2835_spi_transfernb( writeword, readback, length );edge_detect[1] = edge_detect[0]; // Shift previous responsebcm2835_delayMicroseconds(1); // Delay 1 us to allow LU1 to settleedge_detect[0] = bcm2835_gpio_lev( RPI_GPIO_P1_22 ); // Read current responseif( edge_detect[0] != edge_detect[1] ) // If LU1 response har changed (from 1 to 0) => current is found

found_curr = 1;current[0][i] = current_map[0][incremental_step];//current[0] = 3*incremental_step; // 3.2 is also experimented with//found_step = incremental_step; // Set found step for next loop’s starting point

// Uncomment for adaptive loop//incremental_step = 32; // Set incremental step to exit loop

// Uncomment for adaptive loopfound_step = 32; // Comment for adaptive loop

else if( (edge_detect[0] == edge_detect[1]) && (incremental_step >= 31) && ( found_curr == 0 ) ) // If no edge is found & we’re at end of loop

found_step = 32;current[0][i] = 0; // Set found_step for decremental_loop

else

writeword[3]++; // If still in loop, increment SPI SELTHR limit

writeword[3] = found_step; // Limit a couple steps above step found at incremental loopedge_detect[0] = 0; // Expect LU1 edge to go from 0 to 1, so default is 0found_curr = 0;

for( decremental_step = found_step; decremental_step >−1; decremental_step−−)

bcm2835_spi_transfernb( writeword, readback, length );edge_detect[1] = edge_detect[0];bcm2835_delayMicroseconds(1); // Delay 1 us to allow LU1 to settleedge_detect[0] = bcm2835_gpio_lev( RPI_GPIO_P1_22 );if( edge_detect[0] != edge_detect[1] )

found_curr = 1;current[1][i] = current_map[1][decremental_step];//current[1] = 3*decremental_step; // 3.2 is also experimented with//found_step = decremental_step; // Uncomment for adaptive loop//decremental_step =− 1; // Uncomment for adaptive loopfound_step = 0; // Comment for adaptive loop

106

else if( ( edge_detect[0] == edge_detect[1] ) && ( decremental_step <= 0 ) && ( found_curr == 0 ) )

found_step = 0;current[1][i] = 0;

else

writeword[3]−−;

writeword[3] = found_step;bcm2835_spi_transfernb( writeword, readback, length );auto tp2 = std::chrono::high_resolution_clock::now();std::chrono::duration<double, std::milli> interval_ms = (tp2− tp1);timer[i] = interval_ms.count();

if( (i % 80) == 0 ) // 2 full loops: To print approximately every 0.5s (div16) set i % 80// 1 full loop: i% 160

cout<< "Time: " << timer[i]<< "\tMean current = " << ( current[0][i] + current[1][i] ) / 2 << "\r";

// SEL check, optionalif( sel_check == 1 )

if( ( current[0][i] > sel_current_thr ) && ( sel == 0 ) )

sel = 1;sel_time = timer[i];

if( ( sel == 1 ) && ( ( timer[i]− sel_time ) < off_time ) )

bcm2835_gpio_set( RPI_GPIO_P1_18 );else if( ( sel == 1 ) && ( ( timer[i]− sel_time ) > off_time ) )


logfile.open( "log.txt", ios::app ); // "reduced filewrite" logfor( i = 0; i < buffer_size; i++ )

logfile<< timer[i] << "\t"<< (current[0][i]+current[1][i])/2 << "\t"<< current[0][i] << "\t"<< current[1][i] << "\n";

logfile.close();

//−−−−− CLOSE BCM2835 CONNECTION −−−−−

bcm2835_spi_end();bcm2835_close();

107

H OscilloscopeMeasurements of

the IDE3466 SELDM

This appendix shows the oscilloscope print-screens used to determine the internal circuitrydelay of the IDE3466 SELDM, as well as the through-software latch-up detection delay ofthe SELDM application.

Figure 54: Propagation delay measured from SELB1 input to LU1 output.

109

H Oscilloscope Measurements of the IDE3466 SELDM

Figure 55: Propagation delay measured from SELB2 input to LU2 output.

Figure 56: Propagation delay measured from SELB1 input to (externally buffered) GLU output.

110

Figure 57: Propagation delay measured from SELB2 input to (externally buffered) GLU output.

Figure 58: Propagation delay measured from SPI CLK input to LU1 output.

111

H Oscilloscope Measurements of the IDE3466 SELDM

Figure 59: Detection delay of the SELDM application’s single event latch-up check.

112

I Measurement Data of the IDE3466

SELDM internal DAC

Table 44 lists all measurement points taken of the IDE3466 SELDMDAC.

113

I Measurement Data of the IDE3466 SELDM internal DAC

Table 44: Shunt voltage and supply current for each IDE3466 DAC step.

StepIncremental (0 ->1) Decremental (1 ->0)

ISELDM [A]Voltage [mV] Sink [A] Source [A] Voltage [mV] Sink [A]

0 1 0.00482 0.6 0.00335 -0.004821 4.1 0.01930 0.0198 3.8 0.01785 0.00052 7.2 0.03340 0.0339 7.0 0.03171 0.00053 10.4 0.04755 0.0481 10.0 0.04603 0.000554 13.4 0.06157 0.0621 13.1 0.05997 0.000535 16.5 0.07569 0.0762 16.2 0.07417 0.000516 19.6 0.08945 0.0900 19.3 0.08798 0.000557 22.7 0.10345 0.1040 22.4 0.10186 0.000558 25.8 0.11731 0.1178 25.5 0.11567 0.000499 28.9 0.13135 0.1318 28.5 0.12993 0.0004510 31.9 0.14505 0.1455 31.5 0.14371 0.0004511 34.9 0.15890 0.1593 34.6 0.15759 0.000412 38 0.17286 0.1733 37.6 0.17123 0.0004413 41 0.18633 0.1868 40.6 0.18508 0.0004714 43.9 0.19983 0.2003 43.6 0.19869 0.0004715 47 0.21352 0.2140 46.6 0.21218 0.0004816 50 0.22720 0.2275 49.6 0.22570 0.000317 53 0.24086 0.2412 52.6 0.23945 0.0003418 56 0.25350 0.2549 55.6 0.25300 0.001419 58.9 0.26806 0.2685 58.6 0.26658 0.0004420 61.8 0.28123 0.2816 61.4 0.27952 0.0003721 64.8 0.29493 0.2953 64.5 0.29345 0.0003722 67.7 0.30809 0.3085 67.5 0.30688 0.0004123 70.7 0.32144 0.3219 70.4 0.32013 0.0004624 73.7 0.33492 0.3353 73.4 0.33350 0.0003825 76.6 0.34833 0.3487 76.3 0.34720 0.0003726 79.5 0.36165 0.3621 79.2 0.36003 0.0004527 82.4 0.37483 0.3753 82.2 0.37350 0.0004728 85.3 0.38789 0.3882 85.0 0.38634 0.0003129 88.2 0.40110 0.4015 88.0 0.39978 0.000430 91.1 0.41397 0.4143 90.8 0.41288 0.0003331 94 0.42745 0.4278 93.7 0.42589 0.00035

114

Abbreviations

ADC Analog-to-Digital ConverterALICE A Large Ion Collider ExperimentASIC Application Specific Integrated CircuitBJT Bipolar Junction TransistorCERN Conseil Européen pour la Recherche NucléaireCMOS Complimentary Metal-Oxide-SemiconductorCOTS Commercial Off The ShelfCPU Central Processing UnitDUT Device Under TestECSS European Cooperation for Space StandardisationHIF Heavy Ion Irradiation FacilityI2C Inter-Integrated CircuitIC Integrated CircuitINA Texas Instruments INA3221IP Intellectual PropertyJUICE Jupiter Icy Moons ExplorerLEO Low Earth OrbitLET Linear Energy TransferLHC Large Hadron ColliderMCM Multi-ChipModulePCB Printed Circuit BoardRADEM Rad-Hard ElectronMonitorRHBD Radiation Hardened by DesignRHBP Radiation Hardened by ProcessROIC Readout Integrated CircuitSAA South Atlantic AnomalySEE Single-Event EffectSEFI Single-Event Functional InterruptSEL Single-Event Latch-upSELDM Single Event Latch-up DetectionModuleSELTC Single Event Latch-up Test CircuitSEU Single-Event UpsetSOI Silicon-On-InsulatorTMR Triple Modular RedundancyUCL Université catholique de LouvainUM Université de Montpellier

115

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