PIC18F14K22LIN Data Sheet - hytic.net · 2011. 8. 4. · LFINTOSC Oscillator 16 MHz Oscillator Single-Supply Programming FVR FVR FVR CV REF Address Latch Program Memory Data Latch

2011 Microchip Technology Inc. Preliminary DS41580A

PIC18F14K22LINData Sheet

20-Pin Flash Microcontrollers

with Integrated LIN Transceiver and

Voltage Regulator

Note the following details of the code protection feature on Microchip devices:• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of ourproducts. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such actsallow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding deviceapplications and the like is provided only for your convenienceand may be superseded by updates. It is your responsibility toensure that your application meets with your specifications.MICROCHIP MAKES NO REPRESENTATIONS ORWARRANTIES OF ANY KIND WHETHER EXPRESS ORIMPLIED, WRITTEN OR ORAL, STATUTORY OROTHERWISE, RELATED TO THE INFORMATION,INCLUDING BUT NOT LIMITED TO ITS CONDITION,QUALITY, PERFORMANCE, MERCHANTABILITY ORFITNESS FOR PURPOSE. Microchip disclaims all liabilityarising from this information and its use. Use of Microchipdevices in life support and/or safety applications is entirely atthe buyer’s risk, and the buyer agrees to defend, indemnify andhold harmless Microchip from any and all damages, claims,suits, or expenses resulting from such use. No licenses areconveyed, implicitly or otherwise, under any Microchipintellectual property rights.

DS41580A-page 2 Prelimin

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their respective companies.

© 2011, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.

Printed on recycled paper.

ISBN: 978-1-61341-171-1Microchip received ISO/TS-16949:2002 certification for its worldwide

ary 2011 Microchip Technology Inc.

headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

PIC18F14K22LIN20-Pin Flash Microcontrollers with Integrated LIN Transceiver

and Voltage Regulator

Cross-referenced Material:This data sheet refers heavily to the following Microchipdata sheets:

• PIC18F1XK22/LF1XK22 Data Sheet (DS41365)• MCP2021/2, LIN Tranceiver with Voltage Regula-

tor Data Sheet (DS22018)

Please have these documents available when readingthis device specification. Only deviations from the datasheets listed above will be noted.

Devices Included In This Data Sheet:• PIC18F14K22LIN

High-Performance RISC CPU:• C Compiler Optimized Architecture/Instruction Set• 256 Bytes Data EEPROM• Linear Program Memory Addressing to 16 Kbytes• Linear Data Memory Addressing to 512 Bytes • Up to 16 MIPS Operation• 16-bit Wide Instructions, 8-bit Wide Data Path• Priority Levels for Interrupts • 31-Level, Software Accessible Hardware Stack• 8 x 8 Single-Cycle Hardware Multiplier

Flexible Oscillator Structure:• Precision 16 MHz Internal Oscillator Block:

- Factory calibrated to ±1%- Software selectable frequencies range of

31 kHz to 16 MHz- 64 MHz performance available using PLL –

no external components required• Four Crystal modes up to 64 MHz• Two External Clock modes up to 64 MHz• 4X Phase-Lock Loop (PLL)• Secondary Oscillator using Timer1 @ 32 kHz• Fail-Safe Clock Monitor:

- Allows for safe shutdown if peripheral clock stops

• Two-Speed Oscillator Start-up

Special Microcontroller Features:• Full 5.5V Operation• Self-Reprogrammable under Software Control• Power-on Reset (POR), Power-up Timer (PWRT)

and Oscillator Start-up Timer (OST)• Programmable Brown-out Reset (BOR)• Extended Watchdog Timer (WDT) with On-Chip

Oscillator and Software Enable• Programmable Code Protection• In-Circuit Serial Programming™ (ICSP™) via

Two Pins• In-Circuit Debug via Two Pins

Power Managed Modes:• RUN – CPU on, Peripherals on• IDLE – CPU off, Peripherals on• Sleep – CPU off, Peripherals off

Analog Features:• Analog-to-Digital (A/D) Converter module:

- 10-bit resolution- 9 analog input channels- Auto acquisition capability- Conversion available during Sleep

• Analog Comparator module with:- Two rail-to-rail analog comparators- Comparator inputs and outputs externally

accessible and configurable• Voltage Reference module with:

- Programmable on-chip voltage reference (CVREF) module (% of VDD)

- Fixed Voltage Reference (FVR) with multiple reference voltages

Peripheral Features:• 12 I/O pins and 1 Input Only Pin:

- High current sink/source 25 mA/25 mA- Individually programmable weak pull-ups- Individually programmable interrupt-on-pin

change• Three External Interrupt Pins• Four Timer modules:

- 3 16-bit timers/counters with prescaler- 1 8-bit timer/counter with 8-bit period register,

prescaler and postscaler- Dedicated, low-power Timer1 oscillator

2011 Microchip Technology Inc. Preliminary DS41580A-page 3

PIC18F14K22LIN

• Enhanced Capture/Compare/PWM (ECCP)

module with:- One, two or four PWM outputs- Selectable polarity- Programmable dead time- Auto-shutdown and Auto-restart- PWM output steering control

• Enhanced Universal Synchronous Asynchronous Receiver Transmitter module (EUSART):- Supports RS-232, RS-485 and LIN 2.0- Auto-Baud Detect- Auto Wake-up on Start bit

• SR Latch (555 Timer) module with:- Configurable inputs and outputs- Supports mTouch™ capacitive sensing

applications• On-board Voltage Regulator:

- Output voltage of 5.0V with tolerances of ±3% over temperature range

- Maximum continuous input voltage of 30V- Internal thermal overload protection- Internal short circuit current limit- External components limited to filter

capacitor only and load capacitor- Automatic thermal shutdown

• Internal Bus Transceiver Compliant with LIN Bus Specifications 1.3, 2.0 and 2.1 and are Compliant to SAE J2602:- Support Baud Rates up to 20 Kbaud- 43V load dump protected- Very low EMI meets stringent OEM require-

ments- Wide supply voltage, 6.0V-18.0V continuous:- Internal pull-up resistor and diode- Protected against ground shorts- Protected against loss of ground- High current drive- Automatic thermal shutdown

• Extended Temperature Range: -40 to +125°C

DS41580A-page 4 Preliminary 2011 Microchip Technology Inc.

PIC18F14K22LIN

TABLE 1: DEVICE OVERVIEW

Pin Diagrams

Device

Program Memory Data Memory

Pins I/O

10-b

it A

/DC

hann

els

Com

para

tors

Tim

ers

8-bi

t/16-

bit

ECC

P

EUSA

RT(

1)

SR L

atch

Other Features

Bytes Words SRAM(bytes)

Data EEPROM(bytes)

PIC18F14K22LIN 16K 8K 512 256 20 13 9-ch 2 1/3 1 1 Yes LIN Transceiver, Voltage Regulator

Note 1: EUSART dedicated to LIN communications.

20-PIN SSOP

10

23456

1

87

9111213141516

1920

1817

VDDRA5/OSC1/CLKIN/T13CKIRA4/AN3/OSC2/CLKOUT

RA3/MCLR/VPPRC5/CCP1/P1A

RC4/C2OUT/P1B/SRQRC3/AN7/C12IN3-/P1C/PGM

VssLBUSVREG

VSSRA0/AN0/CVREF/VREF-/C1IN+/INT0/PGDRA1/AN1/C12IN0-/VREF+/INT1/PGCRA2/AN2/C1OUT/T0CKI/INT2/SRQRC0/AN4/C2IN+RC1/AN5/C12IN1-RC2/AN6/C12IN2-/P1DRB4/AN10FAULT/TXEVBAT

PIC

18F1

4K22

LIN


PIC18F14K22LIN

FIGURE 1: PIC18F14K22LIN BLOCK DIAGRAM

InstructionDecode and

Control

PORTA

PORTB

PORTC

RA1RA0

Data Latch

Data Memory

Address Latch

Data Address12

AccessBSR FSR0FSR1FSR2

inc/declogic

Address

4 12 4

PCH PCL

PCLATH

8

31-Level Stack

Program Counter

PRODLPRODH

8 x 8 Multiply

8

BITOP88

ALU

20

8

8

Table Pointer

inc/dec logic

21

8

Data Bus

Table Latch8

IR

12

3

ROM Latch

PCLATU

PCU

Note 1: RA3 is only available when MCLR functionality is disabled.2: OSC1/CLKIN and OSC2/CLKOUT are only available in select Oscillator modes and when these pins are not being used

as digital I/O. Refer to DS41365, “PIC18(L)F1XK22 Data Sheet”, Section 2.0 “Oscillator Module” for additional information.

Comparator 10-bit ADC

Timer2Timer1 Timer3Timer0

ECCP1

BORData

EEPROM

W

Instruction Bus

STKPTR Bank

8

State machinecontrol signals

Decode

8

8

Power-upTimer

OscillatorStart-up Timer

Power-onReset

WatchdogTimer

OSC1(2)

OSC2(2)

VDD,

InternalOscillator

Fail-SafeClock Monitor

Precision

ReferenceBand GapVSS

MCLR(1)

Block

LFINTOSCOscillator

16 MHzOscillator

Single-SupplyProgramming

FVR

FVRFVRCVREF

Address Latch

Program Memory

Data Latch

CVREF

RA3RA4RA5

RB4

RC0RC1RC2RC3RC4RC5

(512/768 bytes)

LDORegulator

RA1

EUSART

TX RX

Transceiver

LBUSFAULT/

TXE

VoltageRegulator

RB6

ENABLE

RESETVSSVREGVBAT

RB5RB7

RC7

RC6NC


PIC18F14K22LIN

TABLE 2: PIC18F14K22LIN PIN SUMMARY

20-P

iN S

SOP

I/O

Ana

log

Com

para

tor

Ref

eren

ce

ECC

P

EUSA

RT

SR L

atch

Tim

ers

Inte

rrup

ts

Pull-

up

Bas

ic

19 RA0 AN0 C1IN+ VREF-/CVREF — — — — IOC/INT0 Y PGD18 RA1 AN1 C12IN0- VREF+ — — — — IOC/INT1 Y PGC17 RA2 AN2 C1OUT — — — SRQ T0CKI IOC/INT2 Y —4 RA3 — — — — — — — IOC Y MCLR/VPP3 RA4 AN3 — — — — — — IOC Y OSC2/CLKOUT2 RA5 — — — — — — T13CKI IOC Y OSC1/CLKIN

13 RB4 AN10 — — — — — — IOC Y —Note RB5 — — — — RXD — — — — —Note RB6 — — — — — — — — — CS/LWAKENote RB7 — — — — TXD — — — — —16 RC0 AN4 C2IN+ — — — — — — — —15 RC1 AN5 C12IN1- — — — — — — — —14 RC2 AN6 C12IN2- — P1D — — — — — —7 RC3 AN7 C12IN3- — P1C — — — — — PGM6 RC4 C2OUT — P1B — SRQ — — — —5 RC5 — — — CCP1/P1A — — — — — —

Note RC6 — — — — — — — — — no connectionNote RC7 — — — — — — — — — RESET input from

Voltage Regulator12 FAULT/

TXE— — — — — — — — —

11 VBAT — — — — — — — — —10 VREG — — — — — — — — —9 LBUS — — — — — — — — —8 — — — — — — — — — — VSS1 — — — — — — — — — — VDD

20 — — — — — — — — — — VSSNote 1: Internal connection. No associated external pin.


PIC18F14K22LIN

Table of Contents1.0 Using the MCP200X in LIN Bus Applications............................................................................................................................... 92.0 Memory Organization ................................................................................................................................................................. 173.0 I/O Ports ..................................................................................................................................................................................... 234.0 Master Synchronous Serial Port (MSSP) Module ...................................................................................................................... 315.0 Analog-to-Digital Converter (ADC) Module ................................................................................................................................ 336.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ................................................................. 357.0 LIN/J2602 Transceiver and Voltage Regulator .......................................................................................................................... 418.0 Electrical Specifications.............................................................................................................................................................. 439.0 DC and AC Characteristics Graphs and Tables......................................................................................................................... 4910.0 Development Support................................................................................................................................................................. 5111.0 Packaging Information................................................................................................................................................................ 55Appendix A: Revision History............................................................................................................................................................... 59

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PIC18F14K22LIN

1.0 USING THE MCP200X IN LIN BUS APPLICATIONS

1.1 HardwareThe MCP200X internal connections are optimized toreduce the number of components in a typical LIN/J2602 node in a LIN bus system. Some features andmodules of the stand-alone PIC18F14K22 are nolonger available or their functionality has changed.

FIGURE 1-1: TYPICAL LIN NETWORK CONFIGURATION

For this reason, the following (Example 1-1) is arecommended block diagram. Note the microcontrolleris powered by the internal voltage regulator and anexternal connection must be made between VREG andVBB along with a load capacitor. FAULT/TXE can bemonitored or controlled by any I/O pin.

Note: Failure to follow the recommended setupand initialization may result in improper orunknown LIN operation.

LIN busMCP202X

MasterµC

1 kVBB

Slave 1µC

Slave 2µC

Slave n

PIC18F14K22LIN

EXAMPLE 1-1: TYPICAL PIC18F14K22LIN APPLICATION

1.2 SoftwarePlease refer to the sections of this data sheet to deter-mine what facilities have changed and what registervalues need to be properly initialized. Failure to followthese guidelines may result in improper operation.

1.2.1 TYPICAL INITIALIZATION CODEInitialiseIOports

MOVLB 0xF ;point the F bankMOVLW 0x04 ;disable AN8:9,11ANDWF ANSELH,fMOVLW 0xC0 ;PORTB7:6 must be inputsIORWF TRISB,fMOVLW 0xCF ;PORTB5:4 must be outputsANDWF TRISB,fBSF LINCS ;Chip Select TransceiverMOVLW 0x80IORWF TRISC,f ;PORTC7 is an inputRETURN

SetupLINUSARTMOVLB 0x0F ;Register Bank 0xFMOVLW B'10010000' ;UART enabled,8-bit,continuous receiveMOVWF RCSTAMOVLW B'00000100' ;8-bit, asynchronous, high-baudrateMOVWF TXSTA

LIN Bus

27V (2)

VBB

LBUS

VREG

VSS

VDD

+12

CF (1)

CG

FAULT/TXEI/O

43V(3)

1 k

+12Master Node Only

Note 1: CF is the filter capacitor for the external voltage supply.2: Transient suppressor diode. VCLAMP L = 27V.3: These components are required for additional load dump protection above 43V.

RTP(3)

VSS


PIC18F14K22LIN

MOVLW B'00001000' ;16-bit Baud Rate GeneratorMOVWF BAUDCONCLRF SPBRGHMOVLW 0x31 ;setup initially for 20KBaud @ 4.0MHz, BRGH=1, BRG16=1MOVWF SPBRGBSF LINCS ;to enable transceiverRETURN

1.3 Sample Transmit SoftwareThis routine is called when PIR1 = 1:PutDATAbyte

MOVF INDF0,w ; copy data byte into w-registerMOVWF TXREGINCF FSR0, f ; point to next locationDECFSZ MESSAGE_COUNTER, f ; decrement Message Counter by oneRETURN

1.4 Sample Receive SoftwareThe following routines are called when PIR1 = 1:GetBREAK

BTFSS RCSTA,FERR ; was BREAK character longer than 8 bits?GOTO BadBREAKchar ; no, not a valid BREAK, too shortMOVF RCREG,w ; dump break character, reset RCIF and FERRBTFSS STATUS,ZGOTO BadBREAKchar ; no, not a valid BREAK, not zeroDECF MESSAGE_COUNTERBTFSS LINRXGOTO $-2BSF BAUDCTL,ABDEN ; enable AutoBaudRETURN

BadBREAKcharMOVF RCREG,w ; dump break character, reset RCIF and FERRRETURN

GetSYNCBTFSC BAUDCTL,ABDOVF; did baud rate generator overflow?GOTO BadSYNCchar; yes, bad sync characterBTFSC RCSTA,FERR; was there a Framing Error?GOTO BadSYNCchar; yes, bad sync characterDECF SPBRGMOVF RCREG,w ; dump sync character, reset RCIFDECF MESSAGE_COUNTERRETURN

BadSYNCcharBCF BAUDCTL,ABDOVF; clear the overflow conditionMOVLW .12 ; reset the state machineMOVWF MESSAGE_COUNTERRETURN

GetDATAbyteMOVF RCREG,w ; get character, reset RCIF and FERRMOVWF RXTX_REG ; copy data into w-registerMOVWF INDF0 ; copy data into data areaINCF FSR0, f ; point to next locationDECF MESSAGE_COUNTER, f ; decrement number of bytes to receive by oneRETURN


PIC18F14K22LIN

NOTES:


PIC18F14K22LIN

2.0 MEMORY ORGANIZATIONSee DS41365, “PIC18F1XK22/LF1XK22 Data Sheet”for descriptions of program memory, Data RAM andData EEPROM.


PIC18F14K22LIN

TABLE 2-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18F14K22LIN DEVICESAddress Name Address Name Address Name Address Name Address Name

FFFh TOSU FD7h TMR0H FAFh SPBRG F87h —(2) F5Fh —(2)

FFEh TOSH FD6h TMR0L FAEh RCREG F86h —(2) F5Eh —(2)

FFDh TOSL FD5h T0CON FADh TXREG F85h —(2) F5Dh —(2)

FFCh STKPTR FD4h —(2) FACh TXSTA(3) F84h —(2) F5Ch —(2)

FFBh PCLATU FD3h OSCCON FABh RCSTA(3) F83h —(2) F5Bh —(2)

FFAh PCLATH FD2h OSCCON2 FAAh EEADRH F82h PORTC(3) F5Ah —(2)

FF9h PCL FD1h WDTCON FA9h EEADR F81h PORTB(3) F59h —(2)

FF8h TBLPTRU FD0h RCON FA8h EEDATA F80h PORTA F58h —(2)

FF7h TBLPTRH FCFh TMR1H FA7h EECON2(1) F7Fh ANSELH(3) F57h —(2)

FF6h TBLPTRL FCEh TMR1L FA6h EECON1 F7Eh ANSEL F56h —(2)

FF5h TABLAT FCDh T1CON FA5h —(2) F7Dh —(2) F55h —(2)

FF4h PRODH FCCh TMR2 FA4h —(2) F7Ch —(2) F54h —(2)

FF3h PRODL FCBh PR2 FA3h —(2) F7Bh —(2) F53h —(2)

FF2h INTCON FCAh T2CON FA2h IPR2 F7Ah IOCBFF1h INTCON2 FC9h SSPBUF(3) FA1h PIR2 F79h IOCAFF0h INTCON3 FC8h SSPADD(3) FA0h PIE2 F78h WPUBFEFh INDF0(1) FC7h SSPSTAT(3) F9Fh IPR1(3) F77h WPUAFEEh POSTINC0(1) FC6h SSPCON1(3) F9Eh PIR1(3) F76h SLRCONFEDh POSTDEC0(1) FC5h SSPCON2(3) F9Dh PIE1(3) F75h —(2)

FECh PREINC0(1) FC4h ADRESH F9Ch —(2) F74h —(2)

FEBh PLUSW0(1) FC3h ADRESL F9Bh OSCTUNE F73h —(2)

FEAh FSR0H FC2h ADCON0 F9Ah —(2) F72h —(2)

FE9h FSR0L FC1h ADCON1 F99h —(2) F71h —(2)

FE8h WREG FC0h ADCON2 F98h —(2) F70h —(2)

FE7h INDF1(1) FBFh CCPR1H F97h —(2) F6Fh SSPMASK(3)

FE6h POSTINC1(1) FBEh CCPR1L F96h —(2) F6Eh —(2)

FE5h POSTDEC1(1) FBDh CCP1CON F95h —(2) F6Dh CM1CON0FE4h PREINC1(1) FBCh VREFCON2 F94h TRISC(3) F6Ch CM2CON1FE3h PLUSW1(1) FBBh VREFCON1 F93h TRISB(3) F6Bh CM2CON0FE2h FSR1H FBAh VREFCON0 F92h TRISA F6Ah —(2)

FE1h FSR1L FB9h PSTRCON F91h —(2) F69h SRCON1FE0h BSR FB8h BAUDCON(3) F90h —(2) F68h SRCON0FDFh INDF2(1) FB7h PWM1CON F8Fh —(2) F67h —(2)

FDEh POSTINC2(1) FB6h ECCP1AS F8Eh —(2) F66h —(2)

FDDh POSTDEC2(1) FB5h —(2) F8Dh —(2) F65h —(2)

FDCh PREINC2(1) FB4h —(2) F8Ch —(2) F64h —(2)

FDBh PLUSW2(1) FB3h TMR3H F8Bh LATC(3) F63h —(2)

FDAh FSR2H FB2h TMR3L F8Ah LATB(3) F62h —(2)

FD9h FSR2L FB1h T3CON F89h LATA F61h —(2)

FD8h STATUS FB0h SPBRGH F88h —(2) F60h —(2)

Legend: = Unimplemented data memory locations, read as ‘0’, Note 1: This is not a physical register.

2: Unimplemented registers are read as ‘0’.3: Registers in BOLD have functional differences. Please refer to appropriate chapters for details.


PIC18F14K22LIN

TABLE 2-2: REGISTER FILE SUMMARY (PIC18F14K22LIN)

File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR

TOSU — — — Top-of-Stack Upper Byte (TOS) ---0 0000TOSH Top-of-Stack, High Byte (TOS) 0000 0000TOSL Top-of-Stack, Low Byte (TOS) 0000 0000STKPTR STKOVF STKUNF — SP4 SP3 SP2 SP1 SP0 00-0 0000PCLATU — — — Holding Register for PC ---0 0000PCLATH Holding Register for PC 0000 0000PCL PC, Low Byte (PC) 0000 0000TBLPTRU — — — Program Memory Table Pointer Upper Byte (TBLPTR) ---0 0000TBLPTRH Program Memory Table Pointer, High Byte (TBLPTR) 0000 0000TBLPTRL Program Memory Table Pointer, Low Byte (TBLPTR) 0000 0000TABLAT Program Memory Table Latch 0000 0000PRODH Product Register, High Byte xxxx xxxxPRODL Product Register, Low Byte xxxx xxxxINTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RABIE TMR0IF INT0IF RABIF 0000 000xINTCON2 RABPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RABIP 1111 -1-1INTCON3 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF 11-0 0-00INDF0 Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register) N/A

POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register) N/A

POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register) N/A

PREINC0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) N/A

PLUSW0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) – value of FSR0 offset by W

N/A

FSR0H — — — — Indirect Data Memory Address Pointer 0, High Byte ---- 0000FSR0L Indirect Data Memory Address Pointer 0, Low Byte xxxx xxxxWREG Working Register xxxx xxxxINDF1 Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register) N/A





N/A

FSR1H — — — — Indirect Data Memory Address Pointer 1, High Byte ---- 0000FSR1L Indirect Data Memory Address Pointer 1, Low Byte xxxx xxxxBSR — — — — Bank Select Register ---- 0000INDF2 Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register) N/A





N/A

FSR2H — — — — Indirect Data Memory Address Pointer 2, High Byte ---- 0000FSR2L Indirect Data Memory Address Pointer 2, Low Byte xxxx xxxxSTATUS — — — N OV Z DC C ---x xxxxLegend: x = unknown, u = unchanged, — = unimplemented, q = value depends on conditionNote 1: The SBOREN bit is only available when the BOREN Configuration bits = 01; otherwise it is disabled and reads as ‘0’. Refer to

DS41365, “PIC18(L)F1XK22 Data Sheet”, Section 21.4 “Brown-out Reset (BOR)” for additional information2: The RA3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0). Otherwise, RA3 reads as ‘0’. This bit

is read-only.3: Rows highlighted in black show required values for normal LIN protocol applications.


PIC18F14K22LIN

TMR0H Timer0 Register, High Byte 0000 0000TMR0L Timer0 Register, Low Byte xxxx xxxxT0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111OSCCON IDLEN IRCF2 IRCF1 IRCF0 OSTS HFIOFS SCS1 SCS0 0011 qq00OSCCON2 — — — — — PRI_SD HFIOFL LFIOFS ---- -10xWDTCON — — — — — — — SWDTEN --- ---0RCON IPEN SBOREN(1) — RI TO PD POR BOR 0q-1 11q0TMR1H Timer1 Register, High Byte xxxx xxxxTMR1L Timer1 Register, Low Bytes xxxx xxxxT1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000TMR2 Timer2 Register 0000 0000PR2 Timer2 Period Register 1111 1111T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000SSPBUF(3) x x x x x x x x xxxx xxxxSSPADD(3) 0 0 0 0 0 0 0 0 0000 0000SSPSTAT(3) 0 0 0 0 0 0 0 0 0000 0000SSPCON1(3) 0 0 0 0 0 0 0 0 0000 0000SSPCON2(3) 0 0 0 0 0 0 0 0 0000 0000ADRESH A/D Result Register, High Byte xxxx xxxxADRESL A/D Result Register, Low Byte xxxx xxxxADCON0 — — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON --00 0000ADCON1 — — — — PVCFG1 PVCFG0 NVCFG1 NVCFG0 ---- 0000ADCON2 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 0-00 0000CCPR1H Capture/Compare/PWM Register 1, High Byte xxxx xxxxCCPR1L Capture/Compare/PWM Register 1, Low Byte xxxx xxxxCCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000VREFCON2 — — — DAC1R4 DAC1R3 DAC1R2 DAC1R1 DAC1R0 ---0 0000

VREFCON1 D1EN D1LPS DAC1OE --- D1PSS1 D1PSS0 — D1NSS 000- 00-0

VREFCON0 FVR1EN FVR1ST FVR1S1 FVR1S0 — — — — 0001 ----PSTRCON — — — STRSYNC STRD STRC STRB STRA ---0 0001BAUDCON(3) ABDOVF RCIDL 0 0 BRG16 — WUE ABDEN 0100 0-00PWM1CON PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 0000 0000ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 0000 0000TMR3H Timer3 Register, High Byte xxxx xxxxTMR3L Timer3 Register, Low Byte xxxx xxxxT3CON RD16 — T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0-00 0000

TABLE 2-2: REGISTER FILE SUMMARY (PIC18F14K22LIN) (CONTINUED)


Legend: x = unknown, u = unchanged, — = unimplemented, q = value depends on conditionNote 1: The SBOREN bit is only available when the BOREN Configuration bits = 01; otherwise it is disabled and reads as ‘0’. Refer to




PIC18F14K22LIN

SPBRGH EUSART Baud Rate Generator Register, High Byte 0000 0000SPBRG EUSART Baud Rate Generator Register, Low Byte 0000 0000RCREG EUSART Receive Register 0000 0000TXREG EUSART Transmit Register 0000 0000TXSTA(3) 0 0 TXEN 0 SENDB BRGH TRMT 0 0000 0010RCSTA(3) SPEN 0 0 CREN 0 FERR OERR 0 0000 000xEEADR EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 0000 0000EEADRH — — — — — — EEADR9 EEADR8 ---- --00EEDATA EEPROM Data Register 0000 0000EECON2 EEPROM Control Register 2 (not a physical register) 0000 0000EECON1 EEPGD CFGS — FREE WRERR WREN WR RD xx-0 x000IPR2 OSCFIP C1IP C2IP EEIP BCLIP — TMR3IP — 1111 111-PIR2 OSCFIF C1IF C2IF EEIF BCLIF — TMR3IF — 0000 000-PIE2 OSCFIE C1IE C2IE EEIE BCLIE — TMR3IE — 0000 000-IPR1(3) — ADIP RCIP TXIP 1 CCP1IP TMR2IP TMR1IP -111 1111PIR1(3) — ADIF RCIF TXIF 0 CCP1IF TMR2IF TMR1IF -000 0000PIE1(3) — ADIE RCIE TXIE 0 CCP1IE TMR2IE TMR1IE -000 0000OSCTUNE INTSRC PLLEN TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 0000 0000TRISC(3) TRISC7 — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111TRISB(3) TRISB7 TRISB6 TRISB5 TRISB4 — — — — 1111 ----TRISA — — TRISA5 TRISA4 — TRISA2 TRISA1 TRISA0 --11 -111LATC(3) LINRESET — LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 xxxx xxxxLATB(3) LATB7 LATB6 LATB5 LATB4 — — — — xxxx ----LATA — — LATA5 LATA4 — LATA2 LATA1 LATA0 --xx -xxxPORTC(3) LINRESET — RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxxPORTB(3) LINTX LINCS LINRX RB4 — — — — xxxx ----PORTA — — RA5 RA4 RA3(2) RA2 RA1 RA0 --xx xxxxANSELH(3) — — — — 0 ANS10 0 0 ---- 1111ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111IOCB IOCB7 IOCB6 IOCB5 IOCB4 — — — — 0000 ----IOCA — — IOCA5 IOCA4 IOCA3 IOCA2 IOCA1 IOCA0 --00 0000WPUB WPUB7 WPUB6 WPUB5 WPUB4 — — — — 1111 ----WPUA — — WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 --11 1111SLRCON — — — — — Reserved Reserved Reserved ---- -111SSPMSK(3) 1 1 1 1 1 1 1 1 1111 1111CM1CON0 C1ON C1OUT C1OE C1POL C1SP C1R C1CH1 C1CH0 0000 1000

CM2CON1 MC1OUT MC2OUT C1RSEL C2RSEL C1HYS C2HYS C1SYNC C2SYNC 0000 0000

CM2CON0 C2ON C2OUT C2OE C2POL C2SP C2R C2CH1 C2CH0 0000 1000

SRCON1 SRSPE SRSCKE SRSC2E SRSC1E SRRPE SRRCKE SRRC2E SRRC1E 0000 0000

SRCON0 SRLEN SRCLK2 SRCLK1 SRCLK0 SRQEN SRNQEN SRPS SRPR 0000 0000

TABLE 2-2: REGISTER FILE SUMMARY (PIC18F14K22LIN) (CONTINUED)


Legend: x = unknown, u = unchanged, — = unimplemented, q = value depends on conditionNote 1: The SBOREN bit is only available when the BOREN Configuration bits = 01; otherwise it is disabled and reads as ‘0’. Refer to




PIC18F14K22LIN

NOTES:


PIC18F14K22LIN

3.0 I/O PORTS

3.1 PORTB, TRISB and LATB Registers

PORTB is a 4-bit wide, bidirectional port. It functionsthe same as described in the “PIC18F1XK22/LF1XK22Data Sheet” (DS41365) with the following differences.

Three bits are dedicated to the LIN transceiver. No pinsare associated with this function. Only RB4 is availableon a pin. The corresponding data direction register isTRISB. The TRISB bits must be set as ‘001x 0000’.The PORTB Data Latch register (LATB) is also memorymapped. Read-modify-write operations on the LATBregister read and write the latched output value forPORTB.

EXAMPLE 3-1: INITIALIZING PORTB

.

Note: On a Power-on Reset, RB areconfigured as analog inputs by default andread as ‘0’.

MOVLW 0C0h ; set RB6 and RB7; high

MOVWF PORTB ; Initialize PORTB by; clearing output; data latches

CLRF LATB ; Alternate method; to clear output; data latches

MOVLW 030h ; Value used to; initialize data ; direction

MOVWF TRISB ; Set RB as outputs; and RB as inputs

REGISTER 3-1: PORTB: PORTB REGISTER

R/W-x R/W-x R/W-x R/W-x U-0 U-0 U-0 U-0LINTX LINCS LINRX RB4 — — — —

bit 7 bit 0

Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 LINTX: Dedicated to the LIN Transceiver Transmit Functionbit 6 LINCS: Dedicated to the LIN Transceiver Chip Select Functionbit 5 LINRX: Dedicated to the LIN Transceiver Receive Functionbit 4 RB4: PORTB I/O Pin bit

1 = Port pin is >VIH0 = Port pin is

PIC18F14K22LIN

REGISTER 3-2: TRISB: PORTB TRI-STATE REGISTER

R/W-1 R/W-1 R/W-1 R/W-1 U-0 U-0 U-0 U-0TRISB7 TRISB6 TRISB5 TRISB4 — — — —

bit 7 bit 0


bit 7-6 TRISB: PORTB Tri-State Control bitsInitialize as 0 = PORTB pin configured as an output

bit 5-4 TRISB: PORTB Tri-State Control bitsInitialize as 1 = PORTB pin configured as an input (tri-stated)

bit 3-0 Unimplemented: Read as ‘0’

REGISTER 3-3: LATB: PORTB DATA LATCH REGISTER

R/W-x R/W-x R/W-x R/W-x U-0 U-0 U-0 U-0LATB7 LATB6 LATB5 LATB4 — — — —

bit 7 bit 0


bit 7 LATB7: Dedicated to the LIN Transceiver Transmit Functionbit 6 LATB6: Dedicated to the LIN Transceiver Chip Select Functionbit 5 LATB5: Dedicated to the LIN Transceiver Receive Functionbit 4 LATB4: RB Port I/O Output Latch Register bitsbit 3-0 Unimplemented: Read as ‘0’


PIC18F14K22LIN

REGISTER 3-4: WPUB: WEAK PULL-UP PORTB REGISTER

R/W-1 R/W-1 R/W-1 R/W-1 U-0 U-0 U-0 U-0WPUB7 WPUB6 WPUB5 WPUB4 — — — —

bit 7 bit 0


bit 7-4 WPUB: Weak Pull-up Enable bit1 = Pull-up enabled0 = Pull-up disabled


REGISTER 3-5: IOCB: INTERRUPT-ON-CHANGE PORTB REGISTER

R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0IOCB7 IOCB6 IOCB5 IOCB4 — — — —

bit 7 bit 0


bit 7-4 IOCB: Interrupt-on-Change bits1 = Interrupt-on-change enabled0 = Interrupt-on-change disabled


TABLE 3-1: PORTB I/O SUMMARY

Pin Function TRISSetting I/OI/O

Type Description

RB4/AN10/SDI/SDA

RB4 0 O DIG LATB data output.1 I TTL PORTB data input; Programmable weak pull-up.

AN10 1 I ANA ADC input channel 10.RB5/AN11/RX/DT RB5 0 O DIG LATB data output.

1 I TTL PORTB data input; Programmable weak pull-up. RX 1 I ST Asynchronous serial receive data input (USART module).

RB6/SCK/SCL RB6 0 O DIG LATB data output.1 I TTL PORTB data input; Programmable weak pull-up.

RB7/TX/CK RB7 0 O DIG LATB data output.1 I TTL PORTB data input; Programmable weak pull-up.

TX 1 O DIG Asynchronous serial transmit data output (USART module).Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;

x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).


PIC18F14K22LIN

TABLE 3-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0Reset Values

on page

ANSELH — — — — 0 ANS10 0 0 30INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RABIE TMR0IF INT0IF RABIF —(1)

INTCON2 RABPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RABIP —(1)

IOCB IOCB7 IOCB6 IOCB5 IOCB4 25LATB LATB7 LATB6 LATB5 LATB4 — — — — 24PORTB LINTX LINCS LINRX RB4 — — — — 23RCSTA SPEN 0 0 CREN 0 FERR OERR 0 38SLRCON Reserved —(1)

SSPCON1 Reserved —(1)

TRISB TRISB7 TRISB6 TRISB5 TRISB4 — — — — 24TXSTA 0 0 TXEN 0 SENDB BRGH TRMT 0 37WPUB WPUB7 WPUB6 WPUB5 WPUB4 — — — — 25Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTB.

0 = must always be written as ‘0’ to avoid undefined LIN operation.Note 1: Information about these registers can be found in the “PIC18(L)F1XK22 Data Sheet” (DS41365).


PIC18F14K22LIN

3.2 PORTC, TRISC and LATC

RegistersPORTC is an 8-bit wide, bidirectional port. It functionsthe same as described in the “PIC18F1XK22/LF1XK22Data Sheet” (DS41365) with the following differences.

One bit is dedicated to the LIN transceiver and one bitis not available. No pins are associated with this func-tion. Only RC are available on pins. The corre-sponding data direction register is TRISC. The TRISCbits must be set as ‘1xxx xxxx’.The PORTC Data Latch register (LATC) is also mem-ory mapped. Read-modify-write operations on theLATC register read and write the latched output valuefor PORTC.

EXAMPLE 3-2: INITIALIZING PORTC

Note: On a Power-on Reset, RC andRC are configured as analog inputsand read as ‘0’.

CLRF PORTC ; Initialize PORTC by; clearing output; data latches

CLRF LATC ; Alternate method; to clear output; data latches

MOVLW 0FFh ; Value used to ; initialize data ; direction

MOVWF TRISC ; Set RC as inputs; RC as outputs; RC as inputs

REGISTER 3-6: PORTC: PORTC REGISTER

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-xLINRESET — RC5 RC4 RC3 RC2 RC1 RC0

bit 7 bit 0


bit 7 LINRESET: LIN Reset Input bit1 = LIN Reset not asserted0 = LIN Reset asserted

bit 6 RC6: No functionbit 5-0 RC: PORTC I/O Pin bits

1 = Port pin is > VIH0 = Port pin is < VIL


PIC18F14K22LIN

REGISTER 3-7: TRISC: PORTC TRI-STATE REGISTER

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1TRISC7 — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0

bit 7 bit 0


bit 7 TRISC7: PORTC Tri-State Control bits1 = PORTC pin configured as LIN Reset input (tri-stated)0 = Do not use to avoid internal contention

bit 6 TRISC6: Don’t carebit 5-0 TRISC: PORTC Tri-State Control bits

1 = PORTC pin configured as an input (tri-stated)0 = PORTC pin configured as an output

REGISTER 3-8: LATC: PORTC DATA LATCH REGISTER

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-xLINRESET — LATC5 LATC4 LATC3 LATC2 LATC1 LATC0

bit 7 bit 0


bit 7 LINRESET: LIN Reset Input bit1 = LIN Reset not asserted0 = LIN Reset asserted

bit 6 LATC6: No functionbit 5-0 LATC: RB Port I/O Output Latch Register bits


PIC18F14K22LIN

TABLE 3-3: PORTC I/O SUMMARY

Pin Function TRISSetting I/OI/O

Type Description

RC0/AN4/C2IN+ RC0 0 O DIG LATC data output.1 I ST PORTC data input.

AN4 1 I ANA A/D input channel 4.C2IN+ 1 I ANA Comparators C2 non-inverting input.

RC1/AN5/C12IN1-

RC1 0 O DIG LATC data output.1 I ST PORTC data input.

AN5 1 I ANA A/D input channel 5.C12IN1- 1 I ANA Comparators C1 and C2 inverting input, channel 1.

RC2/AN6/C12IN2-/P1D



P1D 0 O DIG ECCP1 Enhanced PWM output, channel D.RC3/AN7/C12IN3-/P1C/PGM



P1C 0 O DIG ECCP1 Enhanced PWM output, channel C. PGM x I ST Single-Supply Programming mode entry (ICSP™). Enabled by LVP

Configuration bit; all other pin functions disabled.RC4/C2OUT/P1B RC4 0 O DIG LATC data output.

1 I ST PORTC data input.C2OUT 0 O DIG Comparator 2 output.

P1B 0 O DIG ECCP1 Enhanced PWM output, channel B. RC5/CCP1/P1A RC5 0 O DIG LATC data output.

1 I ST PORTC data input.CCP1 0 O DIG ECCP1 compare or PWM output.

1 I ST ECCP1 capture input.P1A 0 0 DIG ECCP1 Enhanced PWM output, channel A.

RC6 RC6 unavailableRC7 RC7 1 I ST PORTC data input.Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;

x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).


PIC18F14K22LIN

TABLE 3-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC

3.3 Port Analog Control


on page

ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 —(1)

ANSELH — — — — 0 ANS10 0 0 30

CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 —(1)

ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 —(1)

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RABIE TMR0IF INT0IF RABIF —(1)

INTCON2 RABPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RABIP —(1)

INTCON3 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF —(1)

LATC LINRESET — LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 28

PORTC LINRESET — RC5 RC4 RC3 RC2 RC1 RC0 27

PSTRCON — — — STRSYNC STRD STRC STRB STRA —(1)

VREFCON1 D1EN D1LPS DAC1OE --- D1PSS1 D1PSS0 --- D1NSS —(1)

SLRCON — — — — — Reserved Reserved Reserved —(1)

SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 —(1)

TRISC TRISC7 — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 28

T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON —(1)

T3CON RD16 — T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON —(1)

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTB. 0 = must always be written as ‘0’ to avoid undefined LIN operation.Note 1: Information about these registers can be found in the “PIC18(L)F1XK22 Data Sheet” (DS41365).

REGISTER 3-9: ANSELH: ANALOG SELECT HIGH REGISTER

U-0 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1— — — — 0 ANS10 0 0

bit 7 bit 0


bit 7-4 Unimplemented: Read as ‘0’bit 3 Must be ‘0’bit 2 ANS10: RB4 Analog Select Control bit

1 = Digital input buffer of RB4 is disabled0 = Digital input buffer of RB4 is enabled

bit 1-0 Must be ‘0’


PIC18F14K22LIN

4.0 MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE

4.1 Master SSP (MSSP) Module Overview

The Master Synchronous Serial Port (MSSP) module isnot to be used as its operation conflicts with LIN pinfunctions.

TABLE 4-1: REGISTERS ASSOCIATED WITH MSSP OPERATION


on page

IPR1 — ADIP RCIP TXIP 1 CCP1IP TMR2IP TMR1IP —(1)

PIE1 — ADIE RCIE TXIE 0 CCP1IE TMR2IE TMR1IE —(1)

PIR1 — ADIF RCIF TXIF 0 CCP1IF TMR2IF TMR1IF —(1)

TRISC TRISC7 — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 28SSPADD 0 0 0 0 0 0 0 0 —(1)SSPBUF Don’t care —(1)

SSPCON1 0 0 0 0 0 0 0 0 —(1)SSPCON2 0 0 0 0 0 0 0 0 —(1)SSPMSK 1 1 1 1 1 1 1 1 —(1)SSPSTAT 0 0 0 0 0 0 0 0 —(1)Legend: Shaded cells are not used by the MSSP in SPI mode. Register bits shown above must not be changed from their initial values and read as shown.

Note 1: Information about these registers can be found in the “PIC18(L)F1XK22 Data Sheet” (DS41365).


PIC18F14K22LIN

NOTES:


PIC18F14K22LIN

5.0 ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE

The Analog-to-Digital Converter (ADC) allows conver-sion of an analog input signal to a 10-bit binary repre-sentation of that signal. It functions the same asdescribed in the “PIC18F1XK22/LF1XK22 Data Sheet”(DS41365) with the following differences.

FIGURE 5-1: ADC BLOCK DIAGRAM

ADC

AN4

AVDD

VREF+

ADON

GO/DONE

CHS

ADRESH ADRESL

10

10

ADFM

VSS

AN5

AN6AN7

AN3

Reserved

Reserved

AN10

Reserved

AVSS

VREF-

NVCFG[1:0] = 00

FVR

000000010010001101000101

01110110

10001001101010111100110111101111

UnusedUnused

0 = Left Justify1 = Right Justify

DAC

NVCFG[1:0] = 01

FVR

PVCFG[1:0] = 00PVCFG[1:0] = 01

PVCFG[1:0] = 10

AN1

AN2

AN0

Note: Analog channels markedreserved are not available

to pins.


PIC18F14K22LIN

TABLE 5-1: REGISTERS ASSOCIATED WITH A/D OPERATION


on page

ADRESH A/D Result Register, High Byte —(1)

ADRESL A/D Result Register, Low Byte —(1)

ADCON0 — — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON —(1)

ADCON1 — — — — PVCFG1 PVCFG0 NVCFG1 NVCFG0 —(1)

ADCON2 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 —(1)

ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 —(1)

ANSELH — — — — 0 ANS10 0 0 30INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RABIE TMR0IF INT0IF RABIF —(1)




TRISA – – TRISA5 TRISA4 – TRISA2 TRISA1 TRISA0 —(1)

TRISB TRISB7 TRISB6 TRISB5 TRISB4 – – – – 24

TRISC TRISC7 — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 28

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion 0 = must always be written as ‘0’ to avoid undefined LIN operation.Note 1: Information about these registers can be found in the “PIC18(L)F1XK22 Data Sheet” (DS41365).


PIC18F14K22LIN

6.0 ENHANCED UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (EUSART)

The Enhanced Universal Synchronous AsynchronousReceiver Transmitter (EUSART) module is a serial I/Ocommunications peripheral. It is the same as containedin the standard PIC18F1XK22 (See“PIC18F1XK22/LF1XK22 Data Sheet” (DS41365) withthe following exceptions:

• The 9-bit character length and address detection should never be selected

• Synchronous Master or Slave modes are not sup-ported.

• Programmable clock and data polarity should not be used.

6.1 EUSART Asynchronous LIN Transmitter

6.1.1 ASYNCHRONOUS LIN TRANSMISSION SETUP:

1. Initialize the SPBRGH:SPBRG register pair andthe BRGH and BRG16 bits to achieve the desiredbaud rate (see Register 6-3).

2. Enable the asynchronous serial port by clearingthe SYNC bit and setting the SPEN bit.

3. Enable the transmission by setting the TXENcontrol bit. This will cause the TXIF interrupt bitto be set.

4. If interrupts are desired, set the TXIE interruptenable bit. An interrupt will occur immediatelyprovided that the GIE and PEIE bits of theINTCON register are also set.

5. Load 8-bit data into the TXREG register. Thiswill start the transmission.

TABLE 6-1: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION


on page

BAUDCON ABDOVF RCIDL 0 0 BRG16 — WUE ABDEN 39INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RABIE TMR0IF INT0IF RABIF —(1)




RCSTA SPEN 0 0 CREN 0 FERR OERR 0 38SPBRG EUSART Baud Rate Generator Register, Low Byte —(1)

SPBRGH EUSART Baud Rate Generator Register, High Byte —(1)

TXREG EUSART Transmit Register —(1)

TXSTA 0 0 TXEN 0 SENDB BRGH TRMT 0 37Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission. 0 = must always be written as ‘0’ to avoid undefined LIN operation.Note 1: Information about these registers can be found in the “PIC18(L)F1XK22 Data Sheet” (DS41365).


PIC18F14K22LIN

6.1.2 EUSART ASYNCHRONOUS LIN

RECEIVER

6.1.2.1 Asynchronous Reception Setup:1. Initialize the SPBRGH:SPBRG register pair and

the BRGH and BRG16 bits to achieve thedesired baud rate (see Register 6-3).

2. Enable the serial port by setting the SPEN bitand the RX/DT pin TRIS bit. The SYNC bit mustbe clear for asynchronous operation.

3. If interrupts are desired, set the RCIE interruptenable bit and set the GIE and PEIE bits of theINTCON register.

4. Enable reception by setting the CREN bit.5. The RCIF interrupt flag bit will be set when a

character is transferred from the RSR to thereceive buffer. An interrupt will be generated ifthe RCIE interrupt enable bit was also set.

6. Read the RCSTA register to get the error flagsand, if 9-bit data reception is enabled, the ninthdata bit.

7. Get the received 8 Least Significant data bitsfrom the receive buffer by reading the RCREGregister.

8. If an overrun occurred, clear the OERR flag byclearing the CREN receiver enable bit.

TABLE 6-2: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION


on page

BAUDCON ABDOVF RCIDL 0 0 BRG16 — WUE ABDEN 39INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RABIE TMR0IF INT0IF RABIF —(1)




RCREG EUSART Receive Register —(1)

RCSTA SPEN 0 0 CREN 0 FERR OERR 0 38SPBRG EUSART Baud Rate Generator Register, Low Byte —(1)

SPBRGH EUSART Baud Rate Generator Register, High Byte —(1)

TRISC TRISC7 — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 —(1)

TXSTA 0 0 TXEN 0 SENDB BRGH TRMT 0 37Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.Note 1: Information about these registers can be found in “PIC18(L)F1XK22 Data Sheet” (DS41365).


PIC18F14K22LIN

REGISTER 6-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-1 R/W-00 0 TXEN(1) 0 SENDB BRGH TRMT 0

bit 7 bit 0


bit 7 Must be ‘0’bit 6 Must be ‘0’bit 5 TXEN: Transmit Enable bit(1)

1 = Transmit enabled0 = Transmit disabled

bit 4 Must be ‘0’bit 3 SENDB: Send Break Character bit

1 = Send Sync Break on next transmission (cleared by hardware upon completion)0 = Sync Break transmission completed

bit 2 BRGH: High Baud Rate Select bitAsynchronous mode: 1 = High speed 0 = Low speed

bit 1 TRMT: Transmit Shift Register Status bit1 = TSR empty 0 = TSR full

bit 0 Must be ‘0’Note 1: SREN/CREN overrides TXEN in Sync mode.


PIC18F14K22LIN

REGISTER 6-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER(1)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-xSPEN 0 0 CREN 0 FERR OERR 0

bit 7 bit 0


bit 7 SPEN: Serial Port Enable bit1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins)0 = Serial port disabled (held in Reset)

bit 6 Must be ‘0’bit 5 Don’t carebit 4 CREN: Continuous Receive Enable bit

1 = Enables receiver0 = Disables receiver

bit 3 Must be ‘0’bit 2 FERR: Framing Error bit

1 = Framing error (can be updated by reading RCREG register and receive next valid byte)0 = No framing error

bit 1 OERR: Overrun Error bit1 = Overrun error (can be cleared by clearing bit CREN) 0 = No overrun error

bit 0 Don’t care


PIC18F14K22LIN

REGISTER 6-3: BAUDCON: BAUD RATE CONTROL REGISTER

R-0 R-1 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0ABDOVF RCIDL 0 0 BRG16 — WUE ABDEN

bit 7 bit 0


bit 7 ABDOVF: Auto-Baud Detect Overflow bitAsynchronous mode:1 = Auto-baud timer overflowed0 = Auto-baud timer did not overflowSynchronous mode:Don’t care

bit 6 RCIDL: Receive Idle Flag bitAsynchronous mode:1 = Receiver is Idle0 = Start bit has been detected and the receiver is activeSynchronous mode:Don’t care

bit 5 Must be ‘0’bit 4 Must be ‘0’bit 3 BRG16: 16-bit Baud Rate Generator bit

1 = 16-bit Baud Rate Generator is used (SPBRGH:SPBRG)0 = 8-bit Baud Rate Generator is used (SPBRG)

bit 2 Unimplemented: Read as ‘0’bit 1 WUE: Wake-up Enable bit

Asynchronous mode:1 = Receiver is waiting for a falling edge. No character will be received but RCIF will be set on the

falling edge. WUE will automatically clear on the rising edge.0 = Receiver is operating normallySynchronous mode:Don’t care

bit 0 ABDEN: Auto-Baud Detect Enable bitAsynchronous mode:1 = Auto-Baud Detect mode is enabled (clears when auto-baud is complete)0 = Auto-Baud Detect mode is disabledSynchronous mode:Don’t care


PIC18F14K22LIN

NOTES:


PIC18F14K22LIN

7.0 LIN/J2602 TRANSCEIVER AND VOLTAGE REGULATOR

Please refer to “MCP2021/2, LIN Transceiver with Volt-age Regulator Data Sheet” (DS22018). Only differ-ences in the PIC18F14K22LIN are noted here.

The LIN/J2602 Transceiver provides a physical inter-face to a LIN half-duplex bus. It is intended for automo-tive and industrial applications with serial bus speedsup to 20 Kbaud.

The PIC18F14K22LIN provides a +5V 50 mA regulatedpower output.

7.1 Pin Descriptions

7.1.1 POWER OUTPUT (VREG)Positive Supply Voltage Regulator Output pin.

7.1.2 GROUND (VSS)Ground pin.

7.1.3 BATTERY (VBB)Battery Positive Supply Voltage pin. This pin is also theinput for the Internal Voltage Regulator.

7.1.4 LIN BUSThe bidirectional LIN bus Interface pin is the driver unitfor the LIN pin.

7.1.5 FAULT/TXEFault Detect output and Transmitter Enable inputbidirectional pin.

7.2 Internal Connections7.2.1 TRANSMIT DATA INPUT (TXD)The Transmit Data Input pin has an internal pull-up toVREG. The LIN pin is low (dominant) when TXD is low.Internally connected to PORTB.

7.2.2 RECEIVE DATA OUTPUT (RXD)The Receive Data Output pin is a standard CMOSoutput and follows the state of the LIN pin. It is internallyconnected to PORTB.

7.2.3 CS/LWAKEChip Select Input pin. It is internally connected toPORTB.

7.2.4 RESETRESET is an open-drain output. It is internallyconnected to PORTC.


PIC18F14K22LIN

NOTES:


PIC18F14K22LIN

8.0 ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings(†)

Ambient temperature under bias....................................................................................................... -40°C to +125°C

Storage temperature ........................................................................................................................ -65°C to +150°C

Voltage on VDD with respect to VSS, PIC18F1XK22 ........................................................................... -0.3V to +6.0V

Voltage on VDD with respect to VSS, PIC18LF1XK22 ......................................................................... -0.3V to +4.0V

Voltage on MCLR with respect to VSS ................................................................................................. -0.3V to +9.0V

Voltage on all other pins with respect to VSS .............................................................................-0.3V to (VDD + 0.3V

Total power dissipation(1) ............................................................................................................................... 800 mW

Maximum current out of VSS pin ...................................................................................................................... 95 mA

Maximum current into VDD pin ......................................................................................................................... 95 mA

Clamp current, IK (VPIN < 0 or VPIN > VDD)20 mA

Maximum output current sunk by any I/O pin.................................................................................................... 25 mA

Maximum output current sourced by any I/O pin .............................................................................................. 25 mA

Maximum current sunk by all ports ................................................................................................................... 90 mA

Maximum current sourced by all ports ............................................................................................................. 90 mA

Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD – IOH} + {(VDD – VOH) x IOH} + (VOl x IOL).

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for extended periods may affect device reliability.


PIC18F14K22LIN

FIGURE 8-1: HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE

125

25

2.0

0

60

85

VDD (V)

4.0 5.04.5

Tem

pera

ture

(°C

)

2.5 3.0 3.5 5.51.8-40

-20

± 6%

± 3%

± 6%

8.1 DC Characteristics: RC Run Supply Current, PIC18F14K22LIN

PIC18F14K22LIN Standard Operating Conditions (unless otherwise stated)Operating temperature -40°C TA +125°C for extended

Param No. Device Characteristics Typ. Max. Units Conditions

D008 15.5 19.5 A -40°C

VDD = 5.0V

FOSC = 31 kHz(4)

(RC_RUN mode, LFINTOSC source)

16.5 20.5 A +25°C20.5 29.5 A +85°C30.5 35.5 A +125°C

D009 0.98 0.98 mA -40°C TO +125°C VDD = 5.0V

FOSC = 1 MHz(RC_RUN mode, HFINTOSC source)

D010 4.0 4.7 mA -40°C TO +125°C VDD = 5.0V

FOSC = 16 MHz(RC_RUN mode, HF-INTOSC source)

* These parameters are characterized but not tested.Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from

rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading

and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption.

3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended by the formula IR = VDD/2REXT (mA) with REXT in k

4: FVR and BOR are disabled.5: When a single temperature range is provided for a parameter, the specification applies to both industrial and extended

temperature devices.


PIC18F14K22LIN

8.2 DC Characteristics: RC Idle Supply Current, PIC18F14K22LIN

PIC18F14K22LIN Standard Operating Conditions (unless otherwise stated)Operating temperature -40°C TA +125°C for extendedD011 8.5 12.5 A -40°C

VDD = 5.0VFOSC = 31 kHz(4)

(RC_IDLE mode, LFINTOSC source)

9.5 14.5 A +25°C13.5 24.5 A +85°C24.5 30.5 A +125°C

D012 630 780 A -40°C to +125°C VDD = 5.0V

FOSC = 1 MHz(RC_IDLE mode, HF-INTOSC source)

D013 1.8 2.2 mA -40°C to +125°C VDD = 5.0VFOSC = 16 MHz(RC_IDLE mode, HF-INTOSC source)


rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading

and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption.





PIC18F14K22LIN

8.3 DC Characteristics: Primary Run Supply Current, PIC18F14K22LIN



D014

.30 .42 mA -40°C to +125°C VDD = 5.0V

FOSC = 1 MHz(PRI_RUN,EC Med Osc)

D015

3.9 4.4 mA -40°C to +125°C VDD = 5.0V

FOSC = 16 MHz(PRI_RUN,EC High Osc)

D016

12.1 14.6 mA -40°C to +125°C VDD = 5.0V

FOSC = 64 MHz(PRI_RUN,EC High Osc)

D017

3.8 4.8 mA -40°C to +125°C VDD = 5.0V

FOSC = 4 MHz16 MHz Internal(PRI_RUN HS+PLL)

D01812.6 15.6 mA -40°C to +125°C VDD = 5.0V

FOSC = 16 MHz64 MHz Internal(PRI_RUN HS+PLL)


rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin

loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption.





PIC18F14K22LIN

8.4 DC Characteristics: Primary Idle Supply Current, PIC18F14K22LIN



D019

420 455 A -40°C to +125°C VDD = 5.0V

FOSC = 1 MHz(PRI_IDLE mode,EC Med Osc)

D0204.0 4.2 mA -40°C to +125°C VDD = 5.0V

FOSC = 16 MHz(PRI_IDLEmode,EC High Osc)

D0215.3 6.3 mA -40°C to +125°C VDD = 5.0V

FOSC = 64 MHz(PRI_IDLEmode,EC High Osc)







8.5 DC Characteristics: Secondary Run Supply Current, PIC18F14K22LIN



D022 15.5 19.5 A -40°C

VDD = 5.0VFOSC = 32 kHz(3)(SEC_RUN mode, Timer1 as clock)

16.5 20.5 A +25°C20.5 29.5 A +85°C30.5 35.5 A +125°C





4: FVR and BOR are disabled.


PIC18F14K22LIN

8.6 DC Characteristics: Secondary Idle Supply Current, PIC18F14K22LIN



D023 8.5 12.5 A -40°C

VDD = 5.0VFOSC = 32 kHz(3)(SEC_IDLE mode, Timer1 as clock)

9.5 14.5 A +25°C13.5 24.5 A +85°C24.5 30.5 A +125°C





4: FVR and BOR are disabled.

8.7 Thermal ConsiderationsStandard Operating Conditions (unless otherwise stated)Operating temperature -40°C TA +125°C

ParamNo. Sym. Characteristic Typ. Units Conditions

TH01 JA Thermal Resistance Junction to Ambient 108.1 C/W 20-pin SSOP package

TH02 JC Thermal Resistance Junction to Case 24 C/W 20-pin SSOP packageTH03 TJMAX Maximum Junction Temperature 150 CTH04 PD Power Dissipation — W PD = PINTERNAL + PI/OTH05 PINTERNAL Internal Power Dissipation — W PINTERNAL = IDD x VDD(1)

TH06 PI/O I/O Power Dissipation — W PI/O = (IOL * VOL) + (IOH * (VDD - VOH))TH07 PDER Derated Power — W PDER = PDMAX (TJ - TA)/JA(2)

Legend: TBD = To Be DeterminedNote 1: IDD is current to run the chip alone without driving any load on the output pins.

2: TA = Ambient Temperature.3: TJ = Junction Temperature.


PIC18F14K22LIN

9.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES

Graphs and tables are not available at this time.


PIC18F14K22LIN

NOTES:


PIC18F14K22LIN

10.0 DEVELOPMENT SUPPORTThe PIC® microcontrollers and dsPIC® digital signalcontrollers are supported with a full range of softwareand hardware development tools:

• Integrated Development Environment- MPLAB® IDE Software

• Compilers/Assemblers/Linkers- MPLAB C Compiler for Various Device

Families- HI-TECH C for Various Device Families- MPASMTM Assembler- MPLINKTM Object Linker/

MPLIBTM Object Librarian- MPLAB Assembler/Linker/Librarian for

Various Device Families• Simulators

- MPLAB SIM Software Simulator• Emulators

- MPLAB REAL ICE™ In-Circuit Emulator• In-Circuit Debuggers

- MPLAB ICD 3- PICkit™ 3 Debug Express

• Device Programmers- PICkit™ 2 Programmer- MPLAB PM3 Device Programmer

• Low-Cost Demonstration/Development Boards, Evaluation Kits, and Starter Kits

10.1 MPLAB Integrated Development Environment Software

The MPLAB IDE software brings an ease of softwaredevelopment previously unseen in the 8/16/32-bitmicrocontroller market. The MPLAB IDE is a Windows®operating system-based application that contains:

• A single graphical interface to all debugging tools- Simulator- Programmer (sold separately)- In-Circuit Emulator (sold separately)- In-Circuit Debugger (sold separately)

• A full-featured editor with color-coded context• A multiple project manager• Customizable data windows with direct edit of

contents• High-level source code debugging• Mouse over variable inspection• Drag and drop variables from source to watch

windows• Extensive on-line help• Integration of select third party tools, such as

IAR C Compilers

The MPLAB IDE allows you to:

• Edit your source files (either C or assembly)• One-touch compile or assemble, and download to

emulator and simulator tools (automatically updates all project information)

• Debug using:- Source files (C or assembly)- Mixed C and assembly- Machine code

MPLAB IDE supports multiple debugging tools in asingle development paradigm, from the cost-effectivesimulators, through low-cost in-circuit debuggers, tofull-featured emulators. This eliminates the learningcurve when upgrading to tools with increased flexibilityand power.


PIC18F14K22LIN

10.2 MPLAB C Compilers for Various

Device FamiliesThe MPLAB C Compiler code development systemsare complete ANSI C compilers for Microchip’s PIC18,PIC24 and PIC32 families of microcontrollers and thedsPIC30 and dsPIC33 families of digital signal control-lers. These compilers provide powerful integrationcapabilities, superior code optimization and ease ofuse.

For easy source level debugging, the compilers providesymbol information that is optimized to the MPLAB IDEdebugger.

10.3 HI-TECH C for Various Device Families

The HI-TECH C Compiler code development systemsare complete ANSI C compilers for Microchip’s PICfamily of microcontrollers and the dsPIC family of digitalsignal controllers. These compilers provide powerfulintegration capabilities, omniscient code generationand ease of use.

For easy source level debugging, the compilers providesymbol information that is optimized to the MPLAB IDEdebugger.

The compilers include a macro assembler, linker, pre-processor, and one-step driver, and can run on multipleplatforms.

10.4 MPASM AssemblerThe MPASM Assembler is a full-featured, universalmacro assembler for PIC10/12/16/18 MCUs.

The MPASM Assembler generates relocatable objectfiles for the MPLINK Object Linker, Intel® standard HEXfiles, MAP files to detail memory usage and symbolreference, absolute LST files that contain source linesand generated machine code and COFF files fordebugging.

The MPASM Assembler features include:

• Integration into MPLAB IDE projects• User-defined macros to streamline

assembly code• Conditional assembly for multi-purpose

source files• Directives that allow complete control over the

assembly process

10.5 MPLINK Object Linker/MPLIB Object Librarian

The MPLINK Object Linker combines relocatableobjects created by the MPASM Assembler and theMPLAB C18 C Compiler. It can link relocatable objectsfrom precompiled libraries, using directives from alinker script.

The MPLIB Object Librarian manages the creation andmodification of library files of precompiled code. Whena routine from a library is called from a source file, onlythe modules that contain that routine will be linked inwith the application. This allows large libraries to beused efficiently in many different applications.

The object linker/library features include:

• Efficient linking of single libraries instead of many smaller files

• Enhanced code maintainability by grouping related modules together

• Flexible creation of libraries with easy module listing, replacement, deletion and extraction

10.6 MPLAB Assembler, Linker and Librarian for Various Device Families

MPLAB Assembler produces relocatable machinecode from symbolic assembly language for PIC24,PIC32 and dsPIC devices. MPLAB C Compiler usesthe assembler to produce its object file. The assemblergenerates relocatable object files that can then bearchived or linked with other relocatable object files andarchives to create an executable file. Notable featuresof the assembler include:

• Support for the entire device instruction set• Support for fixed-point and floating-point data• Command line interface• Rich directive set• Flexible macro language• MPLAB IDE compatibility


PIC18F14K22LIN

10.7 MPLAB SIM Software SimulatorThe MPLAB SIM Software Simulator allows codedevelopment in a PC-hosted environment by simulat-ing the PIC MCUs and dsPIC® DSCs on an instructionlevel. On any given instruction, the data areas can beexamined or modified and stimuli can be applied froma comprehensive stimulus controller. Registers can belogged to files for further run-time analysis. The tracebuffer and logic analyzer display extend the power ofthe simulator to record and track program execution,actions on I/O, most peripherals and internal registers.

The MPLAB SIM Software Simulator fully supportssymbolic debugging using the MPLAB C Compilers,and the MPASM and MPLAB Assemblers. The soft-ware simulator offers the flexibility to develop anddebug code outside of the hardware laboratory envi-ronment, making it an excellent, economical softwaredevelopment tool.

10.8 MPLAB REAL ICE In-Circuit Emulator System

MPLAB REAL ICE In-Circuit Emulator System isMicrochip’s next generation high-speed emulator forMicrochip Flash DSC and MCU devices. It debugs andprograms PIC® Flash MCUs and dsPIC® Flash DSCswith the easy-to-use, powerful graphical user interface ofthe MPLAB Integrated Development Environment (IDE),included with each kit.

The emulator is connected to the design engineer’s PCusing a high-speed USB 2.0 interface and is connectedto the target with either a connector compatible with in-circuit debugger systems (RJ11) or with the new high-speed, noise tolerant, Low-Voltage Differential Signal(LVDS) interconnection (CAT5).

The emulator is field upgradable through future firmwaredownloads in MPLAB IDE. In upcoming releases ofMPLAB IDE, new devices will be supported, and newfeatures will be added. MPLAB REAL ICE offerssignificant advantages over competitive emulatorsincluding low-cost, full-speed emulation, run-timevariable watches, trace analysis, complex breakpoints, aruggedized probe interface and long (up to three meters)interconnection cables.

10.9 MPLAB ICD 3 In-Circuit Debugger System

MPLAB ICD 3 In-Circuit Debugger System is Micro-chip's most cost effective high-speed hardwaredebugger/programmer for Microchip Flash Digital Sig-nal Controller (DSC) and microcontroller (MCU)devices. It debugs and programs PIC® Flash microcon-trollers and dsPIC® DSCs with the powerful, yet easy-to-use graphical user interface of MPLAB IntegratedDevelopment Environment (IDE).

The MPLAB ICD 3 In-Circuit Debugger probe is con-nected to the design engineer's PC using a high-speedUSB 2.0 interface and is connected to the target with aconnector compatible with the MPLAB ICD 2 or MPLABREAL ICE systems (RJ-11). MPLAB ICD 3 supports allMPLAB ICD 2 headers.

10.10 PICkit 3 In-Circuit Debugger/Programmer and PICkit 3 Debug Express

The MPLAB PICkit 3 allows debugging and program-ming of PIC® and dsPIC® Flash microcontrollers at amost affordable price point using the powerful graphicaluser interface of the MPLAB Integrated DevelopmentEnvironment (IDE). The MPLAB PICkit 3 is connectedto the design engineer's PC using a full speed USBinterface and can be connected to the target via anMicrochip debug (RJ-11) connector (compatible withMPLAB ICD 3 and MPLAB REAL ICE). The connectoruses two device I/O pins and the reset line to imple-ment in-circuit debugging and In-Circuit Serial Pro-gramming™.

The PICkit 3 Debug Express include the PICkit 3, demoboard and microcontroller, hookup cables and CDROMwith user’s guide, lessons, tutorial, compiler andMPLAB IDE software.


PIC18F14K22LIN

10.11 PICkit 2 Development

Programmer/Debugger and PICkit 2 Debug Express

The PICkit™ 2 Development Programmer/Debugger isa low-cost development tool with an easy to use inter-face for programming and debugging Microchip’s Flashfamilies of microcontrollers. The full featuredWindows® programming interface supports baseline(PIC10F, PIC12F5xx, PIC16F5xx), midrange(PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30,dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bitmicrocontrollers, and many Microchip Serial EEPROMproducts. With Microchip’s powerful MPLAB IntegratedDevelopment Environment (IDE) the PICkit™ 2enables in-circuit debugging on most PIC® microcon-trollers. In-Circuit-Debugging runs, halts and singlesteps the program while the PIC microcontroller isembedded in the application. When halted at a break-point, the file registers can be examined and modified.

The PICkit 2 Debug Express include the PICkit 2, demoboard and microcontroller, hookup cables and CDROMwith user’s guide, lessons, tutorial, compiler andMPLAB IDE software.

10.12 MPLAB PM3 Device ProgrammerThe MPLAB PM3 Device Programmer is a universal,CE compliant device programmer with programmablevoltage verification at VDDMIN and VDDMAX formaximum reliability. It features a large LCD display(128 x 64) for menus and error messages and a modu-lar, detachable socket assembly to support variouspackage types. The ICSP™ cable assembly is includedas a standard item. In Stand-Alone mode, the MPLABPM3 Device Programmer can read, verify and programPIC devices without a PC connection. It can also setcode protection in this mode. The MPLAB PM3connects to the host PC via an RS-232 or USB cable.The MPLAB PM3 has high-speed communications andoptimized algorithms for quick programming of largememory devices and incorporates an MMC card for filestorage and data applications.

10.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits

A wide variety of demonstration, development andevaluation boards for various PIC MCUs and dsPICDSCs allows quick application development on fully func-tional systems. Most boards include prototyping areas foradding custom circuitry and provide application firmwareand source code for examination and modification.

The boards support a variety of features, including LEDs,temperature sensors, switches, speakers, RS-232interfaces, LCD displays, potentiometers and additionalEEPROM memory.

The demonstration and development boards can beused in teaching environments, for prototyping customcircuits and for learning about various microcontrollerapplications.

In addition to the PICDEM™ and dsPICDEM™ demon-stration/development board series of circuits, Microchiphas a line of evaluation kits and demonstration softwarefor analog filter design, KEELOQ® security ICs, CAN,IrDA®, PowerSmart battery management, SEEVAL®evaluation system, Sigma-Delta ADC, flow ratesensing, plus many more.

Also available are starter kits that contain everythingneeded to experience the specified device. This usuallyincludes a single application and debug capability, allon one board.

Check the Microchip web page (www.microchip.com)for the complete list of demonstration, developmentand evaluation kits.


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PIC18F14K22LIN

11.0 PACKAGING INFORMATION

11.1 Package Marking Information

Legend: XX...X Customer-specific informationY Year code (last digit of calendar year)YY Year code (last 2 digits of calendar year)WW Week code (week of January 1 is week ‘01’)NNN Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn)* This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it willbe carried over to the next line, thus limiting the number of availablecharacters for customer-specific information.

3e

3e

20-Lead SSOP (5.30 mm) Example

PIC18F14K22LIN-I/SS

1110017


PIC18F14K22LIN

11.2 Package Details The following section give the technical details of the package.

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Documents

PIC18F14K22LIN Data Sheet - hytic.net · 2011. 8. 4. · LFINTOSC Oscillator 16 MHz Oscillator Single-Supply Programming FVR FVR FVR CV REF Address Latch Program Memory Data Latch