S. Reda EN160 SP’07

Design and Implementation of VLSI Systems(EN0160)

Lecture 14: Interconnects

Prof. Sherief RedaDivision of Engineering, Brown University

Spring 2007

[sources: Weste/Addison Wesley – Rabaey/Pearson]

S. Reda EN160 SP’07

Transistors + Wires = Circuits

• Wires (interconnects) are as important as transistors– Speed– Power– Noise

• Alternating layers run orthogonally

S. Reda EN160 SP’07

How interconnects contribute to delay and power?• Interconnects have resistance, capacitance (and

inductance)• Interconnects increase circuit delay:

– The wire capacitance adds loading to each gate– Long wires have significant resistance that further

contribute to the delay• Interconnects increase dynamic power:

– Because of the wire capacitance

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Wire geometry

• Pitch = w + s• Aspect ratio: AR = t/w

– Old processes had AR << 1– Modern processes have AR 2

• Pack in many skinny wires

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1. Wire Resistance

• ρ = resistivity (W*m)

• R = sheet resistance (Ω/) is a dimensionless unit(!)

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How does the kind of metal impact resistivity?

• Until 180 nm generation, most wires were aluminum• Modern processes often use copper

– Cu atoms diffuse into silicon and damage FETs– Must be surrounded by a diffusion barrier

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Contact and via resistance

• Contacts and vias also have 2-20 Ω• Use many contacts for lower R

– Many small contacts for current crowding around periphery

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2. Wire capacitance

• Wire has capacitance per unit length– To neighbors– To layers above and below

• Ctotal = Ctop + Cbot + 2Cadj

layer n+1

layer n

layer n-1

Cadj

Ctop

Cbot

ws

t

h1

h2

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Factors impacting the capacitance

• Parallel plate equation: C = A/d– Wires are not parallel plates, but obey trends– Increasing area (W, t) increases capacitance– Increasing distance (s, h) decreases capacitance

• Dielectric constant– = k0

• 0 = 8.85 x 10-14 F/cm• k = 3.9 for SiO2

• Processes are starting to use low-k dielectrics– k 3 (or less) as dielectrics use air pockets

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M2 capacitance data

• Typical wires have ~ 0.2 fF/mm – Compare to 2 fF/mm for gate capacitance)

• Polysilicon has lower C but high R– Use sparingly for very short wires between gates

0

50

100

150

200

250

300

350

400

0 500 1000 1500 2000

C tota

l (aF/m

)

w (nm)

Isolated

M1, M3 planes

s = 320

s = 480

s = 640s= 8

s = 320

s = 480

s = 640

s= 8

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Given R and C, how to calculate interconnect delay?

• Wires are a distributed system– Approximate with lumped element models

• 3-segment -model is accurate to 3% in simulation• L-model needs 100 segments for same accuracy!• Use single segment -model for Elmore delay

C

R

C/N

R/N

C/N

R/N

C/N

R/N

C/N

R/N

R

C

L-model

R

C/2 C/2

R/2 R/2

C

N segments

-model T-model

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Interconnect delay: the lumped case

0V

Vm Vout

Upper bound on delays in RC trees [Pileggi’97]

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Interconnect delay: ideal analysis

tpd~0.38RC

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Interconnect delay: distributed Elmore delay

R1 R2 R3 RN

C1 C2 C3 CN

lumped overestimates

delay

r = resistance per unit length

c = capacitance per unit length

(ideally, modeling using diffusion equation; covered in class)

S. Reda EN160 SP’07

Delay calculations

Assuming ideal wires:

Realistic wire modeling:

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Layer stack

• AMI 0.6 m process has 3 metal layers• Modern processes use 6-10+ metal layers• Example:

Intel 180 nm process

• M1: thin, narrow (< 3)– High density cells

• M2-M4: thicker– For longer wires

• M5-M6: thickest– For VDD, GND, clk

Intel 180nm process

0

200

400

600

800

1000

1200

1400

1600

1800

2000

6 5 4 3 2 1

metal layer

t(nm)

w(nm)

Why do you think different metal layers have different widths/thickness?