S. Reda EN160 SP’07

Design and Implementation of VLSI Systems(EN0160)

Lecture 13: Power Dissipation

Prof. Sherief RedaDivision of Engineering, Brown University

Spring 2007

[sources: Weste/Addison Wesley – Rabaey/Pearson]

S. Reda EN160 SP’07

Power and Energy

• Power is drawn from a voltage source attached to the VDD pin(s) of a chip.

• Instantaneous Power:

• Energy:

• Average Power:

( ) ( )DD DDP t i t V

0 0

( ) ( )T T

DD DDE P t dt i t V dt

avg0

1 ( )T

DD DDEP i t V dtT T

S. Reda EN160 SP’07

Dynamic power

• Dynamic power is required to charge and discharge load capacitances when transistors switch.

• One cycle involves a rising and falling output.• On rising output, charge Q = CVDD is required• On falling output, charge is dumped to GND• This repeats Tfsw times

over an interval of T

Cfsw

iDD(t)

VDD

S. Reda EN160 SP’07

Dynamic power dissipation

Vin Vout

CL

Vdd

Energy delivered by the supply during input 1 0 transition:

Energy stored at the capacitor at the end of 1 0 transition:

dissipated in NMOS during discharge (input: 0 1)

load capacitance (gate + diffusion +

interconnects)

S. Reda EN160 SP’07

Capacitive dynamic power

If the gate is switched on and off f01 (switching factor) times per second, the power consumption is given by

For entire circuit

where αi is activity factor [0..0.5] in comparison to the clock frequency (which has switching factor of 1)

2dynamic DDP CV f

S. Reda EN160 SP’07

Short circuit current

• When transistors switch, both nMOS and pMOS networks may be momentarily ON at once

• Leads to a blip of “short circuit” current.• < 10% of dynamic power if rise/fall times are

comparable for input and output

S. Reda EN160 SP’07

Dynamic power breakup

Interconnect51%

Gate34%

Diffusion15%

Total dynamic Power [source: Intel’03]

S. Reda EN160 SP’07

Calculating dynamic power: An example

• 200 Mtransistor chip (1.2 V 100 nm process Cg = 2 fF/mm)– 20M logic transistors

• Average width: 12 λ– 180M memory transistors

• Average width: 4 λ

• Static CMOS logic gates: activity factor = 0.1• Memory arrays: activity factor = 0.05 (many banks!)

• Estimate dynamic power consumption per MHz.

6logic

6mem

2dynamic logic mem

20 10 12 0.05 / 2 / 24

180 10 4 0.05 / 2 / 72

0.1 0.05 1.2 8.6 mW/MHz

C m fF m nF

C m fF m nF

P C C f

S. Reda EN160 SP’07

Static (leakage) power

• Static power is consumed even when chip is quiescent.– Leakage draws power from nominally OFF

devices

0 1gs t ds

T T

V V Vnv v

ds dsI I e e

S. Reda EN160 SP’07

Leakage example• The process has two threshold voltages and two oxide

thicknesses. • Subthreshold leakage:

– 20 nA/m for low Vt

– 0.02 nA/m for high Vt

• Gate leakage:– 3 nA/m for thin oxide– 0.002 nA/m for thick oxide

• Memories use low-leakage transistors everywhere• Gates use low-leakage transistors on 80% of logic

S. Reda EN160 SP’07

Leakage power (continued)

• Estimate static power:– High leakage:– Low leakage:

6

6

2.4 10 20 / / 2 3 /

45.6 10 0.02 / / 2 0.002 /

3238

static

static static DD

I m nA m nA m

m nA m nA m

mAP I V mW

6 620 10 0.2 12 0.05 / 2.4 10m m

6

6 6

20 10 0.8 12 0.05 /

180 10 4 0.05 / 45.6 10

m

m m

If no low leakage devices, Pstatic = 749 mW (!)

S. Reda EN160 SP’07

Techniques for low-power design

• Reduce dynamic power– : clock gating, sleep mode– C: small transistors (esp. on clock), short wires – VDD: lowest suitable voltage– f: lowest suitable frequency

Enable

Clock

Clock Gating

2dynamic DDP CV f

only reduce supply voltage of non critical gates

I1I2

I3I4

I5

I6

O1

O2

criticalpath

S. Reda EN160 SP’07

Dynamic power reduction via dynamic VDD scaling

• Scaling down supply voltage – reduces dynamic power– reduces saturation current

increases delay reduce the frequency

Dynamic voltage scaling (DVS): Supply and voltage of the circuit should dynamic adjust according to the workload of our circuits and criticality of the tasks

2dynamic DDP CV f

S. Reda EN160 SP’07

Reducing static power

• Reduce static power– Selectively use low Vt devices– Leakage reduction:

- stacked devices, body bias, low temperature

S. Reda EN160 SP’07

Leakage reduction via adjusting of Vth• Leakage depends exponentially on Vth. How to control Vth?

– Remember: Vth also controls your saturation current delay

2. Oxide thickness1. Body Bias

I1I2

I3I4

I5

I6

O1

O2

criticalpath

Sol1: statically choose high Vt cells for non critical gates

Sol2: dynamically adjust the bias of the body• idle: increase Vt (e.g. by applying –ve body bias on NMOS)• Active: reduce Vt (e.g.: by applying +ve body bias on NMOS)

S. Reda EN160 SP’07

Leakage reduction via Cooling

Impact of temperature on leakage current

S. Reda EN160 SP’07

Summary

We are still in chapter 4:

• We covered delay and power estimation

• Next time, we going to move into integrating the impact of wires into delay/power calculations