S. Reda EN160 SP’07

Design and Implementation of VLSI Systems(EN0160)

Lecture 20: Circuit Design Pitfalls

Prof. Sherief RedaDivision of Engineering, Brown University

Spring 2007

[sources: Weste/Addison Wesley – Rabaey/Pearson]

S. Reda EN160 SP’07

How can circuit design go wrong?

• Underestimating different phenomena• Variations

– Process or runtime

• Reliability concerns

Design for the best and worst and the unexpected in the future!

[material from subsection 4.7, 4.8 and 6.3]

S. Reda EN160 SP’07

Pitfall 1: Underestimating Leakage

• Circuit– Latch

• Symptom– Load a 0 into Q– Set = 0– Eventually Q

spontaneously flips to 1 D Q

X

• Principle: Leakage– Eventually subthreshold leakage may disturb charge

• Solution: Staticize node with feedback– Or periodically refresh node (requires fast clock,

not practical processes with big leakage)

Q

D X

S. Reda EN160 SP’07

Pitfall 2: Underestimating contention due to transistor ratios

• Circuit– Pseudo-nMOS OR

• Symptom– When only one input is

true, Y = 0.– Perhaps only happens in

SF corner. A BYX

• Principle: Ratio Failure– nMOS and pMOS fight each other.– If the pMOS is too strong, nMOS cannot pull X low enough.

• Solution: Check that ratio is satisfied in all corners

S. Reda EN160 SP’07

Pitfall 3: Underestimating charge sharing

• Circuit– Domino AND gate

• Symptom– Precharge gate while

A = B = 0, so Z = 0– Set = 1– A rises– Z is observed to

sometimes rise• Principle:

• Solutions:

B

A

Y

X

Z

• Principle: Charge Sharing– If X was low, it shares charge with Y

• Solutions: Limit charge sharing

– Safe if CY >> CX

– Or precharge node X too

B

A

Y

X

Cx

CY

Z

S. Reda EN160 SP’07

Pitfall 4: ignoring process variations

Both MOSFETs have 30nm channel with 130 dopant atoms in the channel depletion region

threshold voltage 0.97V threshold voltage 0.57V[source: Asenov’99]

Variations are mostly pronounced in gate length, threshold voltage, and oxide thickness

S. Reda EN160 SP’07

Pitfall 5: ignoring runtime variations (temperature)

1st CPU 2nd CPU

cache

Pow

er 4

ser

ver

chip

thermal profile during runtime

[source: Devgan’05]

S. Reda EN160 SP’07

• IR drop/bumps in power supply network reduces saturation current larger transistor delay

(deviations in VDD can be by up to 10%)

Pitfall 5: ignoring runtime variations (IR drop)

S. Reda EN160 SP’07

Pitfall 6: ignoring the future (reliability concerns)

• Electromigration: “Electron wind” causes movement of metal atoms along wires– Excessive electromigration leads to open circuits– Most significant for unidirectional (DC) current: depends on

current density Jdc (current / area)

• Hot Carriers: Electric fields across channel impart high energies to some carriers

– “hot” carriers blasted into the gate oxide become trapped

→ causes shift in Vt over time

→ Eventually Vt shifts too far for devices to operate correctly

S. Reda EN160 SP’07

Combat variability by designing your system in different “corners”

• Transistors have uncertainty in parameters– Process: Leff, Vt, tox of nMOS and pMOS– Vary around typical (T) values

• Fast (F)– Leff: ______– Vt: ______– tox: ______

• Slow (S): opposite• Not all parameters are independent

for nMOS and pMOS nMOS

pM

OS

fastslow

slow

fast

TT

FF

SS

FS

SFshortlowthin

S. Reda EN160 SP’07

Corners for runtime variations

• VDD and T also vary in time and space

• Fast:– VDD: ____

– T: ____

Corner Voltage Temperature

F

T 1.8 70 C

S

Corner Voltage Temperature

F 1.98 0 C

T 1.8 70 C

S 1.62 125 C

high

low

S. Reda EN160 SP’07

Process corners

• Process corners describe worst case variations– If a design works in all corners, it will probably

work for any variation.

• Describe corner with four letters (T, F, S)– nMOS speed– pMOS speed– Voltage– Temperature

S. Reda EN160 SP’07

Simulate your design at different corners

• Some critical simulation corners include

Purpose nMOS pMOS VDD Temp

Cycle time

Power

Subthrehold

leakage

Purpose nMOS pMOS VDD Temp

Cycle time S S S S

Power F F F F

Subthrehold

leakage

F F F S