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Decay Spectroscopy at FAIR Using the Advanced Implantation Detector Array (AIDA). presented by Tom Davinson on behalf of the AIDA collaboration (Edinburgh – Liverpool – CCLRC DL & RAL). Tom Davinson School of Physics The University of Edinburgh. Presentation Outline. Where? Why? - PowerPoint PPT Presentation
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Decay Spectroscopy at FAIRUsing the Advanced Implantation Detector Array (AIDA)
presented byTom Davinson
on behalf of the AIDA collaboration(Edinburgh – Liverpool – CCLRC DL & RAL)
Tom DavinsonSchool of PhysicsThe University of Edinburgh
Presentation Outline
• Where?• Why?• How?• When?• Who?• What next?
•Cost
–Approx €1000M
–€650M central German government
–€100M German regional funding
–€250M from international partners
•Timescale
–Feb 2006- German funds in budget 2007-14
–2007 start construction
–2012 phased start experiments
–2014 completion
NUSTAR
SuperFRS
Future facilityFuture facility100 m
GSI todayGSI today
SIS 100/300
UNILAC
ESR
SIS 18
HESR
RESR
NESR
FAIR: Facility for Antiproton and Ion Research
NUSTAR: Nuclear Structure Astrophysics & Reactions
Exotic (radioactive) beams formed by fragmentation, selected by separator.
HiSpec :gamma spec DeSpec :decay spec LASPEC: laser spec MATS: Penning traps
Stored beam (rings): EXL : hadron scattering ELISe : electron scattering AIC : antiproton scattering
R3B: reactions
FAIR: Production Rates
from FAIR CDR, section 2
Predicted Lifetimes > 100ns
r-process
• Nucleosynthesis along neutron-rich side of valley of stability via s-process and r-process
• s-process – Red Giants, long timescales, moderate n-flux nucleosynthesis close to valley • r-process – Supernova type II?, timescales ~seconds?, high n-flux? nucleosynthesis far from valley
• equilibrium (n,) and (,n) reactions?• n-capture until binding energy becomes small• wait for decay to nuclei with higher binding energy effect of neutron magic numbers – 82, 126?
Require:• nuclear masses (r-process pathway)• decay half lives (abundance along pathway)• -delayed neutron emission probabilities (abundance modification)
NUSTAR: DESPEC/HISPEC
Note – this layout is so out of date …
DESPEC: Implantation DSSD Concept
• SuperFRS, Low Energy Branch (LEB)• Exotic nuclei – energies ~ 50 – 200MeV/u• Implanted into multi-plane, highly segmented DSSD array• Implant – decay correlations• Multi-GeV DSSD implantation events• Observe subsequent p, 2p, , , , p, n … decays• Measure half lives, branching ratios, decay energies …• Tag interesting events for gamma and neutron detector arrays
Implantation DSSD Configurations
Two configurations proposed:
a) 8cm x 24cm “cocktail” mode many isotopes measured simultaneously
b) 8cm x 8cm high efficiency mode concentrate on particular isotope(s)
Implantation – Decay Correlation
• DSSD strips identify where (x,y) and when (t0) ions implanted
• Correlate with upstream detectors to identify implanted ion type
• Correlate with subsequent decay(s) at same position (x,y) at times t1(,t2, …)
• Observation of a series of correlations enables determination of energy distribution and half-life of radioactive decay
• Require average time between implants at position (x,y) >> decay half-lifedepends on DSSD segmentation and implantation rate/profile
• Implantation profilex ~ y ~ 2cm, z ~ 1mm
• Implantation rate (8cm x 24cm) ~ 10kHz, ~ kHz per isotope (say)
• Longest half life to be observed ~ seconds
Implies quasi-pixel dimensions ~ 0.5mm x 0.5mm
Silicon Detector Technology
Current Technology
Single, double-sided, resistive strip
Thin Junctionsp+ 0.1m cf. ~ 0.4m
Integrated ComponentsCoupling CapacitorsBias Resistors
3” & 4” Wafers• Thicknesses ~ 20 – 1500m• Max. Area ~ 70cm2
6” Wafers• Thicknesses ~ 200 – 700m• Max. Area ~ 160cm2
MSL type YY1 (LEDA)• d.c. single sided• 8 sectors, 16 strips/sector• Strip Pitch 5mm• Area 370cm2
NIM A454 (2000) 350
Silicon Detector Technology contd.
GLAST Large Area Telescope (LAT)
• Layers of silicon detectors interleaved with heavy-metal converters for > 20MeV -rays
• Area ~80 m2
• ~106 channels
• integrated a.c. coupling and
bias resistors
• series strip bonding
• >10000 wafers from Hamamatsu Very high quality:
– Leakage current < 2.5 nA/cm2
– Bad channels < 1/10,000
– Full depletion < 100 V
8.95 cm square Hamamatsu-Photonics SSD before cutting from the 6-inch wafer. The thickness is 400 microns, and the strip pitch is 228 microns.
AIDA: DSSD Array Design
• 8cm x 8cm DSSDscommon wafer design for 8cm x 24cm and 8cm x 8cm configurations
• 8cm x 24cm3 adjacent wafers – horizontal strips series bonded
• 128 p+n junction strips, 128 n+n ohmic strips per wafer• strip pitch 625m• wafer thickness 1mm• E, Veto and up to 6 intermediate planes
4096 channels (8cm x 24cm)• overall package sizes (silicon, PCB, connectors, enclosure … )
~ 10cm x 26cm x 4cm or ~ 10cm x 10cm x 4cm
Implantation depth?Stopping power?Ge detector?Calibration?Radiation damage?Cooling?
courtesy B.R
ubio
AIDA: General Arrangement
ASIC Design Requirements
Selectable gain 20 1000 20000 MeV FSRLow noise 12 600 50000 keV FWHM
energy measurement of implantation and decay events
Selectable threshold < 0.25 – 10% FSRobserve and measure low energy , detection efficiency
Integral non-linearity < 0.1% and differential non-linearity < 2% for > 95% FSRspectrum analysis, calibration, threshold determination
Autonomous overload detection & recovery ~ sobserve and measure fast implantation – decay correlations
Nominal signal processing time < 10sobserve and measure fast decay – decay correlations
Receive (transmit) timestamp datacorrelate events with data from other detector systems
Timing trigger for coincidences with other detector systemsDAQ rate management, neutron ToF
Schematic of Prototype ASIC Functionality
Note – prototype ASIC will also evaluate use of digital signal processing
Potential advantages• decay – decay correlations to ~ 200ns• pulse shape analysis• ballistic deficit correction
Representative ASIC Noise Analysis
• Minimise ballistic deficitshaping time >10x tr
operate with ~ snoise dominated by leakage current for ID > 10 nA
Note – amongst other assumptions, we assume detector cooling
Design Study Conclusions
• 4’’ or 6” Si wafer technology?- integrated polysilicon bias resistors (15M)- separate coupling capacitors (require 22nF/200V+)
• Radiation damage mitigation measures essential- detector cooling required
• Noise specification (12keV FWHM) … “not unreasonable”
• Discriminator - low threshold (<50keV) – slow, compromised for ID > 100nA- separate timing discriminator – higher threshold
• x1000 overload recovery ~ s achievable- depends on input pulse shape- optimisation requires more information
Virtex 4FX FPGA Power Supplies,
Temperature+ voltagemonitors and other
components
Fibre Driver(Laser)
16 ch ASIC
128 detector signals in; 1 data fibre out
PPC(Unix)
Ethernetphysicalinterface
ADC Readout
Timestamp control
FADC PSA
ASIC Control
Slow Control
Data Output
ASIC1 SS ADC16 FADCs
ASIC1 SS ADC
16 FADCs
ASIC1 SS ADC16 FADCs
ASIC1 SS ADC16 FADCs
ASIC1 SS ADC16 FADCs
ASIC1 SS ADC16 FADCs
ASIC1 SS ADC16 FADCs
ASIC1 SS ADC16 FADCs
16 FADCs (12 bit)1 Sliding Scale ADC (14bit) per ASIC
Front End Electronics (FEE) Concept
courtesy Ian Lazarus, CCLRC DL
PkDet&
Mux
Preamp + shaper low/high gain. (16 channels)
Octal FADC(serial out)12bit 50MHz(2 per ASIC)
Control Logic
Part ofFPGA
Sliding ScaleSpectroscopyADC 14bits1 to 5us conv.
Octal FADC(serial out)12bit 50MHz(2 per ASIC)
FEE Detail for One ASIC
courtesy Ian Lazarus, CCLRC DL
Slow Control
BUTIS TimestampsData Output Switch
PC FarmASIC ADCASIC ADC Virtex 4FX
FPGA Power Supplies and other
components
Fibre Driver(Laser) forEthernet
EthernetMAC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC Virtex 4FXFPGA Power Supplies
and othercomponents
Fibre Driver(Laser) forEthernet
EthernetMAC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC Virtex 4FXFPGA Power Supplies
and othercomponents
Fibre Driver(Laser) forEthernet
EthernetMAC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC Virtex 4FXFPGA Power Supplies
and othercomponents
Fibre Driver(Laser) forEthernet
EthernetMAC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC Virtex 4FXFPGA Power Supplies
and othercomponents
Fibre Driver(Laser) forEthernet
EthernetMAC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC Virtex 4FXFPGA Power Supplies
and othercomponents
Fibre Driver(Laser) forEthernet
EthernetMAC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC Virtex 4FXFPGA Power Supplies
and othercomponents
Fibre Driver(Laser) forEthernet
EthernetMAC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC Virtex 4FXFPGA Power Supplies
and othercomponents
Fibre Driver(Laser) forEthernet
EthernetMAC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC Virtex 4FXFPGA Power Supplies
and othercomponents
Fibre Driver(Laser) forEthernet
EthernetMAC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC Virtex 4FXFPGA Power Supplies
and othercomponents
Fibre Driver(Laser) forEthernet
EthernetMAC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC Virtex 4FXFPGA Power Supplies
and othercomponents
Fibre Driver(Laser) forEthernet
EthernetMAC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC Virtex 4FXFPGA Power Supplies
and othercomponents
Fibre Driver(Laser) forEthernet
EthernetMAC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC Virtex 4FXFPGA Power Supplies
and othercomponents
Fibre Driver(Laser) forEthernet
EthernetMAC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC Virtex 4FXFPGA Power Supplies
and othercomponents
Fibre Driver(Laser) forEthernet
EthernetMAC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC Virtex 4FXFPGA Power Supplies
and othercomponents
Fibre Driver(Laser) forEthernet
EthernetMAC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC Virtex 4FXFPGA Power Supplies
and othercomponents
Fibre Driver(Laser) forEthernet
EthernetMAC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
ASIC ADCASIC ADC
AIDA: System Concept
courtesy I.Lazarus, CCLRC DL
AIDA Design Concept
Detail of DSSSD detector layers and detector enclosure
Beam
courtesy Dave Seddon & Rob Page, University of Liverpool
AIDA Design Concept
courtesy Dave Seddon & Rob Page, University of Liverpool
AIDA instrumentation (beige)Heavy-metal shielding (grey)
AIDA: Current Status
• Edinburgh – Liverpool – CCLRC DL – CCLRC RAL collaboration
- 4 year grant period- DSSD design, prototype and production- ASIC design, prototype and production- Integrated Front End FEE PCB development and production- Systems integration- Software development
Deliverable: fully operational DSSD array to DESPEC
• Proposal approved EPSRC Physics Prioritisation panel meeting April 2006
• Project commenced August 2006
• Detailed specification development underway
• M0 – specification finalised and critical review
• Technical Specification release to project engineers January 2007
We are here!
AIDA: Resources & Tasks
Cost
• Total announced value proposal £1.96M
Support Manpower
• CCLRC DL c. 4.2 SY FEE PCB DesignDAQ h/w & s/w
• CCLRC RAL c. 3.5 SY ASIC Design & simulationASIC Production
• Edinburgh/Liverpool c. 4.5 SY DSSD Design & productionFEE PCB productionMechanical housing/support
• Platform grant support CCLRC DL/Edinburgh/Liverpool
AIDA: Workplan
AIDA: Project Partners
• The University of Edinburgh (lead RO)Phil Woods et al.
• The University of LiverpoolRob Page et al.
• CCLRC DL & RALJohn Simpson et al.
Project Manager: Tom Davinson
Further information: http://www.ph.ed.ac.uk/~td/AIDA
Technical Specification:http://www.ph.ed.ac.uk/~td/AIDA/Design/AIDA_Draft_Technical_Specification_v1.pdf
Comments on Technical Specification invited!
Acknowledgements
This presentation includes material from other people
Thanks to:
Ian Lazarus (CCLRC DL)Steve Thomas (CCLRC RAL)Dave Seddon & Rob Page (University of Liverpool)Berta Rubio (IFIC, CSIC University of Valencia)Haik Simon (GSI)
