Advanced Implantation Detector Array (AIDA):Update & Issues

Tom DavinsonSchool of PhysicsThe University of Edinburgh

presented byTom Davinson

on behalf of the AIDA collaboration(Edinburgh – Liverpool – STFC DL & RAL)

AIDA: Current Status

• DSSD request for tender

prototypes available 2008/Q3

• Prototype ASIC design

meeting design specificationssubmission 2008/Q2

• FEE design underway

prototype available 2008/Q3liquid cooling required (cf. AGATA digitiser module)

• Prototype testing

fully instrumented 8cm x 8cm DSSDtest experiments being considered for 2009

AIDA: Current Status

• Evaluating

10nF/100V capacitor arrayslong duration operation @ 400V

Analog Devices AD9252 14-bit/50MSPS ADCFEE sampling ADC

• DSSD response high energy heavy-ions

simulations Luigi Bardelli et al.

Texas A&M - November 2008MSL type W1(DS)-1000 34MeV/u 32Cl tr =100ns

GSI (100MeV/u) - March 2008?higher energy, heavier ions predict tr > 400ns

Time Jitter

• Transient signal analysis currently underway (realistic comparator design)

• Preamplifier risetime ( Cf=0.6pF ) tr=110ns

LLD threshold 0.26% 20MeV FSR

20MeV signaljitter ~0.13ns rms ( ID=1nA ), ?ns rms ( ID=100nA )

0.2MeV signaljitter ~2.7ns rms ( ID=1nA ), ~4.0ns rms ( ID=100nA )

events will normally trigger multiple strips ‘simultaneously’S/N improves as n1/2

• Highlights importance ofminimising detector – instrumentation separation

reduces noise and risetimeradiation damage mitigationdetector cooling

Outstanding Issues: approaching the Rubicon

• Package size10cm x 26cm x 4cm (10cm x 10cm x 4cm)

• Mechanical design concepts

10cm x 26cm AIDA/ToF/Ge10cm x 26cm?? AIDA/4 Neutron Detector10cm x 10cm AIDA/TAS

… others?

• Review ASIC Project Specification

DESPEC project requirements satisfied?

AIDA/ToF/Ge

AIDA/4 Neutron (NERO)

AIDA/TAS

Mechanical Design

• STFC Daresbury Laboratoryprofessional 3D CAD/CAE engineering effort available

• Propose STFC Daresbury Laboratory should be responsible for mechanical design of

RISING (cluster detectors) array supports and stand4 Neutron detector stand/overall mechanical design of detectorTAS stand/overall mechanical design of detectorFast Timing Array

• Collaboration remains responsible for detector specification

• STFC DL responsible for ensuring everything fits!

• Assuming UK NUSTAR bid to STFC successful funds available for stand construction, shipping and installation at GSI

AIDA Project Information

Project web site

http://www.ph.ed.ac.uk/~td/AIDA/welcome.html

Design Documents

http://www.ph.ed.ac.uk/~td/AIDA/Design/design.html

Project Technical SpecificationASIC Project Specification v1.3FEE Specification v0.5

The University of Edinburgh (lead RO)Phil Woods et al.

The University of LiverpoolRob Page et al.

STFC DL & RALJohn Simpson et al.

Project Manager: Tom Davinson

Acknowledgements

This presentation includes material from other people

Thanks to:

Ian Lazarus & Patrick Coleman-Smith (STFC DL)Steve Thomas (STFC RAL)Dave Seddon & Rob Page (University of Liverpool)Berta Rubio (IFIC, CSIC University of Valencia)

AIDA: Resources & Tasks

Cost

• Total announced value proposal £1.96M

Support Manpower

• CCLRC DL c. 4.2 SY FEE PCB DesignDAQ h/w & s/w

• CCLRC RAL c. 3.5 SY ASIC Design & simulationASIC Production

• Edinburgh/Liverpool c. 4.5 SY DSSD Design & productionFEE PCB productionMechanical housing/support

• Platform grant support CCLRC DL/Edinburgh/Liverpool

Implantation – Decay Correlation

• DSSD strips identify where (x,y) and when (t0) ions implanted

• Correlate with upstream detectors to identify implanted ion type

• Correlate with subsequent decay(s) at same position (x,y) at times t1(,t2, …)

• Observation of a series of correlations enables determination of energy distribution and half-life of radioactive decay

• Require average time between implants at position (x,y) >> decay half-lifedepends on DSSD segmentation and implantation rate/profile

• Implantation profilex ~ y ~ 2cm, z ~ 1mm

• Implantation rate (8cm x 24cm) ~ 10kHz, ~ kHz per isotope (say)

• Longest half life to be observed ~ seconds

Implies quasi-pixel dimensions ~ 0.5mm x 0.5mm

AIDA: General Arrangement

Representative ASIC Noise Analysis

• Minimise ballistic deficitshaping time >10x tr

operate with ~ snoise dominated by leakage current for ID > 10 nA

Note – amongst other assumptions, we assume detector cooling

AIDA: Workplan

Daughtercard

connector

16 channelASIC

9222ADFADC

9222ADFADC

16 bitADC

Singleto

diffn.

16

1

2I C controls

N 2 2222222222222 22222222

Readout controlsClocksReset

10LVDS 20 pins

10LVDS 20 pins

4

- - AIDA FEE Support connections and parts for one chip

Power Supplies

Daughtercard

connector

16 channelASIC

9222ADFADC

9222ADFADC

16 bitADC

Singleto

diffn.

16

1

2I C controls

N 2 2222222222222 22222222

Readout controlsClocksReset

10LVDS 20 pins

10LVDS 20 pins

4

Daughtercard

connector

16 channelASIC

9222ADFADC

9222ADFADC

16 bit ADC

Singleto

diffn.

16

1

2I C controls

N 2 2222222222222 22222222

Readout controlsClocksReset

10LVDS 20 pins

10LVDS 20 pins

4

Daughtercard

connector

16 channelASIC

9222ADFADC

9222ADFADC

16 bit ADC

Singleto

diffn.

16

1

2I C controls

N 2 2222222222222 22222222

Readout controlsClocksReset

10LVDS 20 pins

10LVDS 20 pins

4

Daughtercard

connector

16 channelASIC

9222ADFADC

9222ADFADC

16 bit ADC

Singleto

diffn.

16

1

2I C controls

N 2 2222222222222 22222222

Readout controlsClocksReset

10LVDS 20 pins

10LVDS 20 pins

4

Xilinx 4 25XC VLX - 688FF 448 I/O

344 4used forASICS 6Timestamp and controls =

6Slow control = 22 22222= 3 2 ,

16 , 4address controls 16Logic Inspection :

: 32leaves spare

Timestamp clock and controls

Slow control interface

Readout interface

4 12XCV FX 320 /I O

Control of the FEE with operating PPC and readout to DAQ with 1 2222: 3 0

SDRAM 8 32Mx : 58 pinsSystemACE : 40 pinsFLASH2 16Mx : 43 pins4ASICs : 64 pins4ASICs : 64 pins

: 2Console pins : 6Timestamp pins

: 4Oscillator pins : 311Total pins

TEMACPHY

32MBSDRAM

SystemACE

FLASH for boot load of

LINUX

Connection forexternal

development CF

45RJ

Timestampexternalinterface

Consoleinterface

Oscillators

Timesta

mpandcontro

ls

Slowcontro

lInt erfa

ce

ReadoutInterfa

ce

- -AIDA FEE ASIC to DAQ block diagram

FPGA & FADCs

FPGA & FADCs

Water cooled metal

Water cooled metal

FPGA & FADCs

FPGA & FADCs

Water cooled metal

Water cooled metal

Water cooled metal

Water cooled metal

Water cooled metal

Water cooled metal

8cms

4cm

s

8Area required for x eightchannel FADCs with one single

to differential buffer perchannel

Allows space for routing the input signals for the second

row of buffers away from the high speed output signals of

the first row.

9cm

s

FPGA for ASIC event readout and slow control

FPGA containing PPC to transfer events to Acquisition computers.

4Mezzanine withASICS

Diagram (above) of the FEE boards as they would fit in the vertical plane. The grey rectangles are heat conductive foam pads which conform to the component outlines and conduct the heat to the water cooled metalwork. The green is pcb, the orange is a Samtec 80 pin connector with a 2.3mm height and the dark brown is the ASIC. The connections to the detector will be on the mezzanine boards to the left and to the acquisition network computers and BUTIS on the right. These are not shown.

Diagram ( alongside) shows the layout of a sub-board.