Analog Integr Circ Sig Process (2007) 53:9–18DOI 10.1007/s10470-006-9019-3

Current status of CMOS low voltage and low powerwireless IC designsTommy K. Tsang · Mourad N. El-Gamal ·Krzysztof Iniewski · Kenneth A. Townsend ·James W. Haslett · Yanjie Wang

Received: 12 December 2005 / Revised: 15 October 2006 / Accepted: 5 December 2006 / Published online: 19 January 2007C© Springer Science + Business Media, LLC 2007

Abstract This paper surveys recent research on CMOS lowvoltage and low power IC designs for wireless applications.Advancements and challenges in using nanometer IC pro-cesses are addressed, and the impacts of device scaling onwireless systems are discussed. Recent advances in devicetechnologies and system architectures are presented. State-of-the-art low power wireless systems, both from academiaand from industry, are summarized. Circuit design tech-niques and challenges for low voltage and low power ap-plications are discussed, along with RF performance andpower trade-offs. Examples of common RF building blocks,e.g. LNA’s and VCO’s, designed for sub-1V power suppliesare presented.

Keywords Low-Voltage . Low-Power . CMOS . Wireless .

Radio Frequency (RF) . Integrated Circuits (IC) .

Nanometer . Sub-1V

1 Introduction

Wireless and mobile communications are two of the fastestgrowing microelectronics applications, and have an enor-mous impact on our daily lives. Driven by the insatiable

T. K. Tsang (�) · M. N. El-GamalRFIC Group, Department of ECE, McGill University,Montreal, Canadae-mail: ktsang@macs.ece.mcgill.ca

K. Iniewski · Y. WangDepartment of ECE, University of Alberta,Edmonton, Canada

K. A. Townsend · J. W. HaslettATIPS Laboratory, Department of ECE, University of Calgary,Calgary, Canada

commercial demand for lower cost and higher bandwidthand functionality RF transceivers, wireless communicationsystems are moving towards higher integration, while operat-ing at higher frequencies. A technology which can maintain abalance among all of these factors will become the dominanttechnology of choice for future wireless applications.

Traditionally, radio frequency integrated circuits (RFIC’s)were implemented in GaAs or in SiGe bipolar technolo-gies, because of their relatively high unity gain cutoff fre-quencies fT (i.e. > 65 GHz) and their lower noise. How-ever, as the minimum feature sizes of the CMOS devicesdecrease, the fT‘s of the transistors continue to improve,to the point where they are becoming comparable to thoseof the GaAs and SiGe processes. Deep sub-micron CMOSdevices with fT‘s exceeding 100 GHz and minimum noisefigures (NF) less that 0.5 dB at 2 GHz have been demon-strated [1, 2]. Due to these promising RF performances, to-gether with the advantages of low cost and ease of integrationwith the baseband digital circuitry, CMOS is becoming a vi-able alternative for RF applications, with continuous effortstowards implementing higher frequency circuits operatingfrom lower supply voltages. This trend has motivated therecent research on low-voltage and low-power CMOS RFICdesigns.

In this paper, different aspects of low voltage and lowpower wireless IC designs are discussed. Section 2 focuseson CMOS design challenges and advancements in nanometerprocesses. Section 3 addresses issues and examples relatedto wireless system-level design, with examples of state-of-the-art low-power and low-voltage wireless systems. Circuittechniques are discussed in Section 4. Two common RFbuilding blocks, namely the low noise amplifier (LNA) andthe voltage controlled oscillator (VCO), are presented. Re-cent published works on sub-1V designs are discussed andcompared.

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2 Current status of nanometer CMOS processes

There are tremendous research efforts on the advancement ofnext generation CMOS technologies, which can be catego-rized into two groups. The first one, is focused on overcomingthe emerging challenges (e.g. leakage current and power dis-sipation) due to the geometry scaling of traditional CMOStechnologies in the deep nanometer regime (i.e. < 100 nm).The second approach is to consider non-standard CMOS pro-cesses which use novel device structures and materials. Thefollowing section will outline the recent advances and thechallenges faced by sub-nanometer CMOS processes.

2.1 Novel device structures

The conventional bulk MOSFET that has served the industryso well for over 30 years is being replaced by novel devicestructures with enhanced performances. Examples of thesestructures include: Silicon on Insulator (SOI) and multiplegate MOSFETs [3].

The SOI technology has been available for a numberof years, but its relative performance advantage over bulkCMOS (30%–50%) was not sufficient in the past to displacethe incumbent. With increasing difficulties with device scal-ing of the bulk MOSFET, it is very likely that a significantportion of the semiconductor industry will shift towards SOIbased structures. Ultra-thin body fully depleted SOI (UTB-SOI) [4] looks particularly promising, although the possibil-ity of using a second gate in planar double-gate structures(DG-SOI) [5] (Fig. 1) offers great potential advantages aswell.

Similar to the SOI technology, a multiple gate conceptwas known for a long time, but only recently that it hasfound applications in practice. In one of the multiple gatecandidates, namely the Fin-FET structure [6] shown in Fig. 2,the gate electrode wraps around a thin FET silicon to create atriple-gate like device structure. Numerous variants based onthe concept of triple gate transistors are being considered. Forexample, a vertical MOSFET is investigated, where current

Fig. 1 Cross-sectional view of the DG-SOI structure [5]

Fig. 2 Conceptual view of a FIN-FET [6]

conduction is orthogonal to the semiconductor surface. Thesestructures are however difficult to manufacture on a VLSIscale.

Due to severe difficulties in device scaling in the nanome-ter regime, it is becoming apparent that the bulk MOSFETwill have to be replaced by new device structures, likely atthe 45 nm node. While the search for the most suitable candi-date will continue for years to come, UTB-SOI and Fin-FETtransistors are the most promising candidates at this point intime.

Both UTB-SOI and Fin-FET devices help to mitigate adegradation of a key transistor parameter: the ratio of thedevice currents in the ON and OFF states - Ion/Ioff . In the mi-cro regime (minimum feature size around 1 µm) the Ion/Ioff

ratio was about a million, facilitating “easy” circuit designs,where the OFF current was negligible compared to the ONcurrent. In the nanometer regime, this ratio becomes a thou-sand, and decreases quickly with each technology generationfor a bulk CMOS. At this rate, ON and OFF currents wouldstart becoming comparable at the 45 nm node and beyond.

2.2 New materials

The era of “simple” silicon based CMOS device scaling hasended. Modern processes are being enhanced by using i)silicon straining techniques, ii) high-k dielectric materialsfor oxide, and iii) metal electrodes which were once used 30years ago.

Strain is one of the most promising process techniquesused to improve silicon performance [7, 8]. Its applica-tion requires the use of new materials with different latticeconstants, like silicon carbide (SiC) and silicon germanium(SiGe). Strain can be implemented into MOSFETs using aglobal approach, where stress is introduced across the entiresubstrate, or by means of local epitaxial layers and/or highstress nitride capping layers in the devices. There are twoapproaches to produce a strained silicon lattice. The first oneconsists of using materials with a smaller lattice constant,like silicon carbide (Si1−xCx), or with a larger lattice con-stant, like silicon germanium (Si1−xGex). Depending on the

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material used and the growth conditions, one can achieveeither uniaxial or biaxial stresses. Due to advantages relatedto n-channel threshold voltage shifts and p-channel mobilityenhancements at low strain and high vertical electric fields[9–11], process induced uniaxial stresses are being adoptedby the industry as the first generation of strained silicondevices.

Strained silicon is being adopted for two key reasons.Firstly, the design and fabrication costs associated with im-plementing strained Si are modest (about 2%). Secondly,strained Si offers unmatched performance enhancements of10–30%, in today’s productions of 300 mm wafers [10]. Oneof the drawbacks of the strain technique is that it increasesthe formation of dislocations. This can be compensated forby modifying the dislocation growth kinetics. In addition, italso increases the variation in performance across all tran-sistor layout styles. Hence, some design rule modificationsare usually required.

High-k dielectrics and metal gates—Low dielectric con-stant (low-k) materials are exploited as interconnect layers,in order to mitigate the issue of the parasitic capacitances ofcopper wires to substrates. In a similar manner, high dielec-tric constant (high-k) oxides are investigated to increase theMOSFET capacitances per unit area. Higher capacitanceslead to larger transistor drives and improved short channelcharacteristics in general.

High-k gate dielectrics have been investigated for decades,and were once thought to be the lead material change requiredto extend simple geometry scaling. High-k gates will likelybe adopted slowly at the 45 nm node or even later, as manypractical issues still need to be resolved. Good progress hasbeen made in high-k reliability and in recovering most ofthe degraded mobility. However, some mobility degradationstill exists at low vertical electric fields, which reduces theoverall performance enhancement to near a single digit.

Significantly increased wafer costs also result when usinghigh-k materials, since dual metal gates are then requiredfor integration into the bulk planar CMOS device structure.The integration flow for dual metal work functions is enor-mously complex. How metal gates can withstand rapid ther-mal processing anneals remains to be seen. To put this intoa historical perspective, the semiconductor industry movedaway from metal, aluminum gates, to polysilicon gates in theseventies.

2.3 Manufacturability and reliability

The new device structures and materials are only some ofthe several challenges that CMOS technologies face in thenanometer regime. Another big challenge is the increasein process variations. While process manufacturing has al-ways dealt with intrinsic parameter variations for transistorchannel lengths and widths, new challenges such as line

edge roughness and dopant fluctuations have emerged re-cently. Line edge roughness causes variations in device char-acteristics, while dopant fluctuations cause threshold volt-age variability. The latter effect should not be surprising,knowing that a modern MOSFET contains only hundredsof dopant atoms within its depletion layer under the gateoxide.

The main challenge resulting from all process variationfactors is that the transistor parameters are no longer deter-ministic. The Ioff current can vary by a factor of 100 in onesilicon wafer, while the Ion current can vary by a factor of 2in another. As a result of this large parameter variation, newdevice simulation tools are required to predict the integratedcircuit performances, and ensure successful manufacturabil-ity.

Apart from process manufacturability, CMOS device re-liability is another important factor. Thin oxides, shallowdrain/source junctions, and nanometer scale channel lengthscause reliability problems such as oxide integrity, hot elec-tron effects, electrostatic discharge (ESD), latch-up or thresh-old voltage instability. Among them, the negative bias tran-sistor instability (NBTI) is becoming a major road block tofurther process scaling.

NBTI effects can be so severe that CMOS designers haveto take them into account early on when designing circuitsthat experience large voltage swings, such as charge pumpsused to increase local power supply levels, LC oscillatorsand amplifiers where the instantaneous voltages can swingabove VDD due to the presence of inductors, or high-speedI/O circuits. Performing reliability simulations prior to thesilicon tape-out is extremely challenging and requires de-tailed process information from silicon foundries, which isoften not available.

2.4 Power dissipation

Power dissipation is another huge CMOS scaling challenge.Power density in high performance microprocessors is ap-proaching limits imposed by package and silicon ability toremove heat from the integrated circuits. Needless to men-tion, power dissipation in battery operated equipment likecellular phones or laptops is extremely important. Finally, inapplications that demand power scavenging, as in wirelesssensor networks, power dissipation is by far the most impor-tant issue, more important sometimes than performance oreven cost.

CMOS power dissipation has two components: static anddynamic. The static power dissipation is due to varioussources of leakage currents, and in some analog circuitscan occur in circuits that are permanently turned on likebias references. The dynamic power dissipation is due tothe charging and discharging of capacitive loads, as well asshort circuit currents that flow in CMOS circuits at the time

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Fig. 3 Cross-sectional view of a MOSFET showing its leakage cur-rents

of gate switching due to the creation of a temporary directconnection between VDD and VSS.

How does static power dissipation compare to the dy-namic one? While at the 0.25 µm process node the staticpower dissipation was negligible (below 1%), it has becomenoticeable at 90 nm, contributing typically about 10% of thetotal power, and is expected to become about equal to thedynamic power at the 45 nm process node. As a result, con-trolling leakage currents becomes a huge process and circuitdesign task that needs to be managed in order to continuemoving CMOS technologies forward.

2.5 Leakage currents

There are 3 major sources of device leakage in a MOSFETstructure [12]: (i) subthreshold leakage, (ii) junction leakage,including band-to-band-tunneling (BTBT), and (iii) gate ox-ide leakage. The conceptual view of the leakage currents ina MOSFET is shown in Fig. 3.

Subthreshold leakage is a diffusion current that flowsbetween the drain and the source of a MOSFET when thedevice is nominally off, which means that its gate-sourcevoltage VGS is smaller than the threshold voltage VT. Thesubthreshold current has an exponential dependence on VGS.In short channel devices, the threshold voltage VT has a lineardependence on the VDS voltage due to the drain-inducedbarrier lowering (DIBL) effect. As a result, the subthresholdleakage has also an exponential dependence on VDS.

Junction leakage is a well-known diffusion current flow-ing in reversely biased p-n junctions. In the nanometerregime, it exhibits an additional band to band tunnelingnature [13]. The reasons for this effect are again devicephysics and scaling laws that resulted in doping levels onboth sides of the drain-bulk junction being high. The highdoping levels and the use of “halo” implants to control short-channel effects have resulted in small depletion widths andhigh electric fields, leading to the possibility of the band-to-band-tunneling (BTBT) process. During BTBT, electronstunnel directly from the valence band (VB) of the p-type sideto the conduction band (CB) of the n-type side. As a result,the BTBT current depends on the junction voltage (VDB).

Gate leakage is due to electrons that directly tunnelthrough the gate oxide [14, 15]. The gate current density de-pends on the oxide thickness and the applied voltage acrossthe gate oxide, which is equal to VGS at the source end ofthe channel and VGD ( = VGS − VDS) at the drain end of thechannel.

As a result of the distributed nature of the gate leakageacross the transistor channel, the total gate leakage can bedivided into 3 components: Gate to (i) source/drain overlapregions, (ii) channel region, and (iii) bulk region.

When the transistor is OFF, the gate to source/drain over-lap leakage dominates and is entirely under the control ofthe external voltages VGS and VDS. When the transistor isON, the gate to channel leakage dominates. The gate to bulkleakage is negligible in most cases.

Total leakage is the sum of the subthreshold, junction, andgate leakage sources. While the subthreshold and junctioncomponents were always present in CMOS technologies, theemergence of gate leakage is a new phenomenon starting toaffect CMOS circuit designs at the 90 nm technology node.

As the threshold voltage VT scales down and the min-imum feature size decreases, the subthreshold componentincreases quite dramatically. Thinner oxides lead to highergate leakage. Higher doping levels and “halo” implants in-crease junction leakage. It is clear that the increase of allcomponents compounds the leakage problem.

Historically, the leakage was rarely an issue at the 1 µmprocess node. Then, subthreshold leakage became quite visi-ble around the 0.18 µm node, gate leakage around the 90 nmnode, and finally the BTBT leakage will become pronouncedaround the 45 nm node.

2.6 Impact on RF performance

While the above challenges apply universally to all CMOScircuits, analog and RF circuits exhibit additional limitationsdue to their specific requirements. Consider a typical scalingscenario, as illustrated in Table 1, in which the power supplyvoltage VDD is scaled down together with the process feature

Table 1 Simulated NMOS device parameters for different CMOStechnologies

CMOS Tech. min. size L 180nm

130nm

90 nm 65 nm 45 nm

VDD (V) 1.8 1.2 1.0 0.9 0.8gm (mS/µm) 0.55 0.85 1.01 1.45 1.65Av = gm/gds (V/V) 19.5 13.1 8.5 7.8 7.1CGS (fF/µm) 1.37 1.06 0.82 0.55 0.45CGD (fF/µm) 0.45 0.42 0.39 0.34 0.31fT (GHz) 50 90 128 160 226NFmin (dB)∗ > 0.5 0.5 0.33 0.2 < 0.2

∗Estimated at 2 GHz for the NMOS devices in [2].

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size L, which determines the transistor minimum channellength. Some intrinsic device parameters, such as the gate-source transconductance gm, the drain-source conductancegds, the gate-source capacitance CGS, and the gate-drain ca-pacitance CGD are obtained from simulations.

Foundry available BSIM3 models are used to simulatefor the 90–180 nm CMOS processes. A large transistor sizein the order of 100 µm is chosen, which is typical for RFapplications. It is biased in the strong inversion region, witha fixed drain current density of 200 µA/µm and an overdrivevoltage (i.e. VOD = VGS − VT) greater than 0.3 V. Atwo-dimensional (2D) mixed-mode device-circuit simulator,Sequoia [16], is used for the 45 nm and 65 nm processes.The results are summarized in Table 1.

As indicated in the table, the voltage gain Av keeps de-creasing from a value of about 19.5 V/V in the 180 nmprocess to about 7.1 V/V at the 45 nm node. This trend il-lustrates the challenges expected to obtain reasonable gainin the CMOS nanometer regime.

For low frequency applications, one can increase the gainby increasing the channel lengths L of transistors, which in-creases the output resistance ro. For a typical nanometer pro-cess, doubling L increases Av by more than 50%. However,this solution is not applicable to high frequency applicationswhere inductive loads are often used instead of active loads.

Although gain will be more difficult to obtain with scaling,the transistors speeds increase substantially. It is well knownthat the cut-off frequency is proportional to 1/L2 for longchannel devices. For short channel transistors, because of themobility degradation and velocity saturation effects, the cut-off frequency of short channel devices is instead proportionalto 1/L.

The fT of the NMOS transistor increases from about50 GHz at 180 nm to about 226 GHz at 45 nm. Whethersuch a high fT will really be obtained in practice remains tobe seen. Nevertheless, it is safe to say that the 65 nm processwill be sufficient to build reliable millimeter-wave CMOScircuits from a frequency point of view. In fact, circuits op-erating in this range have already been reported using 90 nmand 130 nm CMOS processes [17, 18].

The minimum noise figure for a MOSFET continuallydecreases as technology scales down. Its performance is be-coming comparable to, if not better than, modern bipolartechnologies, but at the expense of higher power consump-tion (e.g. higher current density) for the same gain level.Nonetheless, it is still an attractive technology choice formany low noise RF designs.

3 Low-voltage and low-power system level design

The ultimate goal of low-voltage and low-power wirelesssystems is the deployment of ubiquitous embedded commu-

nications. Cost and size are important factors that must beconsidered, making highly integrated devices desirable. Bylimiting power dissipation to microwatt levels in these sys-tems, self-generation and energy scavenging also becomeviable.

Traditional RF design techniques are often not the op-timum choices for low-power ubiquitous wireless systems[19]. Short transmission distances imply that simple front-ends are suitable. Standby power must be minimized, ne-cessitating the use of wakeup radios and low-leakage digitalcircuits. The adaptability of the network is also important;ad-hoc protocols amongst wireless motes improve redun-dancy against failure.

System-level design of low-voltage and low-power wire-less IC’s is primarily function driven. For specialized ap-plications, designers have flexibility in the selection of theoperating frequency, modulation scheme, and data rate. Thetransmission distance is also important; short-range systemsare less subject to stringent bandwidth limitations. Recentwork on wireless sensor networks has focused on the iden-tification of the optimum network and frequency selectionsfor low power designs [20]. Frequency Shift Keying (FSK)has been identified as an optimum scheme when the choiceof modulation is optional, given that its constant envelopeis suitable for nonlinear power amplifiers [21]. A commoncomparison between such systems is based on the calculationof energy-per-bit, a figure of merit that encompasses bothtransceiver and back-end digital blocks. Systems intendedto meet existing standards, such as the 802.15.4, Zigbee,or Bluetooth, must meet minimum acceptable levels of per-formance. While the protocols employed by these standardsoften result in low average energy usage, the standards them-selves do not demand high efficiency in circuit design. Zig-bee, for example, extends battery life through low duty-cycleoperation. Systems that optimize start-up or shutdown timefind favour, but transceiver power consumption during theon-state is often not critical. Nonetheless, reducing the powerconsumption of the transceiver is always beneficial, providedthat the overall system performance is not jeopardized.

3.1 Existing wireless systems

The selection of a specific transceiver architecture involvesthe consideration of trade-offs between complexity, cost,level of integration, and power consumption.

1) The Heterodyne Architecture—The classic hetero-dyne topology relies on multiple frequency conversion stepsand subsequent channel selections. The use of more than oneconversion stage is often detrimental in terms of power con-sumption, due to the requirements for additional RF signalgeneration and matching to off-chip filters.

The possibility of using Radio Data System (RDS) pro-tocols for the continuous transmission of information to

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consumers has resulted in new research into FM receiversfor PDAs and other portable devices. One RDS heterodynereceiver for the 88–108 MHz band incorporates both FMand BPSK demodulators [22]. By assuming that only thestrongest channels are the most relevant, and that no FMaudio signal is present in the band of interest, requirementssuch as image rejection, sensitivity to blockers, phase noise,and channel selection filter order have been relaxed. Powersavings can then be achieved in the analog circuit blocks.Measured results suggest that the fully integrated receiverconsumes only 1.2 mW from a 0.9 V supply.

The designers of a Bluetooth transceiver in CMOS employa modified two-stage down-conversion architecture with on-chip image filtering [23]. In this approach, circuit stackingand noninvasive baseband filtering maintains high sensitivitywith low power dissipation.

2) The Zero-IF and Low-IF Architectures—To minimizepower consumption, zero-IF and low-IF topologies are pre-ferred [24, 25]. In a receiver, these architectures eliminatethe need for impedance transformation to off-chip high-Qimage-reject filters through costly buffers. The single-stagedownconversion assigns image rejection, channel selection,and demodulation to the digital domain. Problematic DC off-set errors and 1/f noise in zero-IF can be compensated forusing additional circuitry.

Sensor networks target extremely long battery livesthrough the lowest possible average power consumption. Asdata rates in such networks are typically low, simple mod-ulation schemes in low frequency bands can be employed.A 434 MHz European ISM band transceiver integrated in astandard digital CMOS process for wireless sensor networksuses direct downconversion with a frequency synthesizershared by both the receiver and the transmitter [26, 27]. FSKwith a large modulation index is used to overcome problemsassociated with zero-IF architectures, by avoiding low de-modulated frequencies. Another FSK transceiver, designedfor 20 kbps at 900 MHz, employs a low-IF architecture [28].Power savings are achieved by using a single oscillator withan off-chip inductor to directly drive both a passive mixerfor reception and an output buffer for transmission.

A number of commercially available systems are tar-geted specifically towards sensor networks [29]. These prod-ucts realize extended battery lifetimes through low-currentsleep modes. Fast transition time between the sleep modeand the active mode decreases unnecessary power con-sumption. A simple low frequency RC oscillator can beused to time device wake up cycles at sub micron currentlevels [30].

Power savings can be achieved at higher operating fre-quencies through careful system design. A 2.4 GHz receivertransmitter for the WPAN 802.15.4 standard employs a low-IF architecture in the receiver, and a direct-conversion onein the transmitter [31]. An on-chip polyphase filter provides

sufficient image rejection, eliminating the need for externalfilters. One recent low-voltage low-power receiver for 5 GHzwireless applications consumes 66 mW from a 1.5 V supply[32]. To achieve low-power operation, with a fully integratedsolution, the designers select a direct-conversion architectureand incorporate an amplifier to boost voltage gain, withoutconsuming significant extra power.

3.2 Future wireless systems

The future of low-voltage and low-power wireless IC designswill necessitate the investigation of new techniques to meetincreasingly demanding network requirements. A number ofevolving technologies offer potential.

1) Super-Regenerative Receivers—The super-regenerative architecture was originally proposed inthe 1920’s, but was replaced when the invention of thetransistor made the heterodyne architecture more attrac-tive. Interest in the super-regenerative architecture hasbeen revived recently for two reasons: 1) it contains fewcomponents, and 2) it consumes very little power. Theblock diagram of a generic super-regenerative receiver foron-off keying (OOK) is shown in Fig. 4(a) [33]. In thereceive mode, a series of RF pulses are produced by thesuperregenerative oscillator with an envelope proportionalto the amplitude of the input signal.

A 1V, 1.9 GHz, 400 µW receiver and a 1.6 mW transmitterusing super-regenerative techniques were reported in [34].A common drawback of super-regeneration is that stronginterferers reduce sensitivity. The receiver here uses an off-chip film bulk acoustic resonator (FBAR) to reduce inter-ferences; the high-Q was sufficient for a 5 kbps data ratewith − 100.5 dBm of sensitivity. In [35], a direct-sequence

Fig. 4 (a) Generic super-regenerative receiver [33], and (b) a genericpulse-based UWB transmitter [37]

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spread-spectrum super-regenerative receiver was described.Though not integrated, this design shows potential for en-hanced selectivity.

Super-regenerative receivers relying on phase-locked loopcontrol are also appearing for robust multi-channel operation[36]. The PLL tunes the frequency without requiring a high-Q off-chip resonant element. For a 500 kpbs data rate, theenergy-per-received bit in this 130 nm CMOS design is only7.2 nJ/bit.

2) Ultra-Wideband—Ultra-wideband (UWB) systems of-fer the potential for high data-rates, with immunity againstchannel fading (Fig. 4(b)) [37]. Since short time-domainpulses can be used to encode information, mixers and PLLscan be eliminated in impulse transceivers.

Integrated receiver designs for UWB are still in its earlystages, and power consumption remains prohibitive due tothe large bandwidth and the need for high sampling rates inthe back-end ADC’s. Low-power pulse-based transmitters,however, have recently been demonstrated. In [38], a 2 mWCMOS pulse generator capable of pulse lengths as short as1.1 ns has been measured. This corresponds to a 50 pJ perpulse energy consumption for a 40 MHz pulse rate. Thisdevice is intended for use in a personal Body Area Network(BAN) with an average power consumption per node of lessthan 50 µW [39].

3) RF Powered Devices—Inductively powered deviceshave received significant attention for short-range low fre-quency wireless links, particularly in the area of implantablemedical sensors [40]. Recently, interest has begun to bedirected towards fully RF-powered devices using near-gigahertz operating frequencies. In [41], a rectifier circuitwas demonstrated, with a power handling capability deemedsuitable for sensor networks with node separations belowten meters. From a − 14 dBm 950 MHz RF input sig-nal, the rectifier produced a 1.5 V DC voltage. A 3 V4 mW RFID device that recovers both power and a refer-ence clock from a 450 MHz incident signal at a range ofup to 18 m was presented in [42]. Shortly, RF-powereddevices will move towards more mainstream telemetryapplications.

4) CMOS-MEMS Co-Design—Advances in Microelec-tromechanical Systems (MEMS) present another avenue forthe exploration of low-power wireless ICs. The co-designof CMOS and MEMS for high-Q resonant elements, eitherthrough post-processing or stacked dies, is emerging. Forinstance, a 130 nm injection locked transmitter with an os-cillator that acts as the power amplifier is presented in [43].The oscillator frequency is stabilized with an off-chip FBAR,and data is modulated using OOK. The transmitter consumes1.6 mW for a maximum data rate of 50 kbps. MEMS mayin the future also act as the source from which the bulk ofself-generated power is obtained, thus supplementing envi-ronmental power scavenging.

4 Low-voltage and low-power circuit techniques

Common RF building blocks—Low noise amplifiers andvoltage controlled oscillators are two critical functionalblocks in RF transceiver designs. The following sectionsaddress circuit techniques which enable low voltage opera-tion, without sacrificing the RF performances of these circuitblocks.

1) Sub-1V LNA Designs—Low noise figure, high linear-ity, enough gain, and low power consumption are the mainperformance metrics of an LNA.

A single transistor amplifier is a good candidate for lowvoltage operation, however there are many practical chal-lenges which make it not a popular choice. It is susceptible toinstability problems at RF, due to the gate-to-drain parasiticcapacitance (Cgd), which provides both forward and reverselow impedance paths between the input and output signals.This considerably complicates impedance and noise match-ing, since the input reactance becomes dependent on a corre-lated function of the voltage gain (AV) and Cgd. Nonetheless,this topology has been employed in [44] and demonstratedlow voltage operation by using transformer feedback neu-tralization techniques. It should be noted here that the de-sign/use of integrated transformers is not as straight-forwardas simple inductors. In [45], a 0.6 V 5 GHz LNA has beendemonstrated by cascading complementary single transistoramplifiers. Sub-mW power consumption is achieved througha current reuse technique. However, this design approach re-quires seven on-chip inductors which occupy a relativelylarge chip area.

A common topology used for many LNA designs is thecascode configuration with inductive source degeneration(e.g. [46]). It is popular, providing good gain and noise per-formance. One of its limitations is the need for a relativelyhigh supply voltage headroom, since it involves the stackingof two transistors. However, as the minimum feature sizes ofCMOS transistors decrease, the threshold voltage (VT) andthe drain-to-source saturation voltage (Vds−sat) are further re-duced. It thus becomes possible to implement a low-voltage(e.g. 1 V) cascode LNA in deep sub-micron technologies, butat the price of a degradation in linearity. The reason behindthe linearity degradation is that the transistors are forced tooperate close to the triode region (i.e. close to Vds−sat) as thesupply voltage decreases [47].

The need to increase the linearity of the conventionalcascode structure has motivated the development of the LC-coupled LNA topology shown in Fig. 5(a) [48–50] The mainidea behind this low-voltage topology is the ability to de-couple the AC and DC currents between the two transis-tors, hence allowing the reduction of the voltage supply toless than 1 V, while avoiding pushing the transistors closeto the triode region. To ensure that the circuit operates asa cascode amplifier, the entire RF signal current (gm1vgs1)

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Fig. 5 Low voltage LNA topologies: (a) LC-coupled [48–50], and (b)modified folded cascode [51, 52]

generated by M1 should be fed into the source of M2 (i.e.driving ≈ 1/gm2). A detailed analysis can be found in [48]. Acomparative study in [49] has shown that the linearity perfor-mance of the 1 V LC-coupled structure is similar to that of theconventional cascode structure employing twice the voltageheadroom (i.e. 2 V) at 1.9 GHz. Despite linearity enhance-ment, this low-voltage topology imposes certain challenges,namely the need to achieve high quality AC blocking tanksat the resonance frequency of interest. Both of the reporteddesigns were implemented in a silicon bipolar technology[48, 49]. CMOS implementations of this topology have notbeen demonstrated (simulation is reported in [50]), probablyowing to the inferior qualities of the on-chip passives. Futureadvances in the development of high performance integratedinductors (e.g. in SOI CMOS) may increase the popularityof this topology

Another promising low voltage LNA architecture is thefolded cascode topology shown in Fig. 5(b) [51, 52]. Histor-ically, the use of PMOS devices in RF circuits was not com-mon due to their lower fT‘s, compared to their NMOS coun-terparts. As CMOS technologies scaled down to 0.18 µm,the fT‘s of the PMOS devices became in the order of 20 GHz,making them good candidates for high performance RF de-signs. The structure in Fig. 5(b) is borrowed from the conven-tional folded cascode topology of CMOS operational ampli-fiers, with modifications making it suitable for low-voltageRF applications. A detailed analysis can be found in [52].One inherent advantage of this topology, over other architec-tures, is its potential to allow gain controllability by adjustingthe gate voltage (Vctl) of the PMOS transistor M2, which canresult in overall linearity improvement. Gain control is donewithout affecting the input noise and impedance matching,which are set by the input NMOS transistor M1 only. A rea-sonably low noise figure (e.g. < 3 dB) can be achieved withgain controllability using this topology [52]. Conventionalcascode amplifiers do not have this flexibility, since stackedtransistors share the same DC current. Some recently pub-lished work on very low voltage LNA’s is summarized inTable 2.

Table 2 Performance summary and comparison of recently publishedlow voltage LNA designs

ISCAS’02 [52] JSSC’03 [44] VLS1’04 [51]

CMOS Tech. 180 nm 180 nm 90 nmTopology Folded Cascode Single Trans. Folded CascodeFo (GHz) 5.8 5.75 5.5VDD (V) 1/0.7 1 1/0.6S21 (dB) 13.2/7 14.2∗ 15/11.2PDD (mW) 22.2/12.5 16 11.1/2.1NF(dB) 2.5/2.68 0.9 2.8/3.2Pin−1dB (dBm) − 14/ − 9 − 9.1 (est.) − 17.9/ − 17.5Other Remarks Gain and freq.

tuning

∗Differential,transformerfeedback

More advancedtechnology

B) Sub-1 V VCO Designs—The VCO is another impor-tant building block in RF transceivers. A number of perfor-mance requirements have to be met to make a VCO suitablefor wireless applications, such as low phase noise, low powerconsumption, and adequate frequency tuning.

With the targeted voltage supply down to 1 V and lower,there are limited numbers of VCO topologies suitable forhigh frequency operation. Based on the linear time-variantphase noise theory [53], the half circuit symmetry (i.e. verti-cal) is important to minimize the upconversion of the 1/fnoise, which does not exist in conventional NMOS andPMOS only topologies. The complementary cross-coupledVCO structure features a good balance between low phasenoise and low power consumption, but requires a high supplyvoltage (i.e. 2–3 V) due to transistor stacking.

The low-voltage VCO topology presented in Fig. 6 is avariation of the conventional complementary cross-coupledstructure, which is suitable for high-frequency operationwith good phase noise and low power consumption [54].Capacitors are inserted between the cross-coupled PMOSand NMOS amplifiers to decouple their DC biases, withoutaffecting the AC interaction between the two tanks - the ca-pacitors can be viewed as short circuits at high frequencies.

Fig. 6 Low voltage complementary VCO structure [54, 55]

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Analog Integr Circ Sig Process (2007) 53:9–18 17

Table 3 Performancesummary and comparison ofsome recently published lowvoltage VCO designs

ISSCC’02 [56] RFIC’03 [55] RFIC’04 [57]

CMOS Tech. 120 nm 180 nm 180 nmTopology NMOS only Low voltage

ComplementaryPMOS only

Fo (GHz) 51 12 4.92–5.12VDD (V) 1 1/0.7 1PDD (mW) 1 7.7/2 6PN (dBc/Hz) − 85 @ 1 MHz − 88.1/ − 84.8 @ 100

kHz− 103 @ 100 kHz

FOM (dBc/Hz) − 179.2 − 180.8/ − 183.4 − 195Other Remarks Quadratic staggered ind. Transformer coupled ind. Noise filtering & switched LC

To preserve symmetry, the tank inductor (L) is decomposedinto two inductors (LN, P) connected in parallel. Blockinginductors (L1-L4) are added to provide a DC path for thetwo cross-coupled pairs, while presenting high impedancesto the AC signals. A more detailed analysis can be found in[54].

This modified complementary topology can operate froma very low voltage, while preserving the merits of the originalstructure. However, this comes at the expense of an increas-ing number of passive components. In particular, this topol-ogy requires two differentially excited inductors, four AC-blocking inductors, and two coupling capacitors, as opposedto the only one inductor required in the original topology. Toovercome this, area-efficient design and layout techniqueswere proposed and are detailed in [55]. This results in a veryhigh performance VCO design with very low voltage and lowpower operation. Table 3 summarizes the performance of thisVCO and compares it to other low voltage VCO designs inthe literature.

5 Conclusion

This paper has described design issues and challenges interms of modern CMOS process scaling, system and circuitlevel designs for low-voltage and low-power CMOS wirelessIC designs. Several examples of low power systems for var-ious wireless standards are described. Emerging techniquesto realize low power systems, such as the use of MEMSand simplistic architectures, are also addressed. Circuit tech-niques which enable low voltage operation for two commonRF building blocks (i.e. LNA and VCO) are also presented.Recent research work on sub-1V designs is summarized andcompared.

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