MITLL Low-Power FDSOI CMOS Process

MITLL Low-Power FDSOI CMOS Process

Design Guide

Revision 2004:1 (November 2004)Process Version: 3D01

© 2004 by MIT Lincoln Laboratory. All rights reserved.

This work was sponsored by the United States Air Force under Air Force Contract #F19628-00-C-0002. Opinions, interpretations, conclusions, and recommendations are those of the authors and are not necessarily endorsed by the United States Government.

MITLL Low-Power FDSOI CMOS Process: Design GuideCONTENTS

CONTENTS

Introduction............................................................................................................................................................ 5About Revision 2004:1 .............................................................................................................................................. 5Notes on Conventions ............................................................................................................................................... 5

Units of Measurement. .............................................................................................................................. 5Measurement Method. .............................................................................................................................. 5

Process Parameters .............................................................................................................................................. 7Process Description................................................................................................................................................... 7Resistance Parameters ............................................................................................................................................. 7Capacitance Parameters ........................................................................................................................................... 9

ILD Parameters ....................................................................................................................................... 10Notes on ILD parameters. ....................................................................................................................... 10

Other Film Parameters ............................................................................................................................................ 11Tolerance Parameters ............................................................................................................................................. 12Dopant Concentration Parameters .......................................................................................................................... 13

Design Layers ...................................................................................................................................................... 15All Process Versions................................................................................................................................................ 15Digital Process Versions.......................................................................................................................................... 183D Via Process Versions......................................................................................................................................... 20Notes on Design Layers .......................................................................................................................................... 22

Planar Process ....................................................................................................................................... 22Feature Bias ........................................................................................................................................... 22Fill Patterns ............................................................................................................................................. 22

Lithography Steps ............................................................................................................................................... 23Baseline Digital Process .......................................................................................................................................... 23Alternative Metal Z Process..................................................................................................................................... 24

Design Rules........................................................................................................................................................ 25Nomenclature .......................................................................................................................................................... 25Summary ................................................................................................................................................................. 26Active Area Layer (ACT, ACTF, ACTXPP).............................................................................................................. 40n-Channel Layer Body Implant Layer (CBN) ........................................................................................................... 41p-Channel Body Implant Layer (CBP) ..................................................................................................................... 42p-Type Capacitor Bottom Plate Implant Layer (CAPP) ........................................................................................... 43n-Type Capacitor Bottom Plate Implant Layer (CAPN) ........................................................................................... 44Polysilicon Gate Layer (POLY, POLYF) .................................................................................................................. 45n+ Implant Layer (NSD) ........................................................................................................................................... 47p+ Implant Layer (PSD) ........................................................................................................................................... 49Contact Cut Layer (CON) ........................................................................................................................................ 51Metal 1 Layer (M1, M1F) ......................................................................................................................................... 52Metal 1/Metal 2 Via Layer (V12) .............................................................................................................................. 53

Rev.: 2004:1 (Nov. 04) Process version: 3D01 3Three-tier 0.18-µm 1.5-V digital FDSOI design guide

MITLL Low-Power FDSOI CMOS Process: Design GuideCONTENTS

Metal 2 Layer (M2, M2F) ......................................................................................................................................... 54Metal 2/Metal 3 Via Layer (V23) .............................................................................................................................. 55Metal 3 Layer (M3, M3F) ........................................................................................................................................ 56Overglass Pad Cut Layer (OGC)............................................................................................................................. 56Metal Z Layer, Alternative Single Metal (MZ, MZF) ................................................................................................ 573D Via Cut to Another Wafer Tier (3DCUT) ............................................................................................................ 583D Via Landing from Another Wafer Tier (3DLAND)............................................................................................... 593D Via Cut to Another Wafer Tier (3DCUT)—ALTERNATE RULE SET ................................................................. 603D Via Landing from Another Wafer Tier (3DLAND)—ALTERNATE RULE SET ................................................... 62Flag for Alternate 3D Via Rule Set (3DALT)............................................................................................................ 63Flag for Flipped Wafer w.r.t. Final 3D Stack (3DFLIP) ............................................................................................ 633D Back Side Cut Through Buried Oxide (3DBOXC).............................................................................................. 63Pad Cut for Final 3D Stack (3DPAD)....................................................................................................................... 64Additional Layers: Flag and Comment (Markup) .................................................................................................... 64

Layout Acceptance Requirements..................................................................................................................... 65Design Grid.............................................................................................................................................................. 65Layout Database Format ......................................................................................................................................... 65Top-Level Cell Labels .............................................................................................................................................. 653D Layout ................................................................................................................................................................ 65Minimum Rule Set ................................................................................................................................................... 66Contact Information ................................................................................................................................................. 66Disclaimer ................................................................................................................................................................ 66

Revision History .................................................................................................................................................. 69Contact Information ............................................................................................................................................ 71

4 Rev.: 2004:1 (Nov. 04) Process version: 3D01Three-tier 0.18-µm 1.5-V digital FDSOI design guide

MITLL Low-Power FDSOI CMOS Process: Design GuideINTRODUCTION

Rev.: 2004:1 (Nov. 04) Process version: 3D01Three-tier 0.18-µm 1.5-V digital FDSOI design guide 5

1. INTRODUCTION

1.1. About Revision 2004:1

This document contains Revision 2004:1 of the design guide for MIT Lincoln Laboratory’s three-tier 0.18-µ m 1-5-V low-power 3D FDSOI CMOS process.

Revision 2004:1, November 2004, replaces Version 6.x of the design guide.

1.2. Notes on Conventions

1.2.1. Units of Measurement. In this era of deep-submicron scaling, it is becoming increasingly common to express feature sizes in nanometers rather than microns. Unfortunately, this often causes difficulty for designers who have EDA tool configurations and legacy data with user units corresponding to microns. To aid designers, we have chosen to express all design rule values in microns. To facilitate quick conversion to nanometers, we have also elected to consistently maintain three decimal places. This convention does not apply to measured values and tolerance parameters, for which the number of decimal places must reflect the precision. Thickness parameters are consistently expressed in nanometers.

1.2.2. Measurement Method. Throughout this guide all distances are Euclidean unless otherwise specified.

MITLL Low-Power FDSOI CMOS Process: Design GuidePROCESS PARAMETERS

2. PROCESS PARAMETERS

Sections 2.2–2.5 present parameters for the three-metal digital FDSOI process. Note that electrical parameters are given for devices at 300 K.

2.1. Process Description

Three tiers, each individually fabricated in the MITLL 0.18-µ m 1.5-V digital FDSOI process version, are vertically stacked and interconnected using dense inter-tier vias. The digital process version is an FDSOI CMOS process with single-level poly and triple-level metal with stacked contacts and vias.

2.2. Resistance Parameters

Tables 2-1 through 2-4 list resistivity and resistance parameters.

Table 2-1: Bulk resistivity (p-type handle wafer)

Parameter Value

Standard substrate (digital process version) ~5–10 Ω-cm

Table 2-2: Cobalt silicided silicon sheet resistance

Parameter Value

Silicided n+ active sheet resistance ~40 Ω/sq

Silicided p+ active sheet resistance ~22 Ω/sq

Silicided n+ polysilicon sheet resistance ~26 Ω/sq

Silicided p+ polysilicon sheet resistance ~20 Ω/sq



Table 2-3: Metal sheet resistances

Parameter Value

Lower level metal (all but top level) ~0.12 Ω/sq

Top-level metal:

Digital process version (M3) ~0.08 Ω/sq

Metal Z (may be available)* ~0.1 Ω/sq

*See MITLL Low-Power FDSOI CMOS Process: Application Notes for an explanation of metal Z.

Table 2-4: Contact and via resistances

Parameter* Value

Poly contact (0.250 µ m x 0.250 µ m) ~10 Ω

n+ active contact (0.250 µ m x 0.250 µ m) ~15 Ω

p+ active contact (0.250 µ m x 0.250 µ m) ~10 Ω

Interconnect metal via (0.300 µ m x 0.300 µ m) 4 Ω

*Sizes are as drawn.



2.3. Capacitance Parameters

Capacitance parameters are summarized in Table 2-5. See also “Device Characteristics” in MITLL Low-Power FDSOI CMOS Process: Device Models.

Table 2-5: Summary of capacitance parameters

Parameter Value

MOS gate oxide (Cox) in inversion 6.5 fF/µ m2

n+ poly gate to CAPN active at +1.5 V 6.5 fF/µ m2

p+ poly gate to CAPP active at –1.5 V 6.5 fF/µ m2

Active island or poly to handle wafer (Cbox)

Digital process version 180 aF/µ m2



2.3.1. ILD Parameters. Parameters for digital process versions are presented In Table 2-6.

2.3.2. Notes on ILD parameters. In Table 2-6 the values for area capacitance are measured on lot neo1 (MP5 reticle set). The values for fringe capacitance are based on a model in which fringe field lines from one layer terminate on an infinite ground plane on another layer. MITLL welcomes measurement results on parasitic capacitance from multiproject designers. (Limited information on parasitic capacitance between wires will be sent later to the mailing list for this design guide.) The ILD is planarized, resulting in a layout-dependent thickness distribution. Chemical-mechanical polishing (CMP) is most effective when active, poly, and metal features are evenly distributed across the wafer.

Table 2-6: ILD thickness and interconnect overlap and fringe capacitances: digital process versions

From Layer:

ActivePoly

(field)Poly

(on active)Metal 1 Metal 2

To Metal 1:

Nominal thickness 800 nm 650 nm 600 nm - -

Area capacitance 49 aF/µ m2 59 aF/µ m2 63 aF/µ m2 - -

Fringe capacitance 38 aF/µ m 47 aF/µ m 48 aF/µ m - -

To Metal 2:

Nominal thickness 2430 nm 2280 nm 2230 nm 1000 nm -

Area capacitance - - - 40 aF/µm2 -

Fringe capacitance 35 aF/µ m 40 aF/µ m 40 aF/µ m 54 aF/µ m -

To Metal 3:

Nominal thickness 4060 nm 3910 nm 3860 nm 2630 nm 1000 nm

Area capacitance - - - - 37 aF/µ m2

Fringe capacitance - - - - -



2.4. Other Film Parameters

Tables 2-7 and 2-8 present properties of various process levels.

Table 2-7: Thickness and other parameters

Parameter Value

MOS transistor gate oxide thickness (ellipsometric) 4.2 nm

SOI buried oxide (BOX) thickness 200 nm

Digital process version 200 nm

SOI silicon thickness (in channel region) 40 nm

Polysilicon thickness 200 nm

Gate/silicide spacer thickness 75 nm

Gate/silicide spacer material Si3N4

Isolation technology Mesa-etched

Overglass thickness 1000 nm, not planarized

Thermal oxide dielectric constant 3.9

Deposited ILD oxide dielectric constant 4.2

Silicon substrate thickness 675 ± 25 µ m



2.5. Tolerance Parameters

Active island and polysilicon width tolerances are presented in Table 2-9.

Table 2-8: Structure of metal layers: digital process version

(Bottom to top)

Contact plug metal

To active island Ti:TiN:W (30 nm : 75 nm : 700 nm)

To field poly Ti:TiN:W (30 nm : 75 nm : 550 nm)

Via plug metal Ti:TiN:W (30 nm : 75 nm : 900 nm)

Metal levels Ti:AlSi :Ti:TiN (40 nm : 500 nm : 40 nm : 50 nm)

Table 2-9: Width tolerance parameters

Parameter Value

Active island width(Active is bloated by 0.075 µ m per side in making the reticle. Channel width is normally determined by sidewall post processing; see MITLL Low-Power FDSOI CMOS Process: Application Notes.)

±0.05 µ m

Polysilicon width(Poly widths drawn at 0.200 µm are exposed to produce 0.180-µ m etched poly width on the silicon wafer.)

±0.02 µ m



2.6. Dopant Concentration Parameters

Table 2-10 presents n- and p-type dopant concentration parameters.

Table 2-10: Dopant concentration parameters

Parameter ValueSheet

Resistance

p-channel active (CBP) n-type dopant concentration ~5x1017/cm3

n-channel active (CBN) p-type dopant concentration ~5x1017/cm3

CAPP* p-type (NMOS sidewall implant used for capacitor) dopant concentration ~5x1018/cm3 ~5 kΩ/sq

CAPN* n-type (PMOS sidewall implant used for capacitor) dopant concentration ~1x1019/cm3 ~1 kΩ/sq

*CAPN and CAPP can be used to form high-value resistors using active regions. Salicide protection isrequired. See MITLL Low-Power FDSOI CMOS Process: Application Notes for details.


MITLL Low-Power FDSOI CMOS Process: Design GuideDESIGN LAYERS

3. DESIGN LAYERS

3.1. All Process Versions

Layer GDS No. CIF Name Description

ACT 1 ACT Active island

ACTF 2 ACTF Active island fill

ACTXPP† 3 ACTX Active island with suppressed sidewall processing

CBN 4 CBN n-channel body implant

CBP 5 CBP p-channel body implant

CAPP 6 CAPP ~5x1018 cm-3 p-type island implant

CAPN 7 CAPN ~1x1019 cm-3 n-type island implant

CAPLCN†† 8 CLC ~1x1020 cm-3 n-type island implant

POLY 9 POLY Polysilicon

POLYF 10 POLF Polysilicon fill

POLYPS†† 11 PPS Phase shift poly flag

NSD 12 NSD n+ implant (degenerate doping)

PSD 13 PSD p+ implant (degenerate doping)

NOSLC†† 14 XSLC Salicide protection

CON 15 CON Contact cut (metal 1 to active or poly)

TGSRF†† 16 TGRF Low-resistance tungsten gate shunt for RF

M1 17 M1 Metal 1

M1F 18 M1F Metal 1 fill

V12 19 V12 Metal 1/metal 2 via

M2 20 M2 Metal 2



M3 23 M3 Metal 3


V34†† 25 V34 Metal 3/metal 4 via

(Continued)

† Not for general use. See MITLL Low-Power FDSOI CMOS Process: Application Notes . †† Not offered in the baseline MITLL process.



3.1. All Process Versions (Continued)


M4†† 26 M4 Metal 4

M4F†† 27 M4F Metal 4 fill

V45†† 28 V45 Metal 4/metal 5 via

M5†† 29 M5 Metal 5

M5F†† 30 M5F Metal 5 fill

VTLRF†† 31 VRF MTLRF/next lower metal via

MTLRF†† 32 MRF Top level metal for RF process

MTLRFF†† 33 MRFF MTLRF fill

OGC 34 OGC Overglass cut

MZ††† 36 MZ Metal for single metal process

MZF 37 MZF Metal fill for single metal process

3DCUT†† 41 3DCT 3D via cut to another wafer tier

3DLAND†† 42 3DLD Landing of 3D via from another wafer tier

3DALT†† 43 3DAR Flag for alternative 3D via rule set

3DFLIP†† 44 3DFL Flag for flipped wafer tier w.r.t. final 3D stack

3DBOXC†† 45 3DBX 3D back side pad cut through buried oxide

3DBMG†† 46 3DBM 3D back side metal gate

3DPAD†† 47 3DPC Pad cut for final 3D stack

NOSLOT 50 XSLT Reserved for future use

NOFILL 51 XFIL Flag to suppress generation of fill structures

DEVR 52 DEVR Indicates device is resistor for verification and simulation

DEVL 53 DEVL Indicates device is inductor for verification and simulation

(Continued)

†† Not offered in the baseline MITLL process. ††† MZ is an alternative metal layer to be used in experimental fabrication runs that use only one layer of material.

See MITLL Low-Power FDSOI CMOS Process: Application Notes.



3.1. All Process Versions (Continued)


RED 58 RED Comment layer

GREEN 59 GRN Comment layer

BLUE 60 BLUE Comment layer

YELLOW 61 YELW Comment layer

BV0†† 62 BV0 Via from front metal 1 to back side metal 1

BM1†† 63 BM1 Back side metal 1

BV1†† 64 BV1 Back side via 1

BM2†† 65 BM2 Back side metal 2

BOGC†† 66 BOGC Back side overglass contact

BREM†† 67 BREM Back side metal remove

FLGCHAN 80 FLCH Channel region indicator for special device verification

FLG33†† 86 FL33 Flag to indicate 3.3-V device


Total Layout Design Layers: 61

†† Not offered in the baseline MITLL process.



3.2. Digital Process Versions














M1 17 M1 Metal 1



M2 20 M2 Metal 2



M3 23 M3 Metal 3




(Continued)

Note: GDS layers not listed above are used in post-submission processing or reserved for future use.

GDS layers not listed for a target process will be filtered out.

† ACTXPP suppresses normal post-submission processing. Not for general use.

See MITLL Low-Power FDSOI CMOS Process: Application Notes .



3.2. Digital Process Versions (Continued)


DEVR 52 DEVR Indicates device is resistor for verification and simulation

DEVL 53 DEVL Indicates device is inductor for verification and simulation








Total Standard Digital Process Layers: 31



†† Not offered in the baseline MITLL process.



3.3. 3D Via Process Versions














M1 17 M1 Metal 1



M2 20 M2 Metal 2



M3 23 M3 Metal 3



3DCUT 41 3DCT 3D via cut to another wafer tier

3DLAND 42 3DLD Landing of 3D via from another wafer tier

(Continued)



† Contact MITLL for more information on the proper use of this layer.



3.4. 3D Via Process Versions (Continued)


3DALT†† 43 3DAR Flag for alternative 3D via rule set

3DFLIP 44 3DFL Flag for flipped wafer tier w.r.t. final 3D stack

3DBOXC†† 45 3DBX 3D back side pad cut through buried oxide

3DBMG†† 46 3DBM 3D back side metal gate

3DPAD††† 47 3DPC Pad cut for final 3D stack





BM1†† 63 BM1 Back side metal 1 (for heat sink formation)





Total 3D Via Process Layers: 37



†† Optional layer that may not be used in all 3D processes. ††† Usually a post-submission layer.



3.4. Notes on Design Layers

3.4.1. Planar Process. The FDSOI devices in this process require a silicon island thickness of about 40 nm. These thin silicon regions are formed by global oxidation thinning.

3.4.2. Feature Bias. Minimum-width (0.18 µ m) poly features are drawn at 0.200 µ m. Exposure and etch bias will produce poly lines 0.18 ± 0.02 µ m.

To avoid formation of parasitic edge transistors, layout data will be post-processed by Lincoln Laboratory to allow for sidewall implants. This operation will create the required sidewall implant mask layers, and will adjust the size of active islands slightly to ensure that MOS channel widths correspond to the drawn data. Active island features are bloated by 0.075 µ m per side during sidewall post-processing. For more information see the section on layout post-processing for sidewall implants in MITLL Low-Power FDSOI CMOS Process: Application Notes.

3.4.3. Fill Patterns. The design layer sections above include six fill layers: ACTF, POLYF, M1F, MZF, M2F, and M3F. These are for inclusion of fill patterns on active, poly, and metal layers to achieve the required feature densities. These layers will be logically ORed with ACT, POLY, M1, MZ, M2, and M3, respectively, before physical masks for these layers are generated. These layers should only be used for fill features that do not contribute to the circuit topology of the design. They may also be used for labels.

Submitted layouts will be post-processed to create patterns of floating rectangles to fill unoccupied regions on each active, poly, and metal level. The output of this automatic generation routine for each design will be made available to its designer, with several days allowed for designer rework. To suppress this automatic fill generation, the NOFILL layer is provided. Note that submitted layouts that use the NOFILL layer must be com-pliant with layer density specifications. Density violations may affect other designs on a multiproject die; hence Lincoln Laboratory may require changes in designs that violate density rules.

See MITLL Low-Power FDSOI CMOS Process: Application Notes for more details.


MITLL Low-Power FDSOI CMOS Process: Design GuideLITHOGRAPHY STEPS

4. LITHOGRAPHY STEPS

4.1. Baseline Digital Process

Step Field Reticle Related Design Layers Description

1 Clear Active area ACT, ACTF, ACTXPP Defines silicon islands

2 Dark n-channel sidewall implant ACT, POLY, CBN, CAPP Implant n-channel island sidewalls

3 Dark p-channel sidewall implant ACT, POLY, CBP, CAPN Implant p-channel island sidewalls

4 Dark n-channel body implant CBN n-channel threshold adjust implant

5 Dark p-channel body implant CBP p-channel threshold adjust implant

6 Clear Polysilicon ACT, POLY, POLYF Defines polysilicon gates and interconnect

7 Dark n+ implant mask (NSD) NSD Implant n-channel source/drain extensions

8 Dark p+ implant mask (PSD) PSD Implant p-channel source/drain extensions

9 Dark n+ implant mask (NSD) NSD Implant n+ degenerate regions

10 Dark p+ implant mask (PSD) PSD Implant p+ degenerate regions

11 Dark Contact cut CON Defines contacts to active and poly

12 Clear Metal 1 M1, M1F Defines first-level metal interconnect

13 Dark Via 12 V12 Defines metal 1/metal 2 vias

14 Clear Metal 2 M2, M2F Defines second-level metal interconnect

15 Dark Via 23 V23 Defines metal 2/metal 3 vias

16 Clear Metal 3 M3, M3F Defines third-level metal interconnect

17 Dark Overglass OGC Defines pad openings in overglass

Total Photolithography Levels: 17

Total Reticles: 15


MITLL Low-Power FDSOI CMOS Process: Design GuideLITHOGRAPHY STEPS

4.2. Alternative Metal Z Process

Step† Field Reticle Related Design Layers Description

1 Clear Active area ACT, ACTF, ACTXPP Defines silicon islands

2 Dark n-channel sidewall implant ACT, POLY, CBN, CAPP Implant n-channel island sidewalls

3 Dark p-channel sidewall implant ACT, POLY, CBP, CAPN Implant p-channel island sidewalls

4 Dark n-channel body implant CBN n-channel threshold adjust implant

5 Dark p-channel body implant CBP p-channel threshold adjust implant

6 Clear Polysilicon ACT, POLY, POLYF Defines polysilicon gates and interconnect

7 Dark n+ implant mask (NSD) NSD Implant n-channel source/drain extensions

8 Dark p+ implant mask (PSD) PSD Implant p-channel source/drain extensions

9 Dark n+ implant mask (NSD) NSD Implant n+ degenerate regions

10 Dark p+ implant mask (PSD) PSD Implant p+ degenerate regions

11 Dark RF gate shunt TGSRF Defines tungsten gate shunt

12 Dark Contact cut CON Defines contacts to active and poly

13† Clear Metal Z MZ, MZF Single metal for reduced fabrication time

14 Dark Overglass OGC Defines pad openings in overglass

Total Photolithography Levels: 14

Total Reticles: 12

† Steps are the same as for RF process, except for metal Z step 13, which replaces steps 13–17.

See MIT Low-Power FDSOI CMOS Process: Application Notes for more information.


MITLL Low-Power FDSOI CMOS Process: Design GuideDESIGN RULES

5. DESIGN RULES

5.1. Nomenclature

In order to facilitate a concise presentation of the design rules, the following terms will be used:

• MOS channel region is the intersection of poly (POLY) and active (ACT). Exception: Where one side of a poly line receives an NSD implant and the other receives a PSD implant, that width is excluded from the MOS channel region. This excluded region is seen in body-contacted device layouts.

• Capacitor region is the intersection of poly (POLY) and active (ACT) inside CAPLCN, CAPN, or CAPP. It corresponds to the drawn area of a capacitor.

• Gate extension is poly (POLY) that extends from a transistor (ACT and POLY) for a distance of up to 0.400 µ m.

• Flag layer is a logical layer that is used to control verification or autogeneration processing of a layout, but does not directly correspond to the design data for a particular reticle.

Active Poly MOSChannelRegion

NSD PSD



5.2. Summary

Active Area Layer (ACT, ACTF, ACTXPP)

n-Channel Layer Body Implant Layer (CBN)

The ACT layer is generally used to define silicon islands corresponding to MOS active areas, capacitor bottom plates, etc.MITLL will oversize features drawn on ACT by 0.075 µm per side to accommodate the sidewall implant process.This oversized active area will be ORed with ACTF and ACTXPP to produce a single active mask.

Rule Value Description

1.01 0.600 µm Minimum contacted width (derived rule from 15.01 and 15.03)

1.02 0.500 µm Minimum width

1.03 0.600 µm Minimum spacing

1.04 0.500 µm Minimum extension of active beyond poly

1.05 Warning Active isolated from CON3.01 ACTXPP Use of ACTXPP is high risk (not subject to ACT post-submission processing)3.02 0.600 µm Minimum width 3.03 0.600 µm Minimum spacing ACTXPP to (ACT or ACTXPP)

D1.01 40% Required minimum active density within any 1 mm x 1 mm window

D1.02 60% Required maximum active density within any 1 mm x 1 mm window

NMOS transistor active area should receive this p-type implant.Autogeneration routines used in mask generation assume NMOS transistors have CBN and PMOS transistors have CBP.For deviations from that such as native or accumulation transistors see MITLL Low-Power FDSOI CMOS Process: Application Notes.


4.01 0.500 µm Minimum width4.02 0.450 µm Minimum surround of NMOS channel region

4.03 0.250 µm Minimum spacing CBN to CBN4.04 0.300 µm Minimum spacing field CBN to PMOS channel

4.05 0.400 µm Minimum spacing CBN to PMOS channel on common active4.06 Prohibited CBN–CBP overlap on (ACT and POLY)

4.07 0.250 µm Minimum CBN extension beyond NMOS H-gate arm



p-Channel Body Implant Layer (CBP)

p-Type Capacitor Bottom Plate Implant Layer (CAPP)

n-Type Capacitor Bottom Plate Implant Layer (CAPN)

PMOS transistor active area should receive this n-type implant.Autogeneration routines used in mask generation assume NMOS transistors have CBN and PMOS transistors have CBP.For deviations from that such as native or accumulation transistors see MITLL Low-Power FDSOI CMOS Process: Application Notes.

Rule Value Description5.01 0.500 µm Minimum width5.02 0.450 µm Minimum surround of PMOS channel region5.03 0.250 µm Minimum spacing CBP to CBP5.04 0.300 µm Minimum spacing field CBP to NMOS channel5.05 0.400 µm Minimum spacing CBP to NMOS channel on common active5.06 Prohibited CBP–CBN overlap on (ACT and POLY)5.07 0.250 µm Minimum CBP extension beyond PMOS H-gate arm

This is a p+ implant resulting in a doping density of about 5x1018 cm-3.

It is suitable for forming low-voltage-coefficient capacitor bottom plates with PSD-dopant gates and high-value resistors with undoped, floating poly gate.

Rule Value Description6.01 0.500 µm Minimum width6.02 0.250 µm Minimum spacing CAPP to CAPP (if not merged)6.03 0.300 µm Minimum spacing field CAPP to MOS channel6.04 0.400 µm Minimum spacing from intersection of CAPP and active to MOS channel

on common island

This is a n+ implant resulting in a doping density of about 1x1019 cm-3.

It is suitable for forming low-voltage-coefficient capacitor bottom plates with NSD-dopant gates and high-value resistors with undoped, floating poly gate.

. Value Description7.01 0.500 µm Minimum width7.02 0.250 µm Minimum spacing CAPN to CAPN (if not merged)7.03 0.300 µm Minimum spacing field CAPN to MOS channel7.04 0.400 µm Minimum spacing from intersection of CAPN and active to MOS channel

on common island



Polysilicon Gate Layer (POLY, POLYF)

This layer defines poly lines, MOS gates, capacitor top plates, etc.POLY will be ORed with POLYF to produce a single poly mask.The POLYF layer is to be used for fill patterns and labels only.When the 3.3 V flag (FLG350) is present anywhere 9.01a, 9.02a, and 9.05a apply.FLG350 IS AN OPTIONAL FLAG–NOT OFFERED IN ALL PROCESS VERSIONS

Rule Value Description9.01 0.200 µm Minimum drawn width (will be reduced in fabrication to 0.18 µm)

9.01a 0.350 µm Minimum drawn width when FLG350 present anywhere9.02 0.250 µm Minimum spacing

9.02a 0.350 µm Minimum spacing when FLG350 present anywhere9.03 0.350 µm Minimum spacing over common active9.04 0.175 µm Minimum field poly spacing to active area not within 0.4 µm of channel region9.05 0.350 µm Minimum spacing of "gate extension poly" (poly extending from a transistor and within 0.4 µm of the channel region) to active area

9.06 0.175 µm Minimum gate extension poly spacing to contact surround active area (for case of "dogbone" transistors)

9.07 0.400 µm Minimum extension beyond active area9.08 0.350 µm Minimum surround by active when used as capacitor top plate9.09 0.300 µm Minimum surround by CAPP, CAPN, or CAPLCN when used as capacitor top plate9.10 Prohibited POLY on ACT outside of NSD or PSD9.11 Warning POLY outside of NSD or PSD not recommended9.12 Warning POLY isolated from CON

D9.01 10% Required minimum POLY/POLYF density within 1 mm x 1 mm windowD9.02 20% Required maximum POLY/POLYF density within 1 mm x 1 mm window



n+ Implant Layer (NSD)

This layer defines the NMOS source/drain and PMOS body contact implant.Use this layer for n+ degenerate doping to form ohmic contacts and to dope poly.

Rule Value Description12.01 0.500 µm Minimum width12.02 0.400 µm Minimum surround on NMOS channel region except in body contact region12.03 0.200 µm Minimum extension beyond active area12.04 0.250 µm Minimum spacing NSD to NSD (if not merged)12.05 0.200 µm Minimum spacing field NSD to non-NSD active area12.06 0.400 µm Minimum spacing field NSD to PMOS channel region12.07 0.400 µm Minimum spacing from intersection of non-body contact NSD and active to

PMOS channel on common island12.08 0.100 µm Minimum NSD overlap on poly gate (This rule applies to body contact structures,

where the gate receives NSD on one side and PSD on the other. If the poly width is large enough, a 0.150-µm overlap is strongly recommended.)

12.09 Prohibited NSD-PSD overlap on active or poly12.10 0.550 µm Minimum surround on n-type capacitor top plate poly12.11 Prohibited Poly over active without NSD or PSD. (However, undoped, floating poly can be

useful as a silicide block. See MITLL Low-Power FDSOI CMOS Process: Application Notes .)

12.12 Warning Poly anywhere without NSD or PSD. PSD is preferable for lower silicide resistance.



p+ Implant Layer (PSD)

This layer defines the PMOS source/drain and NMOS body contact implant.Use this layer for p+ degenerate doping to form ohmic contacts and to dope poly.

Rule Value Description13.01 0.500 µm Minimum width13.02 0.400 µm Minimum surround on PMOS channel region except in body contact region13.03 0.200 µm Minimum extension beyond active area13.04 0.250 µm Minimum spacing PSD to PSD (if not merged)13.05 0.200 µm Minimum spacing field PSD to non-PSD active area13.06 0.400 µm Minimum spacing field PSD to NMOS channel region13.07 0.400 µm Minimum spacing from intersection of non-body contact PSD and active to

NMOS channel on common island13.08 0.100 µm Minimum PSD overlap on poly gate (This rule applies to body contact structures,

where the gate receives PSD on one side and NSD on the other. If the poly width is great enough, a 0.150-µ m overlap is strongly recommended.)

13.09 Prohibited PSD-NSD overlap on active or poly13.10 0.550 µm Minimum surround on p-type capacitor top plate poly13.11 Prohibited Poly over active without NSD or PSD. (However, undoped, floating poly can be





Contact Cut Layer (CON)

Metal 1 Layer (M1, M1F)

Use this layer to define contact cuts to the active and poly areas.

Rule Value Description15.01 0.250 µm square Width (only size and shape allowed)15.02 0.350 µm Minimum spacing15.02a >0.500 µm warning Recommended minimum spacing for 5 to 24 closely placed CON15.02b >0.750 µm warning Recommended minimum spacing for 25 or more closely placed CON15.03 0.175 µm Minimum ACT surround if contacting to ACT15.04 0.175 µm Minimum POLY surround if contacting to POLY15.05 0.350 µm Minimum spacing to POLY gate15.06 0.175 µm Minimum (ACT and POLY) surround if contacting to POLY over ACT15.07 0.175 µm Minimum NSD OR PSD surround15.08 Prohibited CON not over POLY or ACT15.09 Required CON should be provided to poly even if TGSRF also provides metal

connection to poly. (Undoped, floating poly can be useful as a silicide block. See MITLL Low-Power FDSOI CMOS Process: Application Notes .

Note: In this figure the region receiving NSD also illustrates the case where PSD is used.

This layer defines the first metal level.The M1 layer will be ORed with M1F to produce a single metal 1 mask.The M1F layer is to be used for fill patterns and labels only.Note: Also see Metal Z (MZ, MZF) Rule 36.xx

Rule Value Description17.01 0.250 µm Minimum width17.02 0.350 µm Minimum spacing17.03 0.150 µm Minimum surround on contact cut17.04 Required Metal 1 over all TGSRF

D17.01 30% Required minimum metal 1 density within any 1 mm x 1 mm windowD17.02 50% Required maximum metal 1 density within any 1 mm x 1 mm window



Metal 1/Metal 2 Via Layer (V12)



This layer defines vias between the first and second metal levels.

Rule Value Description19.01 0.300 µm square Width (only size and shape allowed)19.02 0.400 µm Minimum spacing19.02a >0.500 µm warning Recommended minimum spacing for 5 to 24 closely placed V1219.02b >0.750 µm warning Recommended minimum spacing for 25 or more closely placed V1219.03 0.150 µm Minimum metal 1 surround19.04 Allowed Stacked via V12 on contact (metal 1 must be present)19.05 Allowed Stacked via V12 on TGSRF (metal 1 must be present)

This layer defines the second metal level.The M2 layer will be ORed with M2F to produce a single metal 2 mask.The M2F layer is to be used for fill patterns and labels only.

Rule Value Description20.01 0.250 µm Minimum width20.02 0.350 µm Minimum spacing20.03 0.150 µm Minimum surround on via V12


This layer defines vias between the second and third metal levels.OPTIONAL LAYER–NOT OFFERED IN ALL PROCESS VERSIONS

Rule Value Description22.01 0.300 µm square Width (only size and shape allowed)22.02 0.400 µm Minimum spacing22.02a >0.500 µm warning Recommended minimum spacing for 5 to 24 closely placed V2322.02b >0.750 µm warning Recommended minimum spacing for 25 or more closely placed V2322.03 0.150 µm Minimum metal 2 surround22.04 Allowed Stacked via V23 on V12 (intervening metals must be present)




Overglass Pad Cut Layer (OGC)

Metal Z Layer, Alternative Single Metal (MZ, MZF)

This layer defines the third metal level.The M3 layer will be ORed with M3F to produce a single metal 3 mask.The M3F layer is to be used for fill patterns and labels only.



This layer defines pad cuts in the overglass, which allow top-level metal pads to be contacted.

Rule Value Description34.01 1.000 µm Spacing in from top-level metal pad edge34.02 Prohibited OGC not over top-level metal

There is no minimum width rule; extremely small widths are unlikely to resolve.

This layer defines an alternative single metal layer to allow testing without multiple metal layer processing.MZ is an alternative to, not a part of, the normal metal/via stack. (M1 is still required for normal wafer processing.) If used, MZ must satisify all M1 rules and surround OGC by 1.000 µ m.See “Antenna Effects and the Metal Z Layer” in MIT Low-Power FDSOI CMOS Process: Application Notes.

OPTIONAL LAYER–NOT OFFERED IN ALL PROCESS VERSIONS

Rule Value Description36.01 0.250 µm Minimum width36.02 0.350 µm Minimum spacing36.03 0.150 µm Minimum surround on contact cut36.04 Required MZ over all TGSRF

D36.01 30% Required minimum metal Z density within any 1 mm x 1 mm windowD36.02 50% Required maximum metal Z density within any 1 mm x 1 mm window



3D Via Cut to Another Wafer Tier (3DCUT)

3DCUT defines 3D via cuts to another wafer tier.The term "tier" refers to a single "conventionally" fabricated wafer. When two tiers are stacked, 3DCUT defines the 3D via starting point on the higher numbered tier while 3DLAND indicates the 3D via stopping location on a metal layer of the lower numbered tier. The 3D via originates on the back side of the cut tier. Its dimensions on the lower numbered tier are defined by a "doughnut" opening in the cut tier's highest level metal (required).OPTIONAL LAYER–NOT OFFERED IN ALL PROCESS VERSIONS

Rule Value Description41.01 1.750 µm square 3DCUT width (only size and shape allowed)41.02 1.800 µm Minimum spacing 3DCUT to 3DCUT on the same tier sharing a net41.03 3.850 µm Minimum spacing 3DCUT to 3DCUT on the same tier not sharing a net41.04a >3.750 µm warning Recommended minimum spacing for 5 to 24 closely placed 3DCUT41.04b >5.800 µm warning Recommended minimum spacing for 25 or more closely placed 3DCUT41.05 0.500 µm Minimum top-level metal extension beyond 3DCUT41.06 1.500 µm square Top-level metal doughnut opening width (only size and shape allowed)41.07 0.250 µm 3DCUT surround of top-level metal doughnut opening (only surround allowed)41.08 2.800 µm Minimum spacing 3DCUT to 3DLAND on the same tier 41.09 1.550 µm Minimum spacing 3DCUT to POLY/POLYF41.10 1.550 µm Minimum spacing 3DCUT to active41.11 1.250 µm Minimum spacing 3DCUT to all non-top-level metals41.12 1.000 µm Minimum top-level metal width for wire connecting to top-level metal doughnut41.13 Prohibited 3DCUT not coincident with 3DLAND on next lower numbered tier41.14 Prohibited 3DCUT without top-level metal doughnut



3D Via Landing from Another Wafer Tier (3DLAND)

3DLAND defines 3D via landings from another wafer tier.The term "tier" refers to a single "conventionally" fabricated wafer. When two tiers are stacked, 3DCUT defines the 3D via starting point on the higher numbered tier while 3DLAND indicates the 3D via stopping location on a metal layer of the lower numbered tier.The 3D via penetrates the "land" wafer from the back side and stops on the first metal layer unless 3DFLIP is present on the landing tier.The presence of 3DFLIP anywhere on the tier's layout indicates that when assembled with other tiers it will be flipped with the 3D via stopping on the top-level metal (not reaching poly or active).OPTIONAL LAYER–NOT OFFERED IN ALL PROCESS VERSIONS

Rule Value Description42.01 1.750 µm square 3DLAND width (only size and shape allowed)42.02 1.800 µm Minimum spacing 3DLAND to 3DLAND on the same tier and on contiguous

metal landing42.03 3.850 µm Minimum spacing 3DLAND to 3DLAND on the same tier and on isolated

metal landing42.04a >3.750 µm warning Recommended minimum spacing for 5 to 24 closely placed 3DLAND42.04b >5.800 µm warning Recommended minimum spacing for 25 or more closely placed 3DLAND42.05 1.625 µm Minimum metal surround of 3DLAND, first metal without 3DFLIP, top-level metal

with 3DFLIP42.06 Prohibited 3DLAND outside of metal landing, first metal without 3DFLIP, top-level metal

with 3DFLIP42.07 Prohibited 3DLAND not coincident with 3DCUT in next higher numbered tier42.08 2.600 µm Minimum space 3DLAND to POLY on non-3DFLIP tier42.09 2.600 µm Minimum space 3DLAND to active on non-3DFLIP tier



3D Via Cut to Another Wafer Tier (3DCUT)—ALTERNATE RULE SET

These rules apply to 3D via structures drawn within 3DALT. They form a more aggressive rule set that is not supported for all 3D lots. See MITLL Low-Power FDSOI CMOS Process: Application Notes .


Rule Value DescriptionALT41.01 1.750 µm square 3DCUT width (only size and shape allowed) inside 3DALTALT41.02 1.800 µm Minimum spacing 3DCUT to 3DCUT on the same tier sharing a net inside 3DALTALT41.03 1.800 µm Minimum spacing 3DCUT to 3DCUT on the same tier not sharing a net inside 3DALT

ALT41.04a >3.750 µm warning Recommended minimum spacing for 5 to 24 closely placed 3DCUT inside 3DALTALT41.04b >5.800 µm warning Recommended minimum spacing for 25 or more closely placed 3DCUT inside 3DALTALT41.05 0.500 µm Minimum top-level metal extension beyond 3DCUT inside 3DALTALT41.06 1.500 µm square Top-level metal doughnut opening width (only size and shape allowed) inside 3DALTALT41.07 0.250 µm 3DCUT surround of top-level metal doughnut opening (only surround allowed)

inside 3DALTALT41.08 1.800 µm Minimum spacing 3DCUT to 3DLAND on the same tier inside 3DALTALT41.09 1.550 µm Minimum spacing 3DCUT to POLY/POLYF inside 3DALTALT41.10 1.550 µm Minimum spacing 3DCUT to active inside 3DALTALT41.11 1.250 µm Minimum spacing 3DCUT to all non-top-level metals inside 3DALTALT41.12 1.000 µm Minimum top-level metal width for wire connecting to top-level metal doughnut

inside 3DALTALT41.13 Prohibited 3DCUT not coincident with 3DLAND on next lower numbered tier inside 3DALTALT41.14 Prohibited 3DCUT without top-level metal doughnut inside 3DALT



3D Via Landing from Another Wafer Tier (3DLAND)—ALTERNATE RULE SET

Flag for Alternate 3D Via Rule Set (3DALT)



Rule Value DescriptionALT42.01 1.750 µm square 3DLAND width (only size and shape allowed) inside 3DALTALT42.02 1.800 µm Minimum spacing 3DLAND to 3DLAND on the same tier and on contiguous

metal landing inside 3DALTALT42.03 1.800 µm Minimum spacing 3DLAND to 3DLAND on the same tier and on isolated

metal landing inside 3DALTALT42.04a >3.750 µm warning Recommended minimum spacing for 5 to 24 closely placed 3DLAND inside 3DALTALT42.04b >5.800 µm warning Recommended minimum spacing for 25 or more closely placed 3DLAND inside 3DALTALT42.05 0.625 µm Minimum metal surround of 3DLAND, first metal without 3DFLIP, top-level metal

with 3DFLIP inside 3DALTALT42.06 Prohibited 3DLAND outside of metal landing, first metal without 3DFLIP, top-level metal

with 3DFLIP inside 3DALTALT42.07 Prohibited 3DLAND not coincident with 3DCUT in next higher numbered tier inside 3DALTALT42.08 1.600 µm Minimum space 3DLAND to POLY on non-3DFLIP tier inside 3DALTALT42.09 1.600 µm Minimum space 3DLAND to active on non-3DFLIP tier inside 3DALT

This is a flag layer that allows alternate 3D via rules inside a defined region.OPTIONAL LAYER–NOT OFFERED IN ALL PROCESS VERSIONS

Rule Value Description43.01 Prohibited Use of 3DALT not supported without permission. Contact MITLL for more information.



Flag for Flipped Wafer w.r.t. Final 3D Stack (3DFLIP)

3D Back Side Cut Through Buried Oxide (3DBOXC)

Pad Cut for Final 3D Stack (3DPAD)

Additional Layers: Flag and Comment (Markup)

NOFILL

DEVR

RED

This is a flag layer that is used to indicate that during 3D assembly, a particular tier is flipped with respect to the final 3D stack.Tiers requiring 3DFLIP flags shall be determined by MITLL.OPTIONAL LAYER–NOT OFFERED IN ALL PROCESS VERSIONS

Rule Value Description44.01 Prohibited 3DCUT on a 3DFLIP tier

3DBOXC defines a cut made through the buried oxide under the silicon of a wafer tier that has been integrated into a 3D stack.OPTIONAL LAYER–NOT OFFERED IN ALL PROCESS VERSIONS

Rule Value Description45.xx No rules available

3DPAD defines pad cuts for the final assembled 3D stack.These are normally generated during post-submission processing (derived from OGC layer).Do not use without consulting with MITLL.OPTIONAL LAYER–NOT OFFERED IN ALL PROCESS VERSIONS


(Comment layers are included as a design aid and have no effect on the layout other than the cell extents.)

This layer suppresses automatic fill generation. In regions not covered by NOFILL, fill structures are automatically generated by MITLL to force compliance with layer density rules. See MITLL Low-Power FDSOI CMOS Process: Application Notes for details.

Warning: When NOFILL is used the designer takes responsiblity for all layer density specifications in that region of use.

Reserved for future use

Comment layer



GREEN

BLUE

YELLOW

Comment layer

Comment layer

Comment layer



Active Area Layer (ACT, ACTF, ACTXPP)

The ACT layer is generally used to define silicon islands corresponding to MOS active areas, capacitor bottom plates, etc.MITLL will oversize features drawn on ACT by 0.075 µm per side to accommodate the sidewall implant process.This oversized active area will be ORed with ACTF and ACTXPP to produce a single active mask.


1.01 0.600 µm Minimum contacted width (derived rule from 15.01 and 15.03)

1.02 0.500 µm Minimum width

1.03 0.600 µm Minimum spacing1.04 0.500 µm Minimum extension of active beyond poly

1.05 Warning Active isolated from CON3.01 ACTXPP Use of ACTXPP is high risk (not subject to ACT post-submission processing)3.02 0.600 µm Minimum width 3.03 0.600 µm Minimum spacing ACTXPP to (ACT or ACTXPP)

D1.01 40% Required minimum active density within any 1 mm x 1 mm window

D1.02 60% Required maximum active density within any 1 mm x 1 mm window

RULE 1.01

(0.600 µm)

RULE 1.02

(0.500 µm)

RULE 1.03

(0.600 µm)

RULE 1.04

(0.500 µm)

Same spacing:

NMOS-to-NMOS

PMOS-to-PMOS

NMOS-to-PMOS

PolyActive Contact Cut



n-Channel Layer Body Implant Layer (CBN)

NMOS transistor active area should receive this p-type implant.Autogeneration routines used in mask generation assume NMOS transistors have CBN and PMOS transistors have CBP.For deviations from that such as native or accumulation transistors see MITLL Low-Power FDSOI CMOS Process: Application Notes.


4.01 0.500 µm Minimum width4.02 0.450 µm Minimum surround of NMOS channel region

4.03 0.250 µm Minimum spacing CBN to CBN4.04 0.300 µm Minimum spacing field CBN to PMOS channel

4.05 0.400 µm Minimum spacing CBN to PMOS channel on common active4.06 Prohibited CBN–CBP overlap on (ACT and POLY)

4.07 0.250 µm Minimum CBN extension beyond NMOS H-gate arm

RULE 4.02

(0.450 µm)

RULE 4.03

(If <0.250 µm,

merge features)RULE 4.04

(0.300 µm)

RULE 4.05

(0.400 µm)

RULE 4.01

(0.500 µm)

RULE 4.07

(0.250 µm)

Active CBN Poly Contact Cut

PMOS



p-Channel Body Implant Layer (CBP)

PMOS transistor active area should receive this n-type implant.Autogeneration routines used in mask generation assume NMOS transistors have CBN and PMOS transistors have CBP.For deviations from that such as native or accumulation transistors see MITLL Low-Power FDSOI CMOS Process: Application Notes.

Rule Value Description5.01 0.500 µm Minimum width5.02 0.450 µm Minimum surround of PMOS channel region5.03 0.250 µm Minimum spacing CBP to CBP5.04 0.300 µm Minimum spacing field CBP to NMOS channel5.05 0.400 µm Minimum spacing CBP to NMOS channel on common active5.06 Prohibited CBP–CBN overlap on (ACT and POLY)5.07 0.250 µm Minimum CBP extension beyond PMOS H-gate arm

Active CBP Poly Contact Cut

RULE 5.02

(0.450 µm)

RULE 5.03

(If <0.250 µm,

merge features)RULE 5.04

(0.300 µm)

RULE 5.05

(0.400 µm)

RULE 5.01

(0.500 µm)

RULE 5.07

(0.250 µm)

NMOS



p-Type Capacitor Bottom Plate Implant Layer (CAPP)

This is a p+ implant resulting in a doping density of about 5x1018 cm-3.

It is suitable for forming low-voltage-coefficient capacitor bottom plates with PSD-dopant gates and high-value resistors with undoped, floating poly gate.

Rule Value Description6.01 0.500 µm Minimum width6.02 0.250 µm Minimum spacing CAPP to CAPP (if not merged)6.03 0.300 µm Minimum spacing field CAPP to MOS channel6.04 0.400 µm Minimum spacing from intersection of CAPP and active to MOS channel

on common island


CAPP

RULE 6.01

(0.500 µm)

RULE 6.03

(0.300 µm)

RULE 6.02

(If <0.250 µm,

merge features)

MOS

MO

S

RULE 6.04

(0.400 µm)



n-Type Capacitor Bottom Plate Implant Layer (CAPN)

This is a n+ implant resulting in a doping density of about 1x1019 cm-3.

It is suitable for forming low-voltage-coefficient capacitor bottom plates with NSD-dopant gates and high-value resistors with undoped, floating poly gate.

. Value Description7.01 0.500 µm Minimum width7.02 0.250 µm Minimum spacing CAPN to CAPN (if not merged)7.03 0.300 µm Minimum spacing field CAPN to MOS channel7.04 0.400 µm Minimum spacing from intersection of CAPN and active to MOS channel

on common island


CAPN

RULE 7.01

(0.500 µm)

RULE 7.03

(0.300 µm)

RULE 7.02

(If <0.250 µm,

merge features)

MOS

MO

S

RULE 7.04

(0.400 µm)



Polysilicon Gate Layer (POLY, POLYF)

This layer defines poly lines, MOS gates, capacitor top plates, etc.POLY will be ORed with POLYF to produce a single poly mask.The POLYF layer is to be used for fill patterns and labels only.When the 3.3 V flag (FLG350) is present anywhere 9.01a, 9.02a, and 9.05a apply.FLG350 IS AN OPTIONAL FLAG–NOT OFFERED IN ALL PROCESS VERSIONS

Rule Value Description9.01 0.200 µm Minimum drawn width (will be reduced in fabrication to 0.18 µm)

9.01a 0.350 µm Minimum drawn width when FLG350 present anywhere9.02 0.250 µm Minimum spacing

9.02a 0.350 µm Minimum spacing when FLG350 present anywhere9.03 0.350 µm Minimum spacing over common active9.04 0.175 µm Minimum field poly spacing to active area not within 0.4 µm of channel region9.05 0.350 µm Minimum spacing of "gate extension poly" (poly extending from a transistor and within 0.4 µm of the channel region) to active area

9.06 0.175 µm Minimum gate extension poly spacing to contact surround active area (for case of "dogbone" transistors)

9.07 0.400 µm Minimum extension beyond active area9.08 0.350 µm Minimum surround by active when used as capacitor top plate9.09 0.300 µm Minimum surround by CAPP, CAPN, or CAPLCN when used as capacitor top plate9.10 Prohibited POLY on ACT outside of NSD or PSD9.11 Warning POLY outside of NSD or PSD not recommended9.12 Warning POLY isolated from CON

D9.01 10% Required minimum POLY/POLYF density within 1 mm x 1 mm windowD9.02 20% Required maximum POLY/POLYF density within 1 mm x 1 mm window



Polysilicon Gate Layer (POLY, POLYF) (Continued)

Contact Cut

Active Poly

RULE 9.02

(0.250 µm)

RULE 9.05

(0.350 µm)

RULE 9.04

(0.175 µm)

RULE 9.07

(0.400 µm)

RULE 9.03

(0.350 µm)RULE 9.01

(0.200 µm)

RULE 9.06

(0.175 µm)

0.4 µm Surround of Channel Region–Gate Extension Connects to Channel

Inside This Region

Contact Cut

Poly

Active

CAPPor CAPN

or CAPLCN

RULE 9.09

(0.300 µm)

RULE 9.08

(0.350 µm)



n+ Implant Layer (NSD)

This layer defines the NMOS source/drain and PMOS body contact implant.Use this layer for n+ degenerate doping to form ohmic contacts and to dope poly.

Rule Value Description12.01 0.500 µm Minimum width12.02 0.400 µm Minimum surround on NMOS channel region except in body contact region12.03 0.200 µm Minimum extension beyond active area12.04 0.250 µm Minimum spacing NSD to NSD (if not merged)12.05 0.200 µm Minimum spacing field NSD to non-NSD active area12.06 0.400 µm Minimum spacing field NSD to PMOS channel region12.07 0.400 µm Minimum spacing from intersection of non-body contact NSD and active to

PMOS channel on common island12.08 0.100 µm Minimum NSD overlap on poly gate (This rule applies to body contact structures,

where the gate receives NSD on one side and PSD on the other. If the poly width is large enough, a 0.150-µm overlap is strongly recommended.)

12.09 Prohibited NSD-PSD overlap on active or poly12.10 0.550 µm Minimum surround on n-type capacitor top plate poly12.11 Prohibited Poly over active without NSD or PSD. (However, undoped, floating poly can be





n+ Implant Layer (NSD) (Continued)

Poly Contact Cut

NSD

RULE 12.02

(0.400 µm)

RULE 12.03

(0.200 µm)

RULE 12.01

(0.500 µm)

RULE 12.05

(0.200 µm)

RULE 12.08

(0.100 µm)

PMOS

PMOS

NMOS

Active

RULE 12.04

(If <0.250 µm,

merge features)

Poly Contact Cut

NSD Active

RULE 12.07

(0.400 µm)

RULE 12.06

(0.400 µm)

RULE 12.10

(0.550 µm)

Capacitor

PMOS



p+ Implant Layer (PSD)

This layer defines the PMOS source/drain and NMOS body contact implant.Use this layer for p+ degenerate doping to form ohmic contacts and to dope poly.

Rule Value Description13.01 0.500 µm Minimum width13.02 0.400 µm Minimum surround on PMOS channel region except in body contact region13.03 0.200 µm Minimum extension beyond active area13.04 0.250 µm Minimum spacing PSD to PSD (if not merged)13.05 0.200 µm Minimum spacing field PSD to non-PSD active area13.06 0.400 µm Minimum spacing field PSD to NMOS channel region13.07 0.400 µm Minimum spacing from intersection of non-body contact PSD and active to

NMOS channel on common island13.08 0.100 µm Minimum PSD overlap on poly gate (This rule applies to body contact structures,

where the gate receives PSD on one side and NSD on the other. If the poly width is great enough, a 0.150-µ m overlap is strongly recommended.)

13.09 Prohibited PSD-NSD overlap on active or poly13.10 0.550 µm Minimum surround on p-type capacitor top plate poly13.11 Prohibited Poly over active without NSD or PSD. (However, undoped, floating poly can be





p+ Implant Layer (PSD) (Continued)

Poly Contact Cut

PSD

RULE 13.02

(0.400 µm)

RULE 13.03

(0.200 µm)

RULE 13.01

(0.500 µm)

RULE 13.05

(0.200 µm)

RULE 13.08

(0.100 µm)

NMOS

NMOS

PMOS

Active

RULE 13.04

(If <0.250 µm,

merge features)

Poly Contact Cut

PSD Active

RULE 13.07

(0.400 µm)

RULE 13.06

(0.400 µm)

RULE 13.10

(0.550 µm)

Capacitor

NMOS



Contact Cut Layer (CON)

Use this layer to define contact cuts to the active and poly areas.

Rule Value Description15.01 0.250 µm square Width (only size and shape allowed)15.02 0.350 µm Minimum spacing15.02a >0.500 µm warning Recommended minimum spacing for 5 to 24 closely placed CON15.02b >0.750 µm warning Recommended minimum spacing for 25 or more closely placed CON15.03 0.175 µm Minimum ACT surround if contacting to ACT15.04 0.175 µm Minimum POLY surround if contacting to POLY15.05 0.350 µm Minimum spacing to POLY gate15.06 0.175 µm Minimum (ACT and POLY) surround if contacting to POLY over ACT15.07 0.175 µm Minimum NSD OR PSD surround15.08 Prohibited CON not over POLY or ACT15.09 Required CON should be provided to poly even if TGSRF also provides metal

connection to poly. (Undoped, floating poly can be useful as a silicide block. See MITLL Low-Power FDSOI CMOS Process: Application Notes .

Note: In this figure the region receiving NSD also illustrates the case where PSD is used.

Contact Cut

PolyActive NSD Metal 1

RULE 15.06

(0.175 µm)

RULES 15.04, 15.07

(0.175 µm)

RULE 15.05

(0.350 µm)

RULE 15.03

(0.175 µm)

RULE 15.02

(0.350 µm)

RULE 15.02a

(>0.500 µm,

5 to 24 contacts)–

RULE 15.02b

(>0.750 µm,

>25 contacts)–

RULE 15.01

(0.250 x 0.250 µm)

(Square)




This layer defines the first metal level.The M1 layer will be ORed with M1F to produce a single metal 1 mask.The M1F layer is to be used for fill patterns and labels only.Note: Also see Metal Z (MZ, MZF) Rule 36.xx

Rule Value Description17.01 0.250 µm Minimum width17.02 0.350 µm Minimum spacing17.03 0.150 µm Minimum surround on contact cut17.04 Required Metal 1 over all TGSRF


PolyActive Metal 1Contact Cut

RULE 17.02

(0.350 µm)

RULE 17.03

(0.150 µm)

RULE 17.01

(0.250 µm)




This layer defines vias between the first and second metal levels.

Rule Value Description19.01 0.300 µm square Width (only size and shape allowed)19.02 0.400 µm Minimum spacing19.02a >0.500 µm warning Recommended minimum spacing for 5 to 24 closely placed V1219.02b >0.750 µm warning Recommended minimum spacing for 25 or more closely placed V1219.03 0.150 µm Minimum metal 1 surround19.04 Allowed Stacked via V12 on contact (metal 1 must be present)19.05 Allowed Stacked via V12 on TGSRF (metal 1 must be present)


Metal 1 V12

RULE 19.03

(0.150 µm)

RULE 19.01

(0.300 x 0.300 µm)

(Square)

RULE 19.02

(0.400 µm)

RULE 19.02a

(>0.500 µm,

5 to 24 V12)–

RULE 19.02b

(>0.750 µm,

25 or more V12)–




This layer defines the second metal level.The M2 layer will be ORed with M2F to produce a single metal 2 mask.The M2F layer is to be used for fill patterns and labels only.



V12 Metal 2

RULE 20.03

(0.150 µm)RULE 20.02

(0.350 µm)

RULE 20.01

(0.250 µm)




This layer defines vias between the second and third metal levels.OPTIONAL LAYER–NOT OFFERED IN ALL PROCESS VERSIONS

Rule Value Description22.01 0.300 µm square Width (only size and shape allowed)22.02 0.400 µm Minimum spacing22.02a >0.500 µm warning Recommended minimum spacing for 5 to 24 closely placed V2322.02b >0.750 µm warning Recommended minimum spacing for 25 or more closely placed V2322.03 0.150 µm Minimum metal 2 surround22.04 Allowed Stacked via V23 on V12 (intervening metals must be present)

V23 Metal 2

RULE 22.02

(0.400 µm)

RULE 22.02a

(>0.500 µm,

5 to 24 V23)–

RULE 22.02b

(>0.750 µm,

25 or more V23)–

RULE 22.01

(0.300 x 0.300 µm)

(Square)

RULE 22.03

(0.150 µm)




Overglass Pad Cut Layer (OGC)

(See M2 illustration)This layer defines the third metal level.The M3 layer will be ORed with M3F to produce a single metal 3 mask.The M3F layer is to be used for fill patterns and labels only.



This layer defines pad cuts in the overglass, which allow top-level metal pads to be contacted.

Rule Value Description34.01 1.000 µm Spacing in from top-level metal pad edge34.02 Prohibited OGC not over top-level metal

There is no minimum width rule; extremely small widths are unlikely to resolve.

RULE 34.01

(1.00 µm)

Top-Level Metal Pad

Pad Cut



Metal Z Layer, Alternative Single Metal (MZ, MZF)

This layer defines an alternative single metal layer to allow testing without multiple metal layer processing.MZ is an alternative to, not a part of, the normal metal/via stack. (M1 is still required for normal wafer processing.) If used, MZ must satisify all M1 rules and surround OGC by 1.000 µ m.See “Antenna Effects and the Metal Z Layer” in MIT Low-Power FDSOI CMOS Process: Application Notes.

OPTIONAL LAYER–NOT OFFERED IN ALL PROCESS VERSIONS

Rule Value Description36.01 0.250 µm Minimum width36.02 0.350 µm Minimum spacing36.03 0.150 µm Minimum surround on contact cut36.04 Required MZ over all TGSRF

D36.01 30% Required minimum metal Z density within any 1 mm x 1 mm windowD36.02 50% Required maximum metal Z density within any 1 mm x 1 mm window



3D Via Cut to Another Wafer Tier (3DCUT)


Rule Value Description41.01 1.750 µm square 3DCUT width (only size and shape allowed)41.02 1.800 µm Minimum spacing 3DCUT to 3DCUT on the same tier sharing a net41.03 3.850 µm Minimum spacing 3DCUT to 3DCUT on the same tier not sharing a net41.04a >3.750 µm warning Recommended minimum spacing for 5 to 24 closely placed 3DCUT41.04b >5.800 µm warning Recommended minimum spacing for 25 or more closely placed 3DCUT41.05 0.500 µm Minimum top-level metal extension beyond 3DCUT41.06 1.500 µm square Top-level metal doughnut opening width (only size and shape allowed)41.07 0.250 µm 3DCUT surround of top-level metal doughnut opening (only surround allowed)41.08 2.800 µm Minimum spacing 3DCUT to 3DLAND on the same tier 41.09 1.550 µm Minimum spacing 3DCUT to POLY/POLYF41.10 1.550 µm Minimum spacing 3DCUT to active41.11 1.250 µm Minimum spacing 3DCUT to all non-top-level metals41.12 1.000 µm Minimum top-level metal width for wire connecting to top-level metal doughnut41.13 Prohibited 3DCUT not coincident with 3DLAND on next lower numbered tier41.14 Prohibited 3DCUT without top-level metal doughnut

Poly

Active

Top-LevelMetal

3D Cut“Doughnut”Cut

OtherMetal

3DLAND

RULE 41.09

(1.550 µm)

RULE 41.08

(2.800 µm)RULE 41.08

(1.075 µm)

RULE 41.02

(1.800 µm)

RULE 41.07

(0.250 µm)

RULE 41.05

(0.500 µm)

RULE 41.01

(1.750 µm)

(Square)

RULE 41.06

(1.500 µm)

(Square)

RULE 41.11

(1.250 µm)



3D Via Landing from Another Wafer Tier (3DLAND)


Rule Value Description42.01 1.750 µm square 3DLAND width (only size and shape allowed)42.02 1.800 µm Minimum spacing 3DLAND to 3DLAND on the same tier and on contiguous

metal landing42.03 3.850 µm Minimum spacing 3DLAND to 3DLAND on the same tier and on isolated

metal landing42.04a >3.750 µm warning Recommended minimum spacing for 5 to 24 closely placed 3DLAND42.04b >5.800 µm warning Recommended minimum spacing for 25 or more closely placed 3DLAND42.05 1.625 µm Minimum metal surround of 3DLAND, first metal without 3DFLIP, top-level metal

with 3DFLIP42.06 Prohibited 3DLAND outside of metal landing, first metal without 3DFLIP, top-level metal

with 3DFLIP42.07 Prohibited 3DLAND not coincident with 3DCUT in next higher numbered tier42.08 2.600 µm Minimum space 3DLAND to POLY on non-3DFLIP tier42.09 2.600 µm Minimum space 3DLAND to active on non-3DFLIP tier

3DLAND PolyActive LandingMetal

RULE 41.01

(2.500 µm)

(Square)

RULE 42.03

(3.850 µm)

RULE 42.05

(1.625 µm)

RULE 42.08

(2.600 µm)

RULE 42.09

(2.600 µm)

RULE 42.02

(1.800 µm)

RULE 42.01

(1.750 µm)

(Square)



3D Via Cut to Another Wafer Tier (3DCUT)—ALTERNATE RULE SET



Rule Value DescriptionALT41.01 1.750 µm square 3DCUT width (only size and shape allowed) inside 3DALTALT41.02 1.800 µm Minimum spacing 3DCUT to 3DCUT on the same tier sharing a net inside 3DALTALT41.03 1.800 µm Minimum spacing 3DCUT to 3DCUT on the same tier not sharing a net inside 3DALT

ALT41.04a >3.750 µm warning Recommended minimum spacing for 5 to 24 closely placed 3DCUT inside 3DALTALT41.04b >5.800 µm warning Recommended minimum spacing for 25 or more closely placed 3DCUT inside 3DALTALT41.05 0.500 µm Minimum top-level metal extension beyond 3DCUT inside 3DALTALT41.06 1.500 µm square Top-level metal doughnut opening width (only size and shape allowed) inside 3DALTALT41.07 0.250 µm 3DCUT surround of top-level metal doughnut opening (only surround allowed)

inside 3DALTALT41.08 1.800 µm Minimum spacing 3DCUT to 3DLAND on the same tier inside 3DALTALT41.09 1.550 µm Minimum spacing 3DCUT to POLY/POLYF inside 3DALTALT41.10 1.550 µm Minimum spacing 3DCUT to active inside 3DALTALT41.11 1.250 µm Minimum spacing 3DCUT to all non-top-level metals inside 3DALTALT41.12 1.000 µm Minimum top-level metal width for wire connecting to top-level metal doughnut

inside 3DALTALT41.13 Prohibited 3DCUT not coincident with 3DLAND on next lower numbered tier inside 3DALTALT41.14 Prohibited 3DCUT without top-level metal doughnut inside 3DALT



3D Via Cut to Another Wafer Tier (3DCUT)—ALTERNATE RULE SET (Continued)

Poly

Active

Top-LevelMetal

3D Cut“Doughnut”Cut

OtherMetal

3DLAND

RULE 41.09

(1.550 µm)

RULE 41.08

(1.075 µm)

RULE 41.02

(1.800 µm)

RULE 41.07

(0.250 µm)

RULE 41.05

(0.500 µm)

RULE 41.01

(1.750 µm)

(Square)

RULE 41.06

(1.500 µm)

(Square)

RULE 41.11

(1.250 µm)

RULE 41.08

(1.800 µm)



3D Via Landing from Another Wafer Tier (3DLAND)—ALTERNATE RULE SET



Rule Value DescriptionALT42.01 1.750 µm square 3DLAND width (only size and shape allowed) inside 3DALTALT42.02 1.800 µm Minimum spacing 3DLAND to 3DLAND on the same tier and on contiguous

metal landing inside 3DALTALT42.03 1.800 µm Minimum spacing 3DLAND to 3DLAND on the same tier and on isolated

metal landing inside 3DALTALT42.04a >3.750 µm warning Recommended minimum spacing for 5 to 24 closely placed 3DLAND inside 3DALTALT42.04b >5.800 µm warning Recommended minimum spacing for 25 or more closely placed 3DLAND inside 3DALTALT42.05 0.625 µm Minimum metal surround of 3DLAND, first metal without 3DFLIP, top-level metal

with 3DFLIP inside 3DALTALT42.06 Prohibited 3DLAND outside of metal landing, first metal without 3DFLIP, top-level metal

with 3DFLIP inside 3DALTALT42.07 Prohibited 3DLAND not coincident with 3DCUT in next higher numbered tier inside 3DALTALT42.08 1.600 µm Minimum space 3DLAND to POLY on non-3DFLIP tier inside 3DALTALT42.09 1.600 µm Minimum space 3DLAND to active on non-3DFLIP tier inside 3DALT



3D Via Land from Another Wafer Tier (3DLAND)—ALTERNATE RULE SET (Continued)

Flag for Alternate 3D Via Rule Set (3DALT)

Flag for Flipped Wafer w.r.t. Final 3D Stack (3DFLIP)

3D Back Side Cut Through Buried Oxide (3DBOXC)

3DLAND PolyActive LandingMetal

RULE 41.01

(2.500 µm)

(Square)

RULE 42.08

(1.600 µm)

RULE 42.02

(1.800 µm)

RULE 42.09

(1.600 µm)

RULE 42.01

(1.750 µm)

(Square)RULE 42.05

(0.625 µm)

RULE 42.03

(1.800 µm)

This is a flag layer that allows alternate 3D via rules inside a defined region.OPTIONAL LAYER–NOT OFFERED IN ALL PROCESS VERSIONS

Rule Value Description43.01 Prohibited Use of 3DALT not supported without permission. Contact MITLL for more information.

This is a flag layer that is used to indicate that during 3D assembly, a particular tier is flipped with respect to the final 3D stack.Tiers requiring 3DFLIP flags shall be determined by MITLL.OPTIONAL LAYER–NOT OFFERED IN ALL PROCESS VERSIONS

Rule Value Description44.01 Prohibited 3DCUT on a 3DFLIP tier

3DBOXC defines a cut made through the buried oxide under the silicon of a wafer tier that has been integrated into a 3D stack.OPTIONAL LAYER–NOT OFFERED IN ALL PROCESS VERSIONS




Pad Cut for Final 3D Stack (3DPAD)

Additional Layers: Flag and Comment (Markup)

NOFILL

DEVR

RED

GREEN

BLUE

YELLOW

3DPAD defines pad cuts for the final assembled 3D stack.These are normally generated during post-submission processing (derived from OGC layer).Do not use without consulting with MITLL.OPTIONAL LAYER–NOT OFFERED IN ALL PROCESS VERSIONS


(Comment layers are included as a design aid and have no effect on the layout other than the cell extents.)

This layer suppresses automatic fill generation. In regions not covered by NOFILL, fill structures are automatically generated by MITLL to force compliance with layer density rules. See MITLL Low-Power FDSOI CMOS Process: Application Notes for details.

Warning: When NOFILL is used the designer takes responsiblity for all layer density specifications in that region of use.

Reserved for future use

Comment layer

Comment layer

Comment layer

Comment layer


MITLL Low-Power FDSOI CMOS Process: Design GuideLAYOUT ACCEPTANCE REQUIREMENTS

6. LAYOUT ACCEPTANCE REQUIREMENTS

6.1. Design Grid

Layouts must be done to a 0.025-µ m (25 nm) grid at the wafer; i.e., the smallest fundamental unit (λ) is 0.025 µ m, and all polygon corners in the layout must be on a 0.025-µ m grid. Noncompliance with the 0.025-µ m grid may lead to reticle errors and unpredictable results. Submissions with structures, substructures, or extents placed off this grid will not be accepted.

6.2. Layout Database Format

GDSII is the preferred format for all layout submissions. CIF is an acceptable alternative if GDSII is not possible. A list of GDSII layer numbers and CIF layer names is included in the “Design Layers” chapter.

In the layout database, the precision must be 1000 with a unit length in µ m (1E-6).

Any round-ended paths (GDS PATH TYPE 1) must be flattened to polygons prior to submission.

All data must be placed inside the intended rectangular extent of the top structure. Any data placed outside will result in additional fill pattern generation in that region during postprocessing and, consequently, will “grow” the submission to a larger unintended extent.

The following GDS data types or attributes are not supported and should not be included:

BOX NODE ABSOLUTE MAGNIFICATIONABSOLUTE ANGLESNONORTHOGONAL REFERENCES

6.3. Top-Level Cell Labels

All top-level cells must have instantiated within them a label containing a brief design identifier and the name of the submitting organization. It is strongly encouraged that this be drawn in top-level metal so that chips may be easily identified after fabrication.

6.4. 3D Layout

Submissions for a 3D stacking process must have the same extent on all tiers, their origins centered in the extents, and the same top structure name with a final number designating to which tier each belongs. Exception: If a top-level cell on one tier is to be instantiated multiple times to align to a set of top-level cells on other tiers, then this top-level cell needs to be submitted only once. Detailed documentation must be provided, however, listing the submitted top-level cells, their corresponding tiers, and the alignment of the final assembly.



6.5. Minimum Rule Set

Table 6-1 lists the rules that must be followed for a layout to be accepted for inclusion in an MITLL FDSOI multiproject run. Any violation of these rules requires explicit permission from MITLL. The purpose of this rule subset is to protect other designs on the run. It is incumbent on designers to accept all responsibility for the effects of rules violations on their own designs.

6.6. Contact Information

Contributor contact information must accompany all submissions to allow follow-up as required.

6.7. Disclaimer

MITLL reserves the right to modify submission requirements at any time. It is strongly recommended that designs be made compliant with all design rules, so that future modifications to autogeneration routines, mask specifications, etc. will not create incompatibilities between design data and layout postprocessing, mask fabrication, and wafer fabrication processes.



Table 6-1: List of Mandatory Rules

Rule Description Constraint

General Polygon and Path Rules

0.1 Minimum feature width 0.200 µ m

0.2 Minimum feature spacing 0.250 µ m

0.3 Acute angles Prohibited

Density Rules (Enforced after Execution of MITLL Fill Generation Script)

Within any 1 mm x 1 mm window:

D1.01 Minimum active density 40%

D1.02 Maximum active density 60%

D9.01 Minimum poly density 10%

D9.02 Maximum poly density 20%

D17.01 Minimum metal 1 density 30%

D17.02 Maximum metal 1 density 80%






MITLL Low-Power FDSOI CMOS Process: Design GuideREVISION HISTORY


REVISION HISTORY

Rev. 2004:1 (Nov. 04). Replaces Version 6.x.

MITLL Low-Power FDSOI CMOS Process: Design GuideCONTACT INFORMATION


CONTACT INFORMATION

For specific inquiries:

Technical: Layout submission:

Brian Tyrrell Bruce Wheeler(781) 981-5496 (781) [email protected] [email protected]

Device modeling: Editorial:

Peter Wyatt Karen Challberg(781) 981-7882 (781) [email protected] [email protected]

For any other questions, comments, or suggestions:

MIT Lincoln Laboratory Advanced Silicon Technology Group 244 Wood Street Lexington, MA 02421 Phone: (781) 981-7880 Fax: (781) 981-7889 http://www.ll.mit.edu/AST

Documents

MITLL Low-Power FDSOI CMOS Process