FUTURE APPLICATIONS AI WITH FDSOI

Emmanuel Sabonnadière

6th Shanghai FDSOI FORUM, 18 September 2018

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• FDSOI mature technology at 28nm with full design platform available.

>1B$ SOI market already. Differentiated applications still waiting for a

killer application such as FE modules for PDSOI.

• 22/18nm platform ready with improved performance

• 12nm platform in advanced state of development, no major roadblocks.

Intrinsic benefits of FD maintained (power efficiency, back bias, RF).

Design platform still in construction.

• Possibility to extend to 7nm with performance booster already

identified. Proof of concept demonstrated on silicon.

• 3D sequential stacking is a natural extension for FDSOI to keep

increasing density while maintaining flexibility and power efficiency

• Neuromorphic design can greatly profit from FDSOI roadmap for

inference at the Edge while keeping the learning in the cloud.

• This combination for Edge IA might be the first awaited killer app to

come.

EXECUTIVE SUMMARY

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T

A Leti event co-organized with SITRI

Sponsored by

For further information, please contactDidier Louis, Leti didier.louis@cea.fr

Yemin DONG, SITRI Yemin.dong@sitrigroup.com

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N.Planes et al., VLSI’12

28nm design rules

28FDSOI VERSUS BULK

E. Beigne et al., ISSCC’14

• Better electrostatic control on FDSOI than planar bulk

• 32% frequency improvement at VDD=1V

• 84% frequency improvement at VDD=0.6V

FD devices are attractive for low voltage applications

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28FDSOI IS TODAY A REALITY

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• Compared to bulk and FinFETs, FDSOI

benefits from its undoped channel for

Gm/Gd and Vth mismatch for analog

circuits

• Optimal electrostatic control and

dynamic Vt setting by backbias for

power efficiency

• Order of magnitudes improvement in

Soft Error Rate for reliability and

mission critical operation

TODAY SOLUTION FOR LOW POWER, IOT AND

AUTOMOTIVE

L. Le Pailleur et al., ESSDERC’16

R. D. Schrimpf, Vandebilt University

G.Gasiot et al., 2014

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18nm/22nm FDSOI PERFORMANCE BOOSTERS

28FDSOI

22FDX

18FD

Performance

In-situ

doped epitaxyStrained

SiGe channel

for PFET

Raccess

Carrier

mobility

+50% frequency

with 100mV VDD

reductionElectrostatics

EOT scaling

6nm channel

20nm BOX STI

Si

SiGe

M. Haond et al., S3S’2014 F. Andrieu et al., ESSDERC’14

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22nm/12nm FDSOI PERFORMANCE

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BOOSTER ENABLERS FOR 7NM

12nm

7nm

Performance

• BOX thickness

scaling

• Dual-STI

• High-Ge SiGeB / HS

SiP source/drain

• High-Ge channel

• SAIPS

• BOX creep

• STRASS *

• sSOI *

• Gate-last *

Back bias

Carrier

mobility -40% Power @

same speed

Electrostatics

• EOT scaling

• Low-k spacer / epi

facetting

• Channel

thickness=Lg/4

* Possible second generation

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• Electrostatic control improved by

thinning TBOX

• Scalability down to 10nm node

• Devices already processed with

3.5nm SOI film

• Physical limit Lg=10nm (5nm-3nm

node)

ELECTROSTATIC CONTROL

Node 28nm 14nm 5nm

LG (nm) 30 20 10

TSOI (nm) 7 6 5

TBOX (nm) 25 20 15K. Cheng et al, VLSI 2011

Si data for LG=15nm:

TSOI

BOX

TSOI

BOX

TSOI

BOX

O.Faynot, IEDM 2010

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NMOS PMOS

• Strain SOI: +100% on narrow NMOS

• Strain SiGe: +60% on narrow PMOS

• Design/Technology co-optimization mandatory to get full strain effect

• e.g. continuous RX

STRONG EFFICIENCY OF STRAIN ON FDSOI!!

-11

-10

-9

-8

-7

-6

0 250 500 750 1000 1250

ION (µA/µm) (VD=VG=0.9V)

I OF

F (A

/µm

) (V

D=

0.9

V)

+100%

Open : W=80nm sSOI

+35%

Close : W=0.5µm SOI

K. Cheng et al., IEDM’12

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• 3D integration is a natural extension of FDSOI to reach ultimate

density and connectivity.

• Back bias can be maintained

• New interconnect layers are introduced in the middle to alleviate routing

congestion

• Top and bottom layers are homogeneous (same type and structure of devices

CoolCUBE (monolithic 3D)

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• New embedded memories can be integrated with FDSOI to enlarge its range of

applications

• Microcontrollers

• Secure applications

• AI at the edge

FDSOI AND NEW EMBEDDED MEMORIES

• CEA-LETI: Front End integration

(pre M1) of OxRAM cell in 28 FDSOI

• Samsung: dense STT-MRAM

integration in 28 FDSOI

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FDSOI AND AI TODAY

• The combination of FDSOI, 3D and new embedded memories open

up new ways for implementation of AI solutions in energy efficient

circuits

• Two examples of dedicated chips in 28FDSOI (ST technology)

• Neuro Accelerator, ST ISSCC 2018

• Deep Convolution NN

• 2.9TOPS/W

• Dynaps-SL (Uni. Zurich,

NeuRAM3 H2020 project)

• Spiking NN

• <2pJ per synaptic event

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FDSOI AND AI, TOMORROW

• The combination of FDSOI, 3D and new embedded memories open

up new ways for implementation of AI solutions in energy efficient

circuits

• Development in progress

• Monolitic 3D integration with RRAM

in the interconnect path for dense

3D neural networks

• ULP Mixed Analog/Digital

Spiking NN with RRAM

synapsis

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• For fully embedded AI at the Edge CEA-LETI is working on

unsupervised learning on combined system with FDSOI, 3D

integration and novel NVM.

• This combination should be able to address approaches

beyond the current purely digital deep learning towards

novel networks capable to work on time domain signal like

sound and speech.

• This might be the first awaited killer app to come.

CONCLUSION ON IA