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Low Power CMOS Process Technology
Scott Crowder
IBM, SRDC, East Fishkill, NY
Process Technology/Scott Crowder 2
Outline• What is Low Power?• Process For Low Standby Power• Process For Low Active Power• Other Low Power Requirements• Conclusions
Process Technology/Scott Crowder 3
Power Components in Digital CMOS• Standby Power
– Power when no function is occurring– Critical for battery driven– Can be reduced through circuit optimization– Temperature dependent leakage current dominates power
• Active Power– Switching power plus passive power– Critical for higher performance applications
• Other Sources of Power Consumption– Analog & I/O Power
• Some circuit configurations have current flow even w/o switching– Dynamic Memory Refresh Power
• eDRAM, 1T SRAM require periodic refresh of data
Process Technology/Scott Crowder 4
Power Components (simple version)
Power = Switching Power + Passive Power
f * C * V * V
FrequencyCapacitance
Voltage
I (V,T) * V
CurrentVoltage
Process Technology/Scott Crowder 5
Power Trends
180nm 130nm 90nm 65nm0
20
40
60
80
100
Pow
er fo
r 10
x 10
mm
chi
p (W
atts
)
Gate Sub Vt Active
Base Devices, 10% Activity, 105C
Desktop Processor TechnologyHandheld Technology
180nm 130nm 90nm 65nm 45nm0
50
100
150
200
Pass
ive
Pow
er (p
icoW
atts
/Mic
ron)
Gate Source Well
High Vt Devices, 25C
with
out H
igh-
K
Process Technology/Scott Crowder 6
What is Low Power in CMOS?• Depends on product application• Examples
#1: Handheld phone chip#2: Server microprocessor chip
Process Technology/Scott Crowder 7
Example #1: Handheld Application• Key Attributes:
– Battery Powered– In off-state significant portion of time– Standby condition at room temperature– Lawsuit if chip gets too hot– Standby dominates power requirements
• Leakage current at room temperature dominates power
• What is Low Power Optimized Design?– Want highest performance @ given leakage current
Process Technology/Scott Crowder 8
Example #2: Server Application• Key Attributes:
– Powered by electrical grid– Almost always on– Power condition at operating temperature– Lower power reduces packaging & cooling expense– Switching power dominated power requirements in past
• Want lower capacitance, voltage at maximum frequency– Passive power at operating temperature now a major component
• Want lower high temperature leakage current & lower voltage
• What is Low Power Optimized Design?– Want switching power to dominate– Want to maximize performance & modulate voltage to meet power
requirements
Process Technology/Scott Crowder 9
One More Major Component: Cost• Critically important to technical solution
• Example #2: Server microprocessor– Higher performance = higher end product price– Will add reasonable cost to enable performance
• Higher cost process: strain engineering, added metal levels• Flip-chip packaging, heat sinks & fans
• Example #1: Handheld application– Market will not allow higher cost solutions– Lower power specifications– Focus on lowest cost process that meets market demand
Process Technology/Scott Crowder 10
Low Standby Power
Process Technology/Scott Crowder 11
Components of Passive Power
• Major components– Source leakage current
• Sub threshold off-state current
– Gate current• Tunneling current thru
gate dielectric– Well current
• Band-to-band tunneling current to well
GND
VDD
VDD GND VDD
IG,off
IG,off
IS, off
IS, off
IW
IW
IG,on
IG,on
Process Technology/Scott Crowder 12
IS: Source Sub threshold Leakage
• Strong Vth dependence• Strong Temperature dependence
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2
Vt (V)
1E-7
1E-5
0.001
0.1
10
1000
100000
10000000
Ioff
(pA
/um
)
25C125C
Sub threshold current
110
1001000
10000100000
100000010000000
0.0010.010.1
1e-4
1e-71e-61e-5
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2
Process Technology/Scott Crowder 13
Under scaling Supply Voltage
• Higher performance at given leakage power by raising Vdd• Vdd scaling has slowed dramatically for low standby power
0
5
10
15
20
25
30
0.1 1 10 100 1000
Relative Leakage Power
Rin
g D
elay
(pse
c)
500mV350mV250mV
1.0V
1.0V
1.0V
1.1V
1.1V
1.1V
1.2V
1.2V1.2V
Lower leakage power at same performance at higher Vth & Vdd
Process Technology/Scott Crowder 14
Methods to Modulate IS Leakages
NWellNWellPWellPWell
N+N+P+P+
NN--band for NFET Active Wellband for NFET Active Well
PP--type Substratetype Substrate
SilicideSilicide
PFET
• Reverse Body Bias or Active Well
Added wellimplant toseparate welland substrate
NFET
Process Technology/Scott Crowder 15
Reverse Body Bias
Body bias dependence limited by IG & IW leakage
Leakage dominated by IS but low body effect
0.40.30.20.10.0-0.4 -0.3 -0.2 -0.1
1e-6
1e-7
1e-8
1e-9
1e-5
Body Bias Voltage0.30.20.10.0-0.4 -0.3 -0.2 -0.1 0.4
1e-6
1e-7
1e-5
1e-4
1e-3Total Leakage
Body Bias Voltage
Total LeakageHIGH VT DEVICES LOW VT DEVICES
Reverse bias
~5x 125C
25C
125C
25C
Reverse bias
Process Technology/Scott Crowder 16
IG: Gate Leakage
• Function of gate dielectric material and thickness• Low temperature dependence -> dominates at low T
Kraus, et al, IEEE TED Vol 52, No. 6 2005, page 1141
SiOxNy
~10xper
0.2nm
0 25 50 75 100 125 1500.00.10.20.30.40.50.60.70.80.91.0
~12 Angstrom gate oxide+1V
NFE
T G
ate
Leak
age
(µA)
Temperature (C)
Q. Liang, IBM
Process Technology/Scott Crowder 17
Methods to Reduce Gate Leakage: N
fixed EOT contours
• Increased Nitrogen concentration reduces gate leakageKraus, et al, IEEE TED Vol 52, No. 6 2005, page 1141
Process Technology/Scott Crowder 18
Methods to Incorporate Nitrogen
SiO2 base oxide
N plasma
plasmanitridation
thermalnitridation
SiO2 base oxide700-1000CNH3, NO
N N N
NN
NN
N
N-implantN N N
N N N
more N at top surface
N throughout
more N at bottomoxidation
Process Technology/Scott Crowder 19
High-k/Metal Gate Stack: Tinv = 14.5A, ToxGL = 16A
silicon
Bottom interface
High-k Layer
PolySi or Metal Gate
Methods to Reduce Gate Leakage: High-K
• Vth control (WF engineering)• Charge trapping• Mobility degradation• Increased complexity
• >1000x lower IG• Lower Tinv at same IG to enable device scaling
IssuesBenefits
Process Technology/Scott Crowder 20
Mobility
[[M FrankM Frank et al., VLSiet al., VLSi--TSA05 TSA05 ]]
• Acceptable long channel mobility with Hf-based oxides• Requires optimization of HfSiO(N)/SiO(N) composition
Process Technology/Scott Crowder 21
-1.5 -1.0 -0.5 0.0 0.5 1.0 1.50.00
0.20
0.40
0.60
0.80
1.00
1.20
nFETpFET
High-k / SiONHigh-k / SiO2
ConventionalHfSiO
SiON
Cap
acita
nce
dens
ity [µ
F/cm
2 ]
Gate voltage [V]
Fig. 3 Split C-V curves demonstrating the Vt shift obtained by gate stack optimization on SiO2 and SiONinterface layers
-1.5 -1.0 -0.5 0.0 0.5 1.0 1.50.00
0.20
0.40
0.60
0.80
1.00
1.20
nFETpFET
High-k / SiONHigh-k / SiO2
ConventionalHfSiO
SiON
Cap
acita
nce
dens
ity [µ
F/cm
2 ]
Gate voltage [V]
Fig. 3 Split C-V curves demonstrating the Vt shift obtained by gate stack optimization on SiO2 and SiONinterface layers
Gate Workfunction Tuning
Optimized high-k dielectric stack reduces pFET Vt shift by 200~300 mVSelective use of ultra-thin interface/surface modification layers
EXT EXTS/D S/D
STI STIhalos
Contact Contact
Bulk Si
Oxide/Nitride spacer
interfacial layer ('cap')
HfSiOgate stack
Counter doping
Fig.1 schematic to illustrate different components for vt adjustments for HfSIO gate stack
M. M. Frank et al VLSI-TSA 2005
Process Technology/Scott Crowder 22
IW: Tunneling & Trap-Assisted Current
50100150200Technology Node (nm)
0.01
0.1
1
10
100
1000
Cur
rent
(pA
/um
)
ISIGIW*
*** *****
*
* *
BTB tunneling
Well
S/DGate Field Enhanced BTB
Depletion
Trap Assisted
• Band to band tunneling increases with doping levels & steeper gradients
• Gate field enhanced tunneling increases with thinner gate dielectric
• Reduction of trap assisted current varies with cause
Schematic of IW sources Relative Contribution of IW
Process Technology/Scott Crowder 23
Methods to Reduce Junction Leakages
25 30 35 40 45Implant Energy (KeV)
0.9
1
1.1
1.2
1.3
1.4
1.5
Cap
acita
nce
(pF/
um2)
3
3.5
4
4.5
5
5.5
6
Cur
rent
(pA
/um
)
25 30 35 40 45 50Halo implant angle (degrees))
0.5
1
1.5
2
2.5
Cur
rent
(pA
/um
)
• Leakage modulated primarily by transistor doping profiles
NFET Junction Leakage vs. Halo Angle PFET Junction Leakage vs. S/D EnergyRef: Hook, ACEED 2005
Process Technology/Scott Crowder 24
Low Active Power
Process Technology/Scott Crowder 25
Components of Active Power Power ~ f * C * V * V + I (V,T) * V
Voltage
Higher Transistor Performance at Same Leakage
Same Fmax at Lower Voltage
Lower Active Power
Process Technology/Scott Crowder 26
Performance Scaling
Traditional performance scaling: Shorter Gate Length Higher Gate Capacitance (IG)Shallower Junctions (IW)Lower Threshold Voltage (IS)Lower Supply Voltage
Higher performance with: Higher Supply VoltageHigher Inversion CapacitanceHigher Mobility
All did not scale in 65nm technology
Process Technology/Scott Crowder 27
Mobility Innovation: Stress MemoryAmorphous layer
By implant
After anneal & Nit Removal
Si is crystallized and stress is “memorized”
0.006 0.007 0.008 0.009 0.01 0.011 0.012 0.013 0.014b (M1 FN10 10 0 08 0 07 M1 I )
1e-08
1e-07
1e-06
1e-05
100
1000
10
600 700 800 900 1000 1100 1200 1300 14001
nFET Ion (uA/um)
nFE
TIo
ff(n
A/u
m)
0.006 0.007 0.008 0.009 0.01 0.011 0.012 0.013 0.014b (M1 FN10 10 0 08 0 07 M1 I )
1e-08
1e-07
1e-06
1e-05
100
1000
10
600 700 800 900 1000 1100 1200 1300 14001
nFET Ion (uA/um)
nFE
TIo
ff(n
A/u
m)
Control
Tensile Nit stressor
[Chan, CICC ’05]
Process Technology/Scott Crowder 28
Mobility Innovations: Strained Liner
350 450 55010-9
10-8
10-7
10-6
10-5
Un-stress Compressive
Ion (µA/µm)
b) PMOS
Ioff
(A/µ
m)
350 450 55010-9
10-8
10-7
10-6
10-5
10-9
10-8
10-7
10-6
10-5
Un-stress Compressive
Ion (µA/µm)
b) PMOS
Ioff
(A/µ
m)
Un-stress
tensile
a) NMOS
700 900 1100 130010-8
10-7
10-6
10-5
10-4
Ioff
(A/µ
m)
Ion (µA/µm)
Un-stress
tensile
a) NMOS
700 900 1100 130010-8
10-7
10-6
10-5
10-4
10-8
10-7
10-6
10-5
10-4
Ioff
(A/µ
m)
Ion (µA/µm)
N PN PN P
Tensile nit Compr nit
Contact
ST
Tensile Nit + GeCompressive Nitride
[Chan, CICC ’05]
Process Technology/Scott Crowder 29
eSiGeeSiGe
P+Compressive liner
Mobility Innovations: Embedded SiGe
• Introduces compressive stress • Lowers contact resistance
[Luo, IEDM 2005]0 0.01 0.02 0.03 0.04 0.05 0.06 0.07PFET Lgate (um)
300
500
700
900
1100
1300
1500
1700
Rod
lin (o
hm)
w/o eSiGe
eSiGe
eSiGe + CSL
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07PFET Lgate (um)
300
500
700
900
1100
1300
1500
1700
Rod
lin (o
hm)
w/o eSiGe
eSiGe
eSiGe + CSL
[Luo, IEDM 2005]
PFET Liner Mobility Enhancement Embedded SiGe Cross-section
Process Technology/Scott Crowder 30
Mobility Innovations: <100> PFET
0o notch
<011> channel
<011> channel
X (100)
Y (010)
Z (001)
X (100)
Y (010)
Z (001)
45o notch
<010> channel
<001> channel
Process Technology/Scott Crowder 31
Mobility Innovations: <100> PFET
0 002 0 0025 0 003 0 0035 0 004 0 0045 0 005 0 0055 0 006
08
07
06
05
compressive
Neutraltensile
10-7
10-8
10-9
10-6
200 300 400 500 600
pMO
S Io
ff (A
/um
)
pMOS Ion (uA/um)
insensitive
0.0002 0.0003 0.0004 0.0005 0.0006M1 FPRVT1x_08 M1 Io n
p , ,
pFE
TIo
ff(n
A/u
m)
100
10
1000
1200 300 400 500 600 .
pFET Ion (uA/um)
Carrier direction<110>
Carrier direction<100>
0.0002 0.0003 0.0004 0.0005 0.0006M1 FPRVT1x_08 M1 Io n
p , ,
pFE
TIo
ff(n
A/u
m)
100
10
1000
1200 300 400 500 600 .
pFET Ion (uA/um)
Carrier direction<110>
Carrier direction<100>
• Significant boost in PFET current without added process steps• Loss of ability to increase current with compressive stress
[Chan, CICC ’05]
Process Technology/Scott Crowder 32
Mobility Innovations: Hybrid Orientation
PMOS NMOS
• 110 surface: 2x higher PFET µ >2x lower NFET µ
• Hybrid Orientation• 110 for PFET• 100 for NFET
Process Challenges:- Low defect epitaxy- Planarization- Trench isolation
M. Yang, VLSI 2004
Process Technology/Scott Crowder 33
Inversion Capacitance: Metal Gates
Binary/ternary alloys: W2N*, Ta2N*, TaN*, TaSiN*, RuO2**, CoSi2, NiSiMetals 3-5 nm thick on 500 nm SiO2, anneal 3 oC/s up to 1000 oC in FG
IIA IIIA IVA VA VIA VIIA
IIIB IVB VB VIB VIIB IB IIBVIII
*
**
Ag
CuCo**
CdPd**
P
Ni**
H
Li
Na
K
Rb
Cs
Fr
Be
Mg
Ca
Sr
Ba
Ra
Sc
Y
La
Ac
Ti*
Zr*
Hf*
V*
Nb*
Ta*
Cr
Mo
W
Mn*
Tc
Re**
Fe
Ru
Os
Rh**
Ir** Pt** Au
Zn
Hg
B
Al*
Ga
In
Tl
C
Si
Ge
Sn
Pb
N
As
Sb
Bi
O
S
Se
Te
Po
F
Cl
Br
I
At
He
Ne
Ar
Kr
Xe
Rn
*
**
Ce Pr Nd Pm Sm Eu Gd Tb Dy Ho Er Tm Yb Lu
Th Pa U Np Pu Am Cm Bk Cf Es Fm Md No Lr
IA VIIlA
1
3 4 5 6 7 8 9 10 11 12
13 14 15 16 17
18Stability <700CStability >700C* = NFET; **=PFET
• Metal gate incorporation to remove gate depletion
• Holy Grail: Band edge workfunction & thermally stable
Process Technology/Scott Crowder 34
Metal Gate Integration Options: FuSi
Metal DepositionAnneal, Strip, Anneal
Anneal, Strip, Anneal
“One Step” “Two Steps”
NiSi
PolysiliconMetal (Ni,Co)
Silicide
PolysiliconMetal (Ni,Co)
Silicide
Silicide
[Kedzierski, IEDM ’02]
Process Technology/Scott Crowder 35
NiAlSi
HfO2
O Al NiHfSi+Hf
Cou
nts
Al spikeAl pile up
Challenges for FuSi
• Dual Workfunction creation– Alloys– Doping– Phase change
• Workfunction control & stability• Variation with gate density & size
[ YH Kim IEDM’05]
Process Technology/Scott Crowder 36
Metal Gate Integration Options: Replacement Gate
Etch Gate Deposit High-kDeposit Gate MetalDeposit Fill Metal
CMP
Build Device
Challenges:• Integration of different workfunction metals: high complexity• High-k deposition on small gate area• ALD probably required for gate metal
Process Technology/Scott Crowder 37
Metal Gate Workfunction Stability• Workfunction of integrated metal gates has strong
dependence on deposition & annealing conditions
• Potential root causes of workfunction shifts– Metal induced gap states (MIGS) – Oxide charge (O vacancies) in HfO2
– Oxidation of interfacial metal– Hf-diffusion into metal (WF change)– Dipole layers at SiO2/HfO2 interface
Deposition
-1.0 -0.5 0.0 0.5 1.0 1.5 2.00.0
0.2
0.4
0.6
0.8
1.0
Gate Voltage (V)
Cap
acita
nce
Den
sity
(nor
m.) As deposited
OxidizingAmbient
ReducingAmbient
Annealing
[E. Cartier, VLSI ’05]
-0.5 0.0 0.5 1.0 1.5 2.00.0
0.5
1.0
1.5
2.0
2.5
3.0
Method1
Method2
Cap
acita
nce
Den
sity
( µF/c
m2 )
Process Technology/Scott Crowder 38
Memory Limitation to Voltage Scaling • SRAM cell stability limits scaling of array Vdd
– Vth mismatch due to dopant fluctuation in best case is constant with scaling
• Lack of gate dielectric scaling has caused it to increase– Reduction of all other components of mismatch critical
• Design Options– Larger cells– Separate array Vdd– Alternative cells/memory
• 8T SRAM• eDRAM
0.0 0.2 0.4 0.6 0.8 1.00.0
0.2
0.4
0.6
0.8
1.0
V rig
ht [V
]
Vleft [V]
6T
Cell area =
0.197µm2
0.0 0.2 0.4 0.6 0.8 1.00.0
0.2
0.4
0.6
0.8
1.0
V rig
ht [V
]
Vleft [V]
8T
Cell area =
0.262µm2
Butterfly curve comparison for scaled cells
[VLSI 2005]
Process Technology/Scott Crowder 39
Components of Switching Power Power ~ f * C * V * V
Capacitance
CmgCcg Cg Cov
Cd, area
Cd, per
Cd, per
Transistor
Cvert
Chor
Metallization
Process Technology/Scott Crowder 40
Capacitance Reduction: SOI
Cd, area
Cd, per Cd, per
Bulk TransistorCd, area
Cd, per Cd, per
SOI Transistor
• Reduction of area diffusion capacitance to negligible level• Reduction of perimeter capacitance with film scaling
• Additional AC drive current benefit from gate coupling
Process Technology/Scott Crowder 41
Options to Gate Capacitance Scaling• Need better electrostatic control to scale LG
– Higher gate inversion capacitance• High-K gate dielectric material to reduce EOT• Metal gate material to eliminate gate depletion
– Fully depleted double gate structures• Better channel control through structural change
• LG must decrease more than Cinv increases
Process Technology/Scott Crowder 42
Capacitance Scaling with Metal Gate• LG must decrease to prevent capacitance increase
• Short channel effect degradation when metal gate workfunction deviates too far from band edge– Lose portion of performance benefit and most of power benefit
Gate Workfunction
DIBL at constant LG
Si Band edge
Towards mid-gap
Process Technology/Scott Crowder 43
One Double Gate Structure: FinFET
[D. Fried][D. Fried]
NiSi Gate
SiFin
BOX
Tox = 1.6nm
NiSi
SiTsi = 25nm
Kedzierski, Kedzierski, IEDM 03IEDM 03
Process Challenges:• Fin creation and control• Source/drain resistance engineering• Contact formation and control
Process Technology/Scott Crowder 44
BEOL Capacitance Scaling
Cvert
Chor
Performance ~ R * C
Capacitance ~ keff * h / space
Resistance ~ ρ / (h * w)
h
Reduce inter-level dielectric constant => lower capacitance
Reduce resistance => lower height => lower capacitance
Process Technology/Scott Crowder 45
Capacitance Scaling: Reducing BEOL k
• Multiple porous dielectric options with k < 2.4– Spin-on and CVD deposition options
• All materials have lower material strength as k decreases– Optimization of BEOL stack & packaging required
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0Nominal Dielectric Constant, k
0.0
4.0
8.0
12.0
Coh
esiv
e St
reng
th, Γ
(J/m
2 ) X-H. Liu et al., Adv. Metal. Conf. (2004);
A. Grill et al., Adv. Metalliz. Conf. 2001
Process Technology/Scott Crowder 46
Capacitance Scaling: Scaling hCu
Ag
Au
45 nm
0.01 0.1 1Linewidth (µm)
0
2
4
6
8
10
12
14
Line
Res
istiv
ity (µ
Ω-c
m)
Al (pure) Note: Pure Al has poor E-M; Al(Cu) alloy has poor R.
AssumptionsGrain size = 2x line widthSmooth surfaces
Mean free paths: Al=15 nm; Cu=39 nm; Au =40 nm; Ag=45 nm
S. Rossnagel, Semicon West (2004).
• Copper will continue to be material for low ρ metallization
Process Technology/Scott Crowder 47
Capacitance Scaling: Scaling h
• Scaling requires thinner liner & seed films– 45nm dimensions demonstrated– Porous dielectrics must be compatible with thin liner to have benefit
• ALD liner & Cu seed reduction provide opportunity for additional scaling
CuTa/TaNLiner
ITRS 45nm PVD liners demonstrated Cu BEOL using Ru liner
[Edelstein, 2005]
Process Technology/Scott Crowder 48
Passives Scaling: BEOL Capacitors
Min. pitchwires
2X pitchwires
Native BEOL capacitor
0
0.5
1
1.5
2
2.5
3
0 50 100 150
Technology (nm)C
apac
itanc
e/A
rea
(fF/u
m2)
Native BEOL
• Benefit of scaling: better “free” BEOL capacitors
• Good tolerance due to averaging over many levels
Process Technology/Scott Crowder 49
Passives Scaling: Decoupling Capacitors
Trench Capacitors
0
50
100
150
200
0 0.5 1 1.5 2 2.5
Leakage (nA/um2)
Cap
acita
nce
(fF/u
m2)
Gate Oxide Caps
Trench Capacitor
• Gate capacitor scaling not possible with low passive power• >10x reduction in area & >100x reduction in leakage with trench capacitors
Process Technology/Scott Crowder 50
Conclusions: Handheld Low Power
• Standby power dominated
• Choices:– Add strain engineering without gate scaling– Add high-K dielectrics to enable gate scaling– Add design complexity to modulate leakage
• Decision will be driven by lowest cost solution
Process Technology/Scott Crowder 51
Conclusions: Plugged In Low Power• Active Power Dominated• Performance elements added as developed
• Choices:– Lower supply voltage
• May require new memory choice– Add design complexity to reduce both switching and
passive power• Voltage islands, clock gating, etc…