CSEE JOURNAL OF POWER AND ENERGY SYSTEMS, VOL. 6, NO. …

CSEE JOURNAL OF POWER AND ENERGY SYSTEMS, VOL. 6, NO. 2, JUNE 2020 249

Optimum Control Scheme of Output Voltage Basedon Cascaded H-bridge DVR

Fei Jiang, Member, IEEE, Siju Cheng, Chunming Tu, Member, IEEE, Qi Guo, Qing Li, and Cheng Chen

Abstract—This study presents an optimum control scheme tomaximize the output voltage level number of the cascaded H-bridge dynamic voltage restorer (CHB–DVR). The relationshipbetween the modulation index and the output voltage levelnumber is analyzed in detail. The compensation reference volt-age value is adjusted with the voltage drop depth to obtainhigh-quality output voltage with an acceptable total harmonicdistortion. Thus, the modulation index remains within a certainrange and thus meets the requirements of the maximum levelnumber technique (MLNT). In addition, an improvement methodbased on the MLNT is proposed to achieve minimum activepower absorption from a direct current link of the CHB–DVR.The traditional in-phase compensation and optimum controlstrategies are implemented to analyze the output voltage qualityfor verifying the feasibility of the proposed approach. Simulationand experimental results show the effectiveness of the proposedcontrol scheme.

Index Terms—Compensation scheme, DC-link voltage,dynamic voltage restorer, harmonic distortion.

I. INTRODUCTION

VOLTAGE sag in distribution networks is a commonpower quality problem that causes numerous losses for

customers [1]–[3]. The main causes of voltage sags are short-circuited faults, but they can also be caused by starting hugemotors and energizing transformers [4], [5]. Severe voltagesags can lead to serious negative effects on industrial produc-tion and residents’ lives. Thus, loads with a constant voltagemust be provided during sags.

Transformer-based regulations and inverter-based voltageregulators are two main voltage regulation methods [6], [7].Although the transformer-based regulator is widely adoptedin electrical power systems, its dynamic response is limitedby the slow movement of the taps or movable contacts [8].Inverter-based regulators use power electronics technology to

Manuscript received October 15, 2019; revised December 25, 2019; ac-cepted February 17, 2020. Date of publication June 30, 2020; date of currentversion March 14, 2020. This work was supported by the National NaturalScience Foundation of China (No. 51707014), and the Hunan ProvincialNatural Science Foundation of China (No. 2018JJ3534), and the ScientificResearch Fund of Hunan Provincial Education Department (No. 17C0040).

F. Jiang (corresponding author, e-mail: [email protected]) and S.J. Cheng are with the School of Electrical and Information Engineering,Changsha University of Science & Technology, Changsha 410004, China.

C. M. Tu, Q. Guo and Q. Li are with the College of Electrical andInformation Engineering, Hunan University, Changsha 410082, China.

C. Chen is with the Department of Engineering Sciences and Mathematics,Lulea University of Technology, Lulea 97187, Sweden.

DOI: 10.17775/CSEEJPES.2019.02580

regulate the output voltage. This type method is suitable forapplications requiring a variable voltage output [9]. A newmethod has been presented to minimise real power loss andimprove voltage profile in distribution systems [10].

A dynamic voltage restorer (DVR) is an effective device tomitigate voltage sags [11]. For traditional DVRs, the compen-sation voltage is injected through a series transformer [12],[13]. At present, a cascaded H-bridge (CHB) DVR (Fig. 1)is receiving extensive research attention [14]. The CHB–DVRgenerates a stepped output voltage that is closely related tototal harmonic distortion (THD). For the same number ofpower electronics, H-bridge multilevel topologies can increasethe level number of an inverter output voltage [15]. Thus,research on H-bridge focuses on increasing the number ofCHB–DVR modules [16]; however, the methods unavoidablyincrease the cost of the device. Other studies have paidintensive attention to optimization algorithms that minimizethe THD of stepwise output waveforms [17]. In [18], aneconomical and effective CHB-multilevel inverter is utilizedto minimize the number of switches and direct current (DC)voltage sources.

1

−1

0

1

−1

0

1

−1

0

0123

−1−2−3

ZLoad

Cdc1

Cdc2

Cdc3

uIOV_3

uIOV_2

uIOV_1

uIOV_1 Lf uS

TCf

uIOV_1uIOV

uIOV_3

Fig. 1. Schematic of a CHB–DVR system.

Several multilevel inverters have been proposed to ensurethat the CHB–DVR generates the required compensating volt-age. However, the main issue is the close relationship of theoutput voltage level number for the CHB–DVR to the voltagesag depth [19]. That is, shallow voltage sags only lead to asmall modulation index, and the level of the output steppedvoltage is low. By contrast, deep voltage sags lead to a largemodulation index and a high level number of stepped voltages.Therefore, the traditional CHB–DVR does not consistently

2096-0042 © 2019 CSEE

250 CSEE JOURNAL OF POWER AND ENERGY SYSTEMS, VOL. 6, NO. 2, JUNE 2020

output a compensation voltage with the maximum level num-ber under different sag depths.

In [20], a DC–DC converter is used to change the modula-tion index by adjusting the DC-link voltage of the DVR; thus,the output voltage of the inverter is consistently at the max-imum level. In [21], a mathematical relationship is proposedby computing the distortion at the point of common couplingto select the proper level number under different conditions.In [22], an adjustable DC-link voltage structure that uses asolar energy conversion system is proposed. Although thisadjustment is interesting, the method requires a nearly constantDC-link voltage [23]. Moreover, frequent adjustments of theDC-link voltage may cause problems in system security andstability [24]. In [25], the turn ratios of the transformer areconsidered variable; thus, a novel method for changing theamplitude of the input voltage is provided.

In this study, an optimum control scheme is presentedto maximize the output voltage level number of the CHB–DVR for obtaining a high-quality output voltage with anacceptable THD. The proposed method is based on adjustingthe compensation reference voltage value with the voltage dropdepth; thus, the method can avoid frequent adjustments ofthe DC-link voltage. Therefore, the CHB–DVR is successful,especially for shallow voltage sags.

The remainder of this paper is organized as follows. Sec-tion II introduces the topology and compensation scheme ofthe CHB–DVR. In Section III, the relationship between themodulation index and the output voltage level number of themultilevel inverter is analyzed in detail. In Section IV, themaximum output level scheme that adjusts the compensationvoltage reference values is proposed. Sections V and VIdemonstrate the performance of the control scheme throughsimulations and experimental results, respectively. Section VIIdiscusses the comparative analysis of the THDs of the outputvoltages between different schemes. Section VIII presents theconclusions drawn from this study.

II. TOPOLOGY AND COMPENSATION SCHEME

A. Topology

A single-phase configuration of a CHB–DVR is illustratedin Fig. 2. The CHB–DVR includes three modules, namely, theinput, DC-link and output modules. In the input module, threeparallel inverters (SM) are connected to the grid through a

uS

k1

k2

k3

k4

LZ Cdc

iC

Na

udvr iLoad

uLoad Zload

n1

n2

Cdc

uIOV

Cdc

LZ

LZ

C

SMSM

SM

SM

SM

SM

SM

① ② ③

L

Si1

Si2

Si3

Si4

①②③

Input module

Output module

DC-link module

Fig. 2. Topology of the CHB–DVR system.

multi-winding transformer, and each parallel inverter is with afilter (Lz), to eliminate the high frequency ripples. The outputmodule, which has a seven-level cascade inverter, is connectedto the grid through a series transformer (Na) and an LCfilter. The output module and the input module are connectedthrough the DC-link capacitor (Cdc). The input module aims tostabilize the DC-link voltage. The DC-link module providesthe compensating energy, and the output module injects thecompensation voltage through an LC filter.

The CHB–DVR compensates for voltage sags. The injectionvoltage is expressed as:

udvr = uLoad − uS (1)

where udvr is the compensation voltage, uLoad is the ratedload voltage (the reference load voltage) and uS is the sourcevoltage during sags. In the present study, phase-shifted carrierpulse width modulation (PSC–PWM) is used in the CHB–DVR [26], [27], and the output fundamental voltage value isexpressed as:

udvr = Nmudc sin(ωst+ θs) (2)

where N is the CHB module number, m is the modulationindex, udc is the DC-link voltage for each module, ωs is theangular frequency and θs is the starting phase angle. In (2), theamplitude of the inverter fundamental output voltage is relatedto N , m and udc. Thus, the modulation index is calculated as:

m =udvr

Nudc(3)

In (3), when N is selected, two methods are observed toincrease the modulation index m. The first method decreasesudc, and the second increases udvr. However, the former mayeasily worsen the CHB–DVR stability given the frequent DC-link voltage fluctuations [28]. Thus, the latter is selected forthe present study.

B. Compensation SchemeThe voltage compensation scheme of the CHB–DVR pri-

marily includes three methods, namely, the in-phase, phaseadvance and minimum energy compensation schemes [29],[30]. In Fig. 3, “O” is the center of the amplitude trajectorycircle of the load voltage (dotted circle), upre is the load voltagebefore the sag, uS is the system voltage after the sag, iL is theload current after the sag, ∆θ is the phase jump angle and udvris the amplitude of the output compensation voltage. For thefirst two schemes, the amplitudes of the compensation voltageudvr are constant when us is detected, as depicted in Figs. 3(a)and (b).

However, the minimum energy compensation scheme re-tains a constant load voltage by minimizing the active powerexchange between the DC-link module and the external powersystem. In Fig. 3(c), the solid circle is the compensationlimited range of the CHB–DVR, its center (Point “C”) isthe end of uS, ϕL is the phase angle of the load, uref is thecompensation reference voltage, β is the phase angle of thecompensation reference voltage and ϕdvr is the phase angle ofthe output compensation voltage.β increases (decreases) when uref has a clockwise (anti-

clockwise) rotation. Moreover, the fundamental amplitude of

JIANG et al.: OPTIMUM CONTROL SCHEME OF OUTPUT VOLTAGE BASED ON CASCADED H-BRIDGE DVR 251

upreO

udvr

uS

iL

∆θ

(a)

O

udvruS

iL

∆θ

(b)

upre(uref)

C

udvr

φdvr φL iL

upre

β

O B

udvr_3uref_2

uref

udvr

udvr_2

uref_1

uS

udvr_1D

∆θ

D2

A(D1)

(c)

Fig. 3. Phase diagram of the different compensation schemes during sags:(a) in-phase compensation; (b) phase advance compensation; (c) minimumenergy compensation.

the inverter output voltage can be changed flexibly within acertain range by adjusting β [31]. In Fig. 3(c), the dotted circleand its intersection region (Arc AB) are the adjustment rangesof uref, in which β can vary. In ∆DOC, the cosine theoremcan be derived as:

∠DOC = arccos|uref|2 + |us|2 − |udvr|2

2 · |uref| · |us|(4)

In Fig. 3(c), when uref is rotated to any position on Arc AB,we obtain:

u2dvr = u2ref + u2s − 2urefus cos(β −∆θ) (5)

and

udvr =√u2ref + u2s − 2urefus cos(β −∆θ) (6)

Equation (6) indicates that the compensation amplitude udvrof the CHB–DVR output voltage can be changed by rotatingthe phase angle β of the load reference voltage uref. Theamplitude range of udvr is controlled by β. Therefore, themodulation ratio can be increased by adjusting β withoutchanging the DC-link voltage.

III. MAXIMUM LEVEL NUMBER SCHEME

When the modulation ratio is flexibly controlled, the max-imum level number of the compensation voltage is easilyachieved [32]. In this section, the maximum level numberscheme of the output voltage is introduced in detail.

A. Relationship Between Output Voltage Level and Modula-tion Index

In this study, we select the unipolarity PSC–PWM becauseof its high DC-link voltage utilization. In Fig. 4, the modulatorsignal is f(t) = m sin(ωst), and the peak values of the trianglecarriers are 1. Tri1 controls Sij , and Tri2 controls Sik, wherei = 1, 2, · · · , n; j = 1, 2; and k = 3, 4. The phase difference

m

1

−1

E

D

A

BC

O

E

σ

Tri1 Tri2Trn2Tr11 Tr22 Tr12

σ′1 θ′1 θN θi+1 θ1 θ1σ1θ2 ωt/rad

ωt/rad

f(t)=msin(ωst)

Fig. 4. Diagram of the PSC–PWM.

between Tri1 and Tri2 is π, and Tr(i+1)1 leads to Tri1 with π/n.In Figs. 2 and 4, Si1 turns on when f(t) > Tri1. By contrast,Si2 turns off when f(t)Tri1. Si4 turns on when f(t) > Tri2,whereas Si3 turns off when f(t)Tri2.

In Fig. 4, θ′1 is the intersection point of Tr11 and f(t), whileθi is the intersection point of Tri2 and f(t). PWM theory positsthat and θi are the voltage phases of the starting and endingtimes, respectively. When each CHB module has a high outputvoltage level number, the phase difference is:

σ = θ1 − θ′1 (7)

We select PWM natural sampling [29] and rewrite (7) as:

σ ≈ σ1 − σ′1 (8)

From the similar triangle principle in ∆ABC, we can obtain(9) as:

AO

AB=m

1=OD

BC=

σ/2

Tcs/4=

2σ

Tcs(9)

where TCS is the carrier period. PSC-PWM is usually appliedto the drive pulse for the CHB inverter, and the shifted phaseof the triangular carrier for cell x relative to that for cell 1 isexpressed as [33]–[36]:

θx − θ1 =(x− 1)

Nπ (10)

where x = 1, · · · , N . Using two-cell CHB as an example,the shifted phases of the triangular carriers for cells 1 and 2are 0 and 90, respectively. Moreover, when x = N , (11) isderived from (10) as:

θN − θ1 =(N − 1)

Nπ (11)

To obtain the (2N + 1) level, θn ∈ (σ′1, σ1). (12) is derivedas follows from (7), (8) and (11) [37]:

N − 1

Nπ < σ =

m

2Tcs (12)

Considering that TCS = 2π in (12), we have:

m >N − 1

N(13)


B. Principle of the Maximum Level Output

In this study, udvr is defined as:

udvr = Nmudc (14)

To obtain the maximum level, (3) is substituted into (12),and m < 1 and TCS = 2π are considered. Thus,

(N − 1)udc < udvr < Nudc (15)

Considering (5) and (15), if the inverter outputs the maxi-mum level, then the compensation voltage must satisfy:

(N − 1)udc <√u2ref + u2s − 2urefus cos(β −∆θ) < Nudc

(16)

Furthermore, (16) is simplified as:

β1 < β < β2 (17)

where

β1 = ∆θ + arccosu2ref + u2s − (N − 1)2u2dc

2urefus(18)

and

β2 = ∆θ + arccosu2ref + u2s −N2u2dc

2urefus(19)

From (16)–(19), when the voltage sag (uS) is detected, ∆θshould be calculated. Considering that udc and N are chosen,β is only related to uref. Thus, the amplitude of the inverteroutput voltage can be controlled to achieve the maximum levelby adjusting β.

IV. IMPROVEMENT OF MAXIMUM LEVELNUMBER SCHEME

We expect the CHB–DVR to not only output maximum levelnumbers but also absorb minimum energy from the DC-side.

A. Minimum Energy Angle Scheme

In Fig. 3(c), the single-phase CHB–DVR outputs the activepower as follows:

pdvr = urefiL cosϕL − usiL cosϕS (20)

If pdvr > 0, then the CHB–DVR outputs the active power;if pdvr < 0, then the CHB–DVR absorbs the active power; andif pdvr = 0, then the CHB–DVR has no active power exchangewith the power network. In (20), if ϕL, uref and iL are constantvalues, then the active exchange between the CHB–DVR andthe system depends on the magnitudes of uS and ϕs.

If pdvr = 0, then the CHB–DVR has no active powerexchange with the system. Simultaneously, (20) is rewrittenas:

ϕS = arccos

(uref cosϕL

uS

)(21)

where ϕS = ϕL + ∆θ − β. Thus, the following is achieved:

β = ϕL + ∆θ − arccos

(uref cosϕL

uS

)(22)

where |uref cosϕL/uS| < 1. Thus, using (20), the followingcan be obtained:

∂pdvr

∂β= −usiL sin(ϕL + ∆θ − β) (23)

If ∂pdvr/∂β = 0, then pdvr will be the smallest value. Atthis time,

ϕL + ∆θ − β0 = 0 (24)

Using (22) and (23), the amplitude and phase angle of thecompensation voltage can be determined as:

udvr =√u2s + u2ref − 2usuref cos(β0 −∆θ) (25)

and

ϕdvr = β0 + arccos

(u2dvr + u2ref − u2s

2udvruref

)(26)

respectively.

B. Improvement Minimum Energy Angle Scheme Based onMaximum Level Output

When the minimum energy angle β0 does not satisfy (17),an improvement minimum energy angle is adopted. In Fig. 3(c)and (17), changing the load reference voltage phase is helpfulin moving β0 to β1, β2. Then, the CHB–DVR can output themaximum level. Two cases are available for selecting β0.

Case 1: When β1 < β0 < β2, pdvr is consistently largerthan 0. That is, the CHB–DVR will output the active power.Thus, the minimum power output value can be calculated as:

β′0 = P−1[min(p(β1), p(β2))] (27)

Case 2: When β1 < β0 < β2, pdvr is constantly smallerthan 0. That is, the CHB–DVR will absorb the active power.Thus, the maximum power can be calculated as:

β′′0 = p−1[max(p(β1), p(β2))] (28)

Using (27) and (28), the amplitude and phase of thecompensation voltage are recalculated to achieve an optimumcompensation voltage.

In summary, when voltage sag occurs in the system voltageresource, the power supply must provide as much active poweras possible, and the CHB–DVR must output the least activepower. To satisfy the maximum output level condition, theload reference voltage vector uref must be slowly rotated tothe point of the smallest value, where the CHB–DVR outputsthe active power based on upre. Otherwise, uref rotates to themaximum point, where the CHB–DVR absorbs active powerbased on upre. In this study, the outer loop is the load voltageinstantaneous value feedback, and the inner loop is the filtercapacitor current instantaneous value feedback. The controlblock diagram of the voltage compensation control strategy isexhibited in Fig. 5.


PLLupre

udvr

φdvr

uSiC

km

ki

sin ×

PI

β

Outer loop Inner loop

uL

+

+ ++

++−−

(18),(19)

PS

C-P

WM

Fig. 5. Control block diagram of the CHB–DVR.

C. Operation Sequence Analysis

The flowchart of the proposed control scheme is displayedin Fig. 6, where dsag is the drop amplitude of the grid voltage.If dsag ≥ 5%, then grid voltage sag is detected, and theCHB–DVR outputs the compensation voltage. Otherwise, thecompensation voltage cannot be generated. Then, ϕS and∆θare detected, and β0 is calculated using (23) and (24). (16)is used to determine whether β0 satisfies the maximum outputlevel condition. If the condition is satisfied, then β does notrequire rotation. If the condition is unsatisfied, then β mustbe slowly rotated until the requirements of (27) and (28) aresatisfied. Accordingly, the compensation voltage is generated.

Calculate β

Yes

No

start

Compensationvoltage

Initialization

No

end

dsag 5%

βi=βi+∆β

β∈(β1,β2)?

pmin=pi βmin=βi

Fig. 6. Flowchart of the phase adjustment of the load reference voltage.

V. SIMULATION RESULTS

In this section, we present the simulation results to supportthe validity of the proposed optimum control scheme. Thesimulations of the circuit model, as shown in Fig. 2, are per-formed in the MATLAB software. The simulation parametervalues are listed in Table I.

A. Traditional In-phase Compensation Strategy

The plots of the performance of the CHB–DVR based onthe in-phase compensation strategy are illustrated in Fig. 7.

From 0.10 s to 0.55 s (the first stage), the load impedanceis 23.325 + j20.567 Ω; from 0.55 s to 1.00 s (the second

TABLE ISIMULATION PARAMETERS OF THE CHB–DVR

Parameters Variable ValueSystem source uS 311 VSystem impedance ZS 0.02 ΩSwitching frequency — 6.4 kHzDC-link capacitor Cdc 5000 µFDC module voltage Udc 40 VLC filter Lf , LC 1.5 mH, 40 µFSeries transformer n1: n2 1:1Multi-winding transformer k1: k2: k3: k4 2:1:1:1Filter inductor Lz 0.6 mHNumber of CHBs — 3Load 1 ZLoad1 23.325 + j20.567 ΩLoad 2 ZLoad2 23.325 + j78.5 Ω

−400

400

100

−100

0

200

300

200

−200

0

20

−20

0

400

−400

Active powerReactive power

Seven levels Seven levelsThree levels Three levels

The first sag The second sag

The third sag The fourth sag

First stage Second stage

Switching process



Unchanged

us(

Lo

ad,d

vr)

/V

0.0

400

−400

us(

Lo

ad,d

vr)

/V

0.0

0.21 0.22 0.240.23Time (s) Time (s)

0.61 0.62 0.63 0.64

udvr

usuL

udvr

usuL

us(

Lo

ad,d

vr)

/V

0.0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0Time (s)

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0Time (s)

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0Time (s)

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

Time (s)

400

−400

us(

Load

,dvr)

/V

0.0

400

−400

us(

Load

,dvr)

/V

0.0

0.41 0.42Time (s) Time (s)

0.43 0.44 0.81 0.82 0.83 0.84

udvr

us

uL

udvr

usuL

pd

vr /W

, q

dvr /V

aru

IOV

/ V

i Lo

ad /A

(a)

(b)

(c)

(d)

Fig. 7. Simulation results of the CHB–DVR under in-phase compensation.Top to bottom: (a) source voltage uS, compensation voltage udvr and loadvoltage uLoad; (b) active power pdvr and reactive power qdvr; (c) steppedoutput voltage of the inverter uIOV; (b) load current iLoad.

stage), the load impedance is 23.325 + j78.5 Ω. As shownin Fig. 7(a), the source voltage has four voltage sags duringdifferent periods and has a depth of 25% of the nominalvalue during 0.2–0.3 s and 0.6–0.7 s and a depth of 5%of the nominal value during 0.4–0.5 s and 0.8–0.9 s. Asshown in Fig. 7(a), the CHB–DVR can inject compensationvoltage udvr to keep load voltage uLoad constant during the foursags. Moreover, the in-phase compensation strategy causes theCHB–DVR to output the active and reactive powers during


different sags, as shown in Fig. 7(b). As shown in Fig. 7(b),the CHB–DVR adopting the traditional scheme requires activepower from the DC-link during different sags.

As shown in Fig. 7(c), the compensation voltage levelnumber uIOV is 7 when the drop depth is 25% of the nominalvalue. However, when the drop depth is 5% of the nominalvalue, the uIOV level number is 3. Thus, the level numbers ofthe output voltage vary with different depths of the voltagesags. Moreover, when the load changes from the first stageto the second stage, the output voltages of the CHB–DVRare unchanged during different sags. As shown in Fig. 7(d),the load current can realize smooth translation, and no currentsurge exists between the different stages.

Figure 8 demonstrates the different harmonic contents fordifferent sags. In Fig. 8(a), the CHB–DVR can flexibly outputdifferent compensation voltages in 0.2–0.3 s, 0.4–0.5 s, 0.6–0.7 s and 0.8–0.9 s. However, as shown in Fig. 8(a), the THDsof the compensation voltages are 1.46% and 1.51% during0.2–0.3 s and 0.6–0.7 s, respectively. As shown in Fig. 8(c),the THDs of the compensation voltages are 6.65% and 6.70%during 0.4–0.5 s and 0.8–0.9 s, respectively. Fig. 8(a) indicatesthat shallow voltage sags increase the THDs of the compen-sation voltage. Therefore, the CHB–DVR is unsuccessful forshallow voltage sags.

−200

200

20

−20

0

0 4 8 12 16 200

1

2

Harmonic order0 4 8 12 16 20

Harmonic order

0 4 8 12 16 20Harmonic order Harmonic order

0 4 8 12 16 20


Mag

(%

of

Fundam

enta

l)

2.5

1.5

0.5

0

1

2

Mag

(%

of

Fundam

enta

l)

2.5

1.5

0.5

Fundamental (50Hz) = 68.23,

THD= 1.46%


THD= 6.65%

ud

vr /V

0.0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

Time (s)

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

Time (s)

i Load

/A

0

1

2

Mag

(%

of

Fundam

enta

l)

2.5

1.5

0.5

0

1

2

Mag

(%

of

Fundam

enta

l)

2.5

1.5

0.5


THD= 1.51%


THD= 6.70%

(a)

(b)

Fig. 8. Harmonic content under in-phase compensation strategy. Top tobottom: (a) compensation voltage udvr; (b) load current iLoad.

B. Optimum Control Scheme Proposed

The plots of the performance of the improved CHB–DVRoptimum compensation strategy are displayed in Fig. 9.

During the first stage, the load impedance is 23.325 +j20.567 Ω. When the depth of a voltage sag is 25% of the

200

−200

0

200

−200

0

400

600

20

−20

0

400

−400

Reactive powerActive power

Seven levels Seven levels

udvr udvrus

usuL uL

The first sag The second sag

The third sagThe forth sag


Switching process

us(

Lo

ad,d

vr)

/V

0.0

400

−400

us(

Load

,dv

r) /V

0.0

400

−400

us(

Load

,dv

r) /V

0.0

400

−400

us(

Lo

ad,d

vr)

/V

0.0

400

−400

us(

Lo

ad,d

vr)

/V

0.0

0.21 0.22Time (s) Time (s)

0.23 0.24 0.61 0.62 0.63 0.64

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0Time (s)

0.41 0.42 0.43 0.44Time (s)

0.81 0.82Time (s)

0.83 0.84

udvr

usuL

udvr

usuL

pd

vr /W

, q

dv

r /V

ar

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0Time (s)

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0Time (s)

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0Time (s)

uIO

V /V

i Lo

ad /A

(a)

(b)

(c)

(d)

Fig. 9. Simulation results of the CHB–DVR under in-phase compensation.Top to bottom: (a) source voltage uS, compensation voltage udvr and loadvoltage uLoad; (b) active power pdvr and reactive power qdvr; (c) steppedoutput voltage of the inverter uIOV; (b) load current iLoad.

nominal value during 0.2–0.3 s, the maximum output leveland the minimum power energy can be achieved if the rangeof the reference voltage phase angle is (4.04, 19.54). (23)indicates that the theoretical value of the minimum energyangle βmin must be 41.12, which is not within (4.04,19.54), to obtain the minimum output active power. Thus,β0 must be re-adjusted. Using (27) and (28), β0 is obtained as19.54. Using (23) and (24), the amplitude and phase angleof the compensation voltage are re-calculated to output thecompensation voltage. In the meantime, when the voltage sagis 5% during 0.4–0.5 s, the range of the reference voltage phaseis (14.87, 22.64). The theoretical value of the minimumenergy angle βmin is 3.54, which is also not within (14.87,22.64). Thus, β0 must be re-adjusted; therefore, β0 is 14.87.On the basis of (23) and (24), the amplitude and phase angleof the compensation voltage are re-calculated to output thecompensation voltage.

During the second stage, the load impedance is 23.325 +j78.5 Ω. When the depth of a voltage sag is 25% of the nominalvalue during 0.6–0.7 s, the maximum output level and theminimum power energy can be achieved if the range of the


reference voltage phase angle is (4.04, 19.54). (23) indicatesthat the theoretical value of the minimum energy angle βmin

is 5.77, which is within (4.04, 19.54). Thus, the CHB–DVR can achieve the minimum active power and the maximumoutput level. When the voltage sag is 5% of the nominal valueduring 0.8–0.9 s, the range of the reference voltage phase is(14.87, 22.64). The theoretical value of the minimum energyangle βmin is 0.90, which is not within (14.87, 22.64).Using (27) and (28), β0 is obtained as 14.87.

As shown in Fig. 9(a), voltage sags occur with four differentdepths, the CHB–DVR can always inject a compensationvoltage udvr and the load voltage uLoad can maintain a constantvalue. Fig. 9(c) shows that the level number of the outputvoltage is always 7 when the improvement minimum energyangle scheme is adopted. On the one hand, the DC-linkoutputting the active power is less than that in traditional in-phase compensation strategie during 0.2–0.3 s and 0.6–0.7 s.For example, the DC-link outputs a small number of the activepower (nearly 100 W) in Fig. 9(b), while it outputs a lot of theactive power (nearly 250 W) in Fig. 7(b) during 0.2–0.3 s. Onthe other hand, the DC-link does not output the power during0.4–0.5 s and 0.8–0.9 s while it absorbs the active power thatis fed back to the power system through the input module.

Figure 10 plots the different harmonic contents for differ-ent sags based on the improvement minimum energy anglescheme. In the first stage shown in Fig. 10(a), the THDs ofthe output voltages of the inverter are 1.35% and 2.03% in0.2–0.3 s and 0.4–0.5 s, respectively. In the second stage, theTHDs of the output voltages of the inverter are 1.54% and2.09% in 0.6–0.7 s and 0.8–0.9 s, respectively. Therefore, theproposed scheme is superior to the control scheme depicted

−200

200

20

−20

0

0 4 8 12 16 200

1

2

Harmonic order0 4 8 12 16 20

Harmonic order

0 4 8 12 16 20Harmonic order Harmonic order


Switching process

2.5

1.5

0.5

Mag

(%

of

Fundam

enta

l)

0

1

2

2.5

1.5

0.5

Mag

(%

of

Fundam

enta

l)

Fundamental (50Hz) = 91.82 ,

THD= 1.35%


THD= 2.03%

0.0

udvr /V

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0Time (s)

0

1

2

2.5

1.5

0.5

Mag

(%

of

Fundam

enta

l)

0

1

2

2.5

1.5

0.5

Mag

(%

of

Fundam

enta

l)

Fundamental (50Hz) =89.78 ,

THD= 1.54%


THD= 2.09%

i Lo

ad /A

0.1 0.2 0.3 0.4 0.5 0.6Time (s)

0.7 0.8 0.9 1.0

(a)

(b)

Fig. 10. Harmonic content under in-phase compensation strategy. Top tobottom: (a) compensation voltage udvr; (b) load current iLoad.

in Fig. 8, especially for shallow voltage sags (0.4–0.5 s and0.8–0.9 s).

VI. EXPERIMENT RESULTS

A single-phase experiment, as shown in Fig. 11, is con-ducted to verify the proposed scheme. The system parametersare the same as those in the simulation system, as shown inTable I. A control hardware in the loop test bed configuration,based on the control-hardware-in-the-loop (CHIL), was builtas shown in Fig. 11. The CHB–DVR was modeled in themaster controller, and the real-time digital simulation (RTDS)of the model was carried out in the slave controller with a stepsize of 10 µs. Control signals are measured at the samplingfrequency of 6.4 kHz and output to the I/O port of an externalTMS320F2812 DSP controller using an interface card. Thescales of the AC voltage and current signals are 50:1 and10:1, respectively; the scales of DC-link and output steppedvoltages are 40:1 and 30:1, respectively; and the scales of thepower are 50:1.

The Osclloscope

Hostcomputer

Real-time digital simulator

DSP

Behind

Host PC

Real-timeDigital Simulator PC

SamplingSignal

Hardware PWMSignalmodel

Conceptual structureof CHIL simulation

ControlProgram

Input

Fig. 11. RT-LAB-based CHIL testing platform.

The performance of the CHB–DVR based on the in-phasecompensation strategy is plotted in Fig. 12. Fig. 12(a) showsthat the source voltage exhibits four sags during differentperiods at depths of 25% of the nominal value during ∆t1 and∆t2 and 5% during ∆t3 and ∆t4. The CHB–DVR can injectcompensation voltage udvr, and load voltage uLoad can maintaina constant value. As shown in Fig. 12(b), the level numbers ofthe output stepped voltage vary with the depths of the voltagesags. The level number of uIOV is 7 when the depth is 20%of the nominal value; however, the level number of uIOV is3 when the depth is 10% of the nominal value. Moreover,the in-phase compensation strategy causes the CHB–DVR tooutput the active and reactive powers during different sags,as shown in Fig. 7(b). Fig. 12(c) shows that the load currentcan realize a smooth translation, and no current surge existsbetween different stages. The experimental results are the sameas the simulation results, as exhibited in Fig. 7.

The plots of the performance of the CHB–DVR improve-ment minimum energy angle scheme are illustrated in Fig. 13.As shown in Fig. 13(a), the source voltage has four voltagesags during different periods and has depths of 25% of thenominal value at ∆t1 and ∆t2 and 5% at ∆t3 and ∆t4. TheCHB–DVR can inject compensation voltage udvr, and the load


usuLudvr

Seven levels

Five levels

Δt1 Δt2 Δt3 Δt4


Active power

Reactive power

Switching process

CH2 5VCH3 2VCH4 5VM 100ms

CH1 2VM 100ms

CH1 2 WCH2 2 VarM 100ms

CH2 1ACH3 2VM 100ms

(d)

(c)

(b)

(a)

Fig. 12. Experimental results of a CHB–DVR during different voltage sags.Top to bottom: (a) source voltage uS, load voltage uLoad and compensationvoltage udvr; (b) level number of output stepped voltage uIOV; (c) activepower pdvr and reactive power qdvr; (d) compensation voltage udvr and loadcurrent iL.

voltage uLoad can maintain a constant value. Fig. 13(b) showsthat the level number of the output voltage is always 7 whenthe improvement minimum energy angle scheme is adopted.Therefore, the proposed scheme is superior to the controlscheme depicted in Fig. 12(b), especially for shallow voltagesags (∆t2 and ∆t4). Fig. 13(c) shows that the DC-link outputsless power than that in traditional in-phase compensationstrategies (as shown in Fig. 12(c)) at ∆t1 and ∆t3. Moreover,the DC-link does not output power at ∆t2 and ∆t3 and absorbsactive power, which is fed back to the power system throughthe input module. Fig. 13(d) indicates that the load currentcan also realize a smooth translation, and no current surgeexists between different stages. The experimental results arethe same as the simulation results, as depicted in Fig. 9.

VII. COMPARATIVE ANALYSIS

On the basis of Figs. 7–10, the comparative analysis of theTHDs of the compensation voltages for different schemes isshown in Fig. 14.

For case I, Fig. 14(a) shows that the load impedance is23.325 + j20.567 Ω. When the drop depth is 5% of the

us uLudvr

Seven levels

Seven levels


Active powerReactive power

Switching process

(a)

(b)

(c)

(d)

Δt1 Δt2 Δt3 Δt4

CH2 5VCH3 5VCH4 5VM 100ms

CH1 2VM 100ms

CH1 2 WCH2 2 VarM 100ms

CH2 1ACH3 5VM 100ms

Fig. 13. Experimental results of the CHB–DVR during different voltage sags.Top to bottom: (a) source voltage uS, load voltage uLoad and compensationvoltage udvr; (b) level number of the output stepped voltage uIOV; (c) activepower pdvr and reactive power qdvr; (d) compensation voltage udvr and loadcurrent iL.

25%5%0

1

2

3

4

5

6

7

Traditional scheme

Proposed optimum scheme

Traditional scheme

Proposed optimum scheme

25%5%

(b)

Nearly unchanged

Nearly unchanged

Decrease

Decrease

Drop depth (%)

Drop depth (%)

TH

D (

%)

0

1

2

3

4

5

6

7

TH

D (

%)

(a)

Fig. 14. Comparative analysis of THD of the compensation voltage duringdifferent sags. (a) Case I (ZLoad =23.325 + j20.567 Ω); (b) Case II(ZLoad =23.325 + j78.5 Ω).


nominal value, the THD of the compensation voltage adoptingthe proposed optimum scheme is only 2.03%, which is smallerthan that adopting the traditional method (6.65%). As shownin Figs. 7 and 9, the level number of the output voltage withthe proposed scheme is 7 during the 5% drops, while the levelnumber of the output voltage with the traditional approaches isonly 3. Moreover, when the drop depth is 25% of the nominalvalue, the THD of the compensation voltage adopting theproposed scheme is nearly equal to that adopting the traditionalscheme. At this time, the level numbers of the output voltageare 7 during the 25% drops, as shown in Figs. 7 and 9.

For case II, Fig. 14(b) shows that the load impedance ischanged to 23.325 + j78.5 Ω. The THD of the compensa-tion voltage adopting the proposed optimum scheme is alsosuperior to that adopting the traditional scheme during 5%sags due to the higher number levels of the former rather thanthe latter, as shown in Figs. 7 and 9. Moreover, the THDsof the compensation voltage are nearly unchanged in the twoschemes during 25% sags due to the same number levels.

VIII. CONCLUSION

In this study, an optimum control scheme for the outputcompensation voltage that maximizes its output voltage levelnumber is designed for the CHB–DVR. The relationshipbetween the modulation index and the output voltage levelnumber is analyzed in detail. The compensation referencevoltage value is adjusted with the voltage drop depth togenerate the maximum level number of the output invertervoltage. The simulation and experimental results of the CHB–DVR, which is designed to compensate for different voltagesags during varying loads, demonstrate different schemes. For25% and 5% voltage sags, the compensation voltages adoptingthe proposed optimum scheme are always seven-level voltages.This case is impossible in traditional approaches.

The results show that the proposed scheme is very suc-cessful due to the high-quality output voltage, especiallyfor shallow voltage sags. The CHB–DVR with the proposedoptimum control scheme will be analyzed in detail in a futureengineering project.

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Fei Jiang (S’15–M’16) received his B.S. and M.S.degrees in Electrical and Information Engineeringfrom the Changsha University of Science and Tech-nology, Changsha, China, in 2007 and 2012, re-spectively, and his Ph.D. degree in Electrical En-gineering from the College of Electrical and Infor-mation Engineering, Hunan University, Changsha, in2016.

From 2007 to 2009, he was an Assistant Electri-cal Engineer with Northwest China Grid Co., Ltd.,Xi’an, China. He was a Visiting Scholar with the

Chair of Power Electronics, Christian-Albrechts-University of Kiel, Kiel,Germany, in 2019. Currently, he is an Associate Professor with the School ofElectronics and Information Engineering, Changsha University of Science andTechnology. His current research interests include power electronic converters,distributed generation, and power quality.

Siju Cheng received his B.S. degree in the Collegeof Information Science and Engineering, ShenyangInstitute of Technology, Shengyang, China, in 2018.Currently, he is working toward his M.S. degreein Electrical Engineering at Changsha Universityof Science and Technology, Changsha, China. Hisresearch interests include distributed generation andpower quality.

Chunming Tu (M’13) received his M.S. and Ph.D.degrees in Electrical Engineering from Central SouthUniversity, Changsha, China, in 2001 and 2003,respectively. He was with Hunan University, Chang-sha, as an Assistant Professor from 2004 to 2005, anAssociate Professor from 2004 to 2009, and has beena Professor since 2009. His current research interestsinclude power quality control and power electronics.Dr. Tu was the recipient of the 2006 NationalScientific and Technological Awards of China, the2010 National Scientific and Technological Awards

of China, and the 2007 Scientific and Technological Awards from the NationalMechanical Industry Association of China.

Qi Guo received his B.S. degree in College ofElectrical Engineering, Anhui Polytechnic Univer-sity, Wuhu, China, in 2014. Currently, he is workingtoward his Ph.D. degree in Electrical Engineerngfrom Hunan University, Changsha, China. His re-search interests include power electronics converter,distributed generation and power quality.

Qing Li received his B.S. degree in the College ofElectrical Engineering, Hunan University, Changsha,China, in 2018. Currently, he is working toward hisM.S. degree in Electrical Engineering from HunanUniversity, Changsha, China. His research interestsinclude power electronic converters, distributed gen-eration and power quality.

Cheng Chen received his B.S. degree in ElectricalEngineering and Automation from Sichuan Univer-sity, Chengdu, China, in 2017, and received hisM.S. degree in Electric Power Engineering at KTH,Sweden, in 2019. Currently, he is working underthe supervision of Prof. Math Bollen at a projectfunded Swedish Energy Agency. He did internshipsin Beijing branch companies in State Grid Corpora-tion of China and is interested in renewable energyintegration and power system stability and control.

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