CSCI-641/EENG-641 Computer Architecture

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CSCI-641/EENG-641 Computer Architecture. Khurram Kazi. Course Outline. Studying Computer architecture from different perspective Processors such as General Purpose Processors (RISC) Specialty processors (Network Processors, security processors … ) Single Board Computers - PowerPoint PPT Presentation

Text of CSCI-641/EENG-641 Computer Architecture

  • CSCI 641 EENG 641 *CSCI-641/EENG-641

    Computer ArchitectureKhurram Kazi

    CSCI 641 EENG 641 *

  • Course Outline CSCI 641 EENG 641 *Studying Computer architecture from different perspectiveProcessors such asGeneral Purpose Processors (RISC)Specialty processors (Network Processors, security processors )Single Board ComputersTypical PC architectureBuses (AMBA Bus)Memory architecturesSRAM, DRAM, Non-volatile RAM (Flash, SD Card), Hard Disk AddressingInputs/OutputsUSB, HDMI, Video Port, Mouse, Keyboard Hardware design simulationsVHDL (VHSIC Hardware Description Language)FirmwareAssembly LanguageAssembly Language Hardware functional blocks

    CSCI 641 EENG 641 *

  • Desired outcomesCSCI 641 EENG 641 *Have a solid fundamental understanding of processors architecturesMemory and I/O architecturesInstruction level parallelism and related it to pipeliningCalculate the throughput with and without stallsHardware and Assembly language design fundamentalsUsing processors to build single board computersPartitioning of a design in hardware and firmware/software

    CSCI 641 EENG 641 *

  • Recommend BooksCSCI 641 EENG 641 *Computer Architecture: A Quantitative Approach, 4th Edition, Morgan Kaufman Publishers, Elsevier, 2007, ISBN: 0-12-370490-1

    Digital Design and Computer Architecture, David Harris and Sarah Harris, Elsevier, 2007, ISBN 13: 978-0-120370497-9

    HDL Programming Fundamentals; VHDL and Verilog, Nazeih, B. Botros, Da Vinci Engineering Press, 2006, ISBN: 1-58450-855-8

    CSCI 641 EENG 641 *

  • Software Tools UsedCSCI 641 EENG 641 *Mentor Graphics ModelSimVHDL simulatorYou can download student version of it from http://model.com/content/modelsim-pe-student-edition-hdl-simulationWill be using it extensivelyRISC instruction set simulatorhttp://sourceforge.net/projects/spimsimulator/files/

    CSCI 641 EENG 641 *

  • Grading PolicyCSCI 641 EENG 641 *Homework/Short Quizzes 30%1 Midterm Test30%Final Project40%Will start to discuss Final Projects towards the mid-semesterOral and written communication skills will be stressed in this course and taken into account in the final gradeCheating/ plagiarism Automatic F

    CSCI 641 EENG 641 *

  • CSCI 641 EENG 641 *Dos and Donts for the Final ProjectDO NOT use any off the shelf general purpose microprocessor or any other circuit taken from the publicly available information base and claim it is your work. I will know if you did!!Come up with your own functional idea and Implement it. Be creative! Have a systems perspective and see how your design fits in the system.By mid semester have a good idea of your project Team of 2 students working on the same project is allowed.Each team members task within the project should be explicitly defined.

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  • CSCI 641 EENG 641 *Teamwork Encouraged: How much collaboration is acceptableSince time will be short, I would encourage you to help out your fellow students with the Usage of the Tools but not the Design. Informing me of the help received is strongly encouraged, i.e. give credit where credit is due!!Helping fellow students with Tools usage and class participation will be rewarded in the final grade.

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  • CSCI 641 EENG 641 *Block Diagram of a Generic Processor

    CSCI 641 EENG 641 *

  • CSCI 641 EENG 641 *Basic Microcomputer DesignClock: Synchronizes internal operations of the CPU with other components of the systemALU: performs arithmetic operations such as +, -, *, /, and logic operations such as AND, OR, NOT Memory Storage: Instructions and data are held while computer program is running. Receives request for data from CPU, transfers data from RAM to CPU, or CPU into memoryBus: is a group of wires that transfer data from one part of the computer to another. Data bus: transfers instructions and data between CPU and memoryControl bus: synchronizes actions of all devices attached to the system busAddress bus: holds address of the instructions and data when the currently executing instruction transfers data between CPU and memory

    CSCI 641 EENG 641 *

  • CSCI 641 EENG 641 *Instruction Execution CycleFetch: The control unit fetches instruction from instruction queue and increments the instruction pointer (IP), AKA, Program CounterDecode: Control Unit decodes the instructions function to determine what the instruction will do and sends the appropriate signals to the ALUFetch Operands: If instruction uses an input operand located in memory, the control unit uses a read operation to retrieve the operand and copy it into internal registers.Execute: ALU executes the instruction using the named registers and internal registers as operands and sends the output to the named registers and/or memory. ALU then updates status flags to indicate the processor stateStore output operand: If the output operand is in memory, the control unit uses a write operation to store the data

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  • CSCI 641 EENG 641 *Testbench (GeneratorIn C or HDL)Testbench (AnalyzerIn C or HDL)HDL Design(VHDL or VerilogReference Model( In C or Functional HDL)HDL (Hardware Description Language) can typically be either VHDL or VerilogTypical HDL Design Environment

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  • CSCI 641 EENG 641 *Overview of VHDLLibrary and Library Declarations Entity DeclarationArchitectureConfiguration

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  • CSCI 641 EENG 641 *Overview of VHDLPackage (typically compiled into the destination library) contains commonly used declarationsConstants maybe defined hereEnumerated data types (Red, Green, Blue)Combinatorial functions (performing a decode function; returns single value)Procedures (can return multiple values)Component declarations

    CSCI 641 EENG 641 *

  • CSCI 641 EENG 641 *Overview of VHDLPackage (typically compiled into the destination library) contains commonly used declarationsConstants maybe defined hereEnumerated data types (Red, Green, Blue)Combinatorial functions (performing a decode function; returns single value)Procedures (can return multiple values)Component declarations

    CSCI 641 EENG 641 *

  • CSCI 641 EENG 641 *Overview of VHDL: Example of Library DeclarationLIBRARY library_name;--commentsUSE library_name.package_name.package_parts;-- VHDL is case -- insesitiveTypically there are three different libraries used in a designieee.std_logic_1164(from the ieee library)standard(from the std library)work(work library)std_logic_1164: Specifies the STD_LOGIC (8 levels) and the STD_ULOGIC (9 levels) multi-values logic systemsstd: It is a resource library (data types, text i/o, etc.)work: This is where the design is saved

    Library ieee;-- A semi-colon (;) indicates the end of a statement or a declarationUSE ieee.std_logic_1164.all;-- double dash indicates a comment.

    Library std;USE std.standard.all;

    Library work;USE work.all;

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  • CSCI 641 EENG 641 *Overview of VHDL: EntityEntityDefines the component name, its inputs and outputs (I/Os) and related declarations. Can use same Entity for different architecture to study various design trade offs.Use std_logic and std_logic_vector(n downto 0): they are synthesis friendly.Avoid enumerated type of I/Os. Avoid using port type buffer or bidir (unless you have to)

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  • CSCI 641 EENG 641 *Overview of VHDL: Syntax of an EntityENTITY entity_name ISPORT (port_name: signal_modesignal type;port_name: signal_modesignal type;.);END entity_name;

    ENTITY nand_gate ISPORT ( a:INstd_logic; b:INstd_logic; x:OUTstd_logic);END nand_gate;orENTITY FiveInput_nand_gate ISPORT ( a:INstd_logic_vector (4 downto 0); x:OUTstd_logic);END FiveInput_nand_gate;

    CSCI 641 EENG 641 *

  • CSCI 641 EENG 641 *Overview of VHDL: ArchitectureArchitectureDefines the functionality of the designNormally consists of processes and concurrent signal assignmentsSynchronous and/or combinatorial logic can be inferred from the way functionality is defined in the Processes.Avoid nested loopsAvoid generate statements with large indicesAlways think hardware when developing code!One way of looking at is how would you implement the digital design on the breadboard; mimic the same thought process in writing VHDL code

    CSCI 641 EENG 641 *

  • CSCI 641 EENG 641 *Overview of VHDL: Syntax of an ArchitectureARCHITECTURE architecture_name OF entity_name IS[declarations]BEGIN(code)END architecture_name;

    ARCHITECTURE myarch OF nand_gate ISBEGINx

  • CSCI 641 EENG 641 *Overview of VHDL: Basic Components of an ArchitecturePrimarily Architecture consists ofProcessConcurrent StatementsCode in VHDL is inherently concurrent (parallel)All processes and concurrent statements are evaluated in parallel (i.e. at the same time)Code inside the process is executed sequentiallyThe code execution is based on sensitivity list (signals that act as triggers in the execution of the respective processProcess can describe Asynchronous (combinatorial logic)Synchronous (clocked logic)Concurrent StatementsTypically combinatorial logic is implemented using concurrent statements

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  • CSCI 641 EENG 641 *Overview of VHDLConfigurationPrimarily used during the simulationsIf there are multiple ar