Appendix A - Pipelining CSCI/ EENG – 641 - W01 Computer Architecture 1 Prof. Babak Beheshti Slides based on the PowerPoint Presentations created by David

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SoECS Moves (OW) in Support of Research Lab Establishment

Appendix A - PipeliningCSCI/ EENG 641 - W01Computer Architecture 1Prof. Babak BeheshtiSlides based on the PowerPoint Presentations created by David Patterson as part of the Instructor Resources for the textbook by Hennessy & PattersonCS252 S051OutlineMIPS An ISA for Pipelining5 stage pipeliningStructural and Data HazardsForwardingBranch SchemesExceptions and InterruptsSummary

2CS252 S052A "Typical" RISC ISA [Page A-4](Reduced Instruction Set Computer)(Instruction Set Architecture)32-bit fixed format instruction (3 formats)32 32-bit GPR (R0 contains zero, DP take pair)3-address, reg-reg arithmetic instructionSingle address mode for load/store: base + displacementno indirectionSimple branch conditionsDelayed branch3see: SPARC, MIPS, HP PA-Risc, DEC Alpha, IBM PowerPC, CDC 6600, CDC 7600, Cray-1, Cray-2, Cray-3CS252 S053Example: MIPS (Microprocessor without Interlocked Pipeline Stages) not Million Instructions Per Second Appendix B.9 Put All Together: The MIPS Architecture -- similar to Figure B.22, Page B-354Op312601516202125Rs1RdimmediateOp3126025Op312601516202125Rs1Rs2targetRdOpxRegister-Register561011Register-ImmediateOp312601516202125Rs1Rs2/OpximmediateBranchJump / CallCS252 S054Datapath vs. ControlDatapath: Storage, FU, interconnect sufficient to perform the desired functionsInputs are Control PointsOutputs are signalsController: State machine to orchestrate operation on the data pathBased on desired function and signals

5DatapathControllerControl PointssignalsCS252 S055Approaching an ISAInstruction Set ArchitectureDefines set of operations, instruction format, hardware supported data types, named storage, addressing modes, sequencingMeaning of each instruction is described by RTL on architected registers and memoryGiven technology constraints assemble adequate datapathArchitected storage mapped to actual storageFunction units to do all the required operationsPossible additional storage (eg. MAR, MBR, )Interconnect to move information among regs and FUsMap each instruction to sequence of RTLsCollate sequences into symbolic controller state transition diagram (STD)Lower symbolic STD to control pointsImplement controller6CS252 S056OutlineMIPS An ISA for Pipelining5 stage pipeliningStructural and Data HazardsForwardingBranch SchemesExceptions and InterruptsSummary

7CS252 S0575 Steps of MIPS DatapathOne Datapath in a pipeline [Figure A.2, Page A-8]8MemoryAccessWriteBackInstructionFetchInstr. DecodeReg. FetchExecuteAddr. CalcLMDALUMUXMemoryReg FileMUXMUXDataMemoryMUXSignExtend4AdderZero?Next SEQ PCAddressNext PCWB DataInstRDRS1RS2ImmIR