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Course Topics - Outline

Lecture 1 - Introduction Lecture 2 - Lexical conventions Lecture 3 - Data types Lecture 4 - Operators Lecture 5 - Behavioral modeling A Lecture 6 – Behavioral modeling B Lecture 7 – Behavioral modeling C Lecture 8 – Data flow modeling Lecture 9 – Gate Level modeling Lecture 10 – Tasks and Functions Lecture 11 – Advanced Modeling Techniques Lecture 12 - Coding Styles and Test Benches Lecture 13 - Switch Level modeling

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Lecture 11 - Advanced Modeling Techniques

User Defined Primitives

o Combinational UDP

o Sequential UDP

The Generate Function

o Generate loop

o Generate conditional

o Generate case

Exercise 11

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User-Defined Primitives

User can extend the set of Verilog predefined gate primitives by designing and specifying new primitive elements called User-Defined Primitives (UDPs).

Instances of these new, self-contained, UDPs can then be used in exactly the same manner as the gate primitives to represent the circuit being modeled.

Employing UDPs can reduce the amount of memory needed for modeling and improve simulation performance.

There are two types of UDPs:

o combinational

o sequential

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Combinational and Sequential UDPs

Combinational UDP is defined where the output is solely determined by a logical combination of the inputs.

Maximum number of inputs to a Combinational UDP is 10. Sequential UDP takes the value of its inputs and the current

value of its output to determine the next value of its output. The value of the output is also the internal state of the UDP.

Sequential UDP provide an easy and efficient way to model sequential circuits such as flip-flops and latches.

Sequential UDP allow mixing of the level-sensitive and edge-sensitive constructs in the same description.

Maximum number of inputs to a Sequential UDP is limited to 9 because the internal state counts as an input.

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UDP Definition – Formal Syntax

Each UDP has exactly one output, which can be in one of three states: 0, 1 or X. Tri-state value Z is not supported.

The formal syntax of the UDP definition is as follows: primitive <UDP_name> (<output_terminal_name>,

<input_terminal_names>) ; // UDP name & terminal list output <output_terminal_name> ; // Terminals declarations input <input_terminal_names> ; reg <output_terminal_name> ; // optional, only for seq UDP initial <output_terminal_name>=<value> ; // only for seq UDP table // UDP state table <table entries> endtable endprimitive // End of UDP definition

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UDP Rules

1. UDP can take only scalar input terminals (1 bit)

2. UDP can have only one scalar output. Output terminal must always appear first in the terminal list.

3. The state in a sequential UDP can be initialized with an initial statement.

4. State table entries can contain values of 0, 1 or X. Z values passed to a UDP are treated as X values.

5. UDPs are defined at the same level as modules.

6. UDPs are instantiated exactly like gate primitives.

7. UDPs do not support inout ports.

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Combinational UDP Example – and gate

primitive udp_and(out, a, b) ; // UDP name and terminal list output out ; // combinational, wire not a reg input a, b ; // inputs declarations table //table input entries & input terminal list - same order! // a b : out ; if unspecified combination occurs, out = X 0 0 : 0 ; 0 1 : 0 ; 1 0 : 0 ; 1 1 : 1 ; endtable endprimitive // ANSI C style UDP declaration. output always 1st in port list! primitive udp_and(output out, input a, input b) ; ……… endprimitive

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Combinational UDP example – or gate

primitive udp_or(out, a, b) ; output out ; input a, b ; table // a b : out ; // table covers all in combinations for out != X 0 0 : 0 ; // input Z not allowed. Treated as X 0 1 : 1 ; 1 0 : 1 ; 1 1 : 1 ; X 1 : 1 ; 1 X : 1 ; endtable endprimitive

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or gate with shorthand notation for don’t cares

primitive udp_or(output out, input a, input b) ; //ANSI C style table // a b : out ; // table covers all in combinations for out != X 0 0 : 0 ; // input Z not allowed. Treated as X 1 ? : 1 ; // ? Expanded to 0, 1, X ? 1 : 1 ; // ? Expanded to 0, 1, X 0 X : X ; X 0 : X ; endtable endprimitive

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Instantiating UDP Primitives

UDP is instantiated exactly as like Verilog gate primitive

// 1-bit full adder using udp_and & udp_or, defined earlier

module fulladd (sum, c_out, a, b, c_in) ; output sum, c_out ; input a, b, c_in : wire s1, c1, c2 ; xor (s1, a, b) ; // use Verilog primitive udp_and (c1, a, b) ; // use UDP xor (sum, s1, c_in) ; // use Verilog primitive udp_and (c2, s1, c_in) ; // use Combinational UDP udp_or (c_out, c2, c1) ; // use Combinational UDP

endmodule

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Example: Level-Sensitive Sequential UDP - latch

Level-sensitive UDP changes state based on input levels. Latches are common example of level-sensitive UDPs.

primitive latch(q, d, clock, clear) ; // Define LS UDP Latch output reg q ; input d, clock, clear ; initial q = 0 ; // initialize output to value 0 table // state table // d clock clear : q : q+ q+ is the new output value ? ? 1 : ? : 0 ; // clear condition 1 1 0 : ? : 1 ; // latch q = d = 1 0 1 0 : ? : 0 ; // latch q = d = 0 ? 0 0 : ? : - ; // retains original state if clock = 0 endtable endprimitive

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Example: Edge-Sensitive Sequential UDP – D FF

Edge-sensitive sequential UDP changes state on edge transition and/or input levels.

Edge-triggered flip-flops are the most common example of edge-sensitive sequential UDPs.

primitive edge_dff (output reg q = 0, input clk, clr, d) ; table // state table // clk clr d : q : q+ // q+ next state ? 1 ? : ? : 0 ; // output = 0 if clr (clear) = 1 ? (10) ? : ? : - ; // ignore negative edge clr (clear) (01) 0 0 : ? : 0 ; // latch data on positive transition of clk (01) 0 1 : ? : 1 ; // latch data on positive transition of clk (10) 0 ? : ? : - ; // ignore negative edge of clk ? 0 (??) : ? : - ; // ignore data changes on steady clk endtable endprimitive

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Symbols to Enhance Readability

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Generate statements allow Verilog code for modules, gate Primitives, UDPs, continuous assignments and initial-always blocks, to be generated dynamically @ elaboration time. This facilitates the creation of parameterized models.

Very useful when same operation or module instance is repeated for multiple bits of a vector or when certain Verilog code is parameter-conditionally included.

Generate statements allow control over declaration of variables, functions, tasks, and instantiations.

All generate instantiations are coded with a module scope and enclosed within the keywords generate – endgenerate

The Generate Function

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The Generate Function cont.

To support interconnection between structural elements and/or procedural blocks, net, reg, integer, real, time, realtime and event data types, are permitted within the generate scope.

Generate data types have unique identifier names and can be referenced hierarchically.

Some module declarations and items are not permitted in a generate statement – parameters, local parameters, input, output, inout declarations, specify blocks

There are 3 methods to create generate statements: o Generate loop o Generate conditional o Generate case

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Generate Loop

Permits one or more of the following to be instantiated multiple times, using a for loop:

Variable declarations

o Modules

o User Defined and Gate Primitives

o Continuous assignments

o Initial and always blocks

The keyword genvar is used as the index control variable by generate for loops. genvar is restricted to a positive or 0 value. Negative values, X and Z values cannot be assigned to a genvar variable.

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Example: 64-bit adder using a generate for loop

// Behavioral adder. Using 8 8bit adders and index part select module adder8bit (ci, a, b, sum, co) ; ……… // ports declarations wire [8:0] carry ; assign carry[0] = ci ; generate genvar i ; for (i = 0 ; i <= 7 ; i = i + 1) begin: for_name // hierarchical referencing name adder8 big_adder(sum[(i * 8) + : 8], co[i + 1], a[(i * 8) + : 8], b[(i * 8) + : 8], ci[i]) ; end endgenerate assign co = carry[8] ; endmodule

//8-bit adder

module adder8 (sum,co,a,b,cin) ;

input [7:0] a, b ; output [7:0] sum ; output co ; input cin; assign {co, sum} = a + b + cin ; endmodule

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Example: bit-wise XOR using a generate for loop

// This module generates a bit-wise xor of two N-bit busses module bitwise_xor (out, i0, i1) ; parameter N = 32 ; // 32-bit bus by default output [N-1:0] out ; // ports declaration input [N-1:0] i0, i1 ; genvar j ; // Temp loop variable. Does not exists during simulation

generate for (j = 0 ; j > N ; j = j + 1) begin: xor_loop xor g1 (out[j], io[j], i1[j]) ; // Using xor primitive gates end endgenerate endmodule

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bit-wise XOR using a generate for loop

// Alternate style: The xor gates are replaced by always blocks module bitwise_xor (out, i0, i1) ; parameter N = 32 ; // 32-bit bus by default input [N-1:0] i0, i1 ; output reg [N-1:0] out ; genvar j ; // this variable does not exists during simulation generate for (j = 0 ; j > N ; j = j + 1) begin: bit always @ (io[j] or i1[j]) // using always blocks out[j] = io[j] ^ i1[j]) ; end endgenerate endmodule

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Generate Conditional

A generate conditional is like an if-else-if generate construct that permits the following Verilog constructs, to be conditionally instantiated into another module, based on an expression that is deterministic at the time the design is elaborated: o Modules

o Gate Primitive and User-Defined Primitives (UDP) o Continuous assignments o Initial and always blocks

A generate if statement can be used inside a generate block to conditionally control what objects get generated.

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Generate Conditional example

/* The generate controls what type of multiplier is instantiated. The contents of each branch of the if... else statement must be enclosed by begin and end statements and the begin statement must be named with a unique qualifier. */ generate if (IF_WIDTH < 10) begin : if_name adder # (IF_WIDTH) u1 (a, b, sum_if); end else begin : else_name subtractor # (IF_WIDTH) u2 (a, b, sum_if); end endgenerate

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Generate Conditional example - parameterized multiplier

module multiplier (product, a0, a1) ;

parameter a0_width = 8 ; // 8-bit bus by default

parameter a1_width = 8 ; // 8-bit bus by default

localparam product_width = a0_width + a1_width

output [product_width-1:0] product ;

input [a0_width-1:0] a0 ;

input [a1_width-1:0] a1 ;

generate // Generate carry look ahead or tree multiplier? if (a0_width < 8) || (a1_width < 8) cla_multiplier #(a0_width,a1_width) m0(product, a0, a1) ;

else tree_multiplier #(a0_width,a1_width) m0(product, a0, a1) ;

endgenerate

endmodule

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Generate Case

A generate case permits the following Verilog constructs to be conditionally instantiated into another module based on a select one-of-many case construct that is deterministic at the time the design is elaborated:

o Modules

o Gate Primitive and User-Defined Primitives (UDP)

o Continuous assignments

o Initial and always blocks

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Example: Generate Case N-bit adder

module adder(co, sum, a0, a1, ci) ;

parameter N = 4 ; 4-bit bus by default.

output [N-1:0] sum ;

output co ;

input [N-1:0] a0, a1 ;

input ci ;

generate // appropriate adder instantiation, based on bus width

case (N)

1: adder_1bit adder1(co, sum, a0, a1, ci) ;

2: adder_2bit adder2(co, sum, a0, a1, ci) ;

default: adder_cla #(N) adder3(co, sum, a0, a1, ci) ; endcase

engenerate

endmodule

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Exercise 11

Part1: Implement 3:1 Mux as a Combinational UDP. instantiate in a module and verify functionality. Define select control = 2'b11 as default to out = in3.

Part2: Design JK-edge FF with async active-low preset and clear signals, as a Sequential mixed-level/edge-sensitive UDP. Instantiate in a module and verify functionality.

Part 3: Implement byte-wide Gray2bin code conversion, using a generate for loop. Use for loop and assign statement. Instantiate in a module and verify functionality.