B.L.D.E. Association’s V.P. Dr. P. G. Halakatti …bldeacet.ac.in/PDF/CourseFile/EC/EC_6th_CBCS_2017-18.pdfBandpass Signal to Equivalent lowpass Signal : Hilbert Transform, Pre-envelopes,

B.L.D.E. Association’s

V.P. Dr. P. G. Halakatti College of Engineering & Technology, Vijayapur – 586 103

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

Programme: B.E in Electronic & Communication Engineering

Digital Communication

Semester: VI Year: 2017-18 (Even Sem)

Subject Code: 15EC61 IA Marks :20

Number of Lecture Hours/Week:04 VTU Exam Marks :80

Total Number of Lecture Hours :50 Exam Hours :3

Credits – 04

1. Course Details

1.1. Syllabus

Module 1

Bandpass Signal to Equivalent lowpass Signal : Hilbert Transform, Pre-envelopes, Complex

envelopes, Canonical representation of bandpass signals, Complex low pass representation of

band-pass systems, Complex representation of bandpass signals and systems.

Line codes: Unipolar, Polar, Bipolar (AMI) and Manchester code and their power spectral

densities. Overview of HDB3, B3ZS, B6ZS. (Text 1, Ref 1, 2)

Module 2 Signaling over AWGN channels-Detection and Estimation: Introduction, Geometric

representation of signals, Gram-Schmidt Orthogonalization procedure, Conversion of the

continuous AWGN channel into a vector channel, Optimum receivers using coherent detection:

ML Decoding, Correlation receiver, matched filter receiver. (Text 1)

Module 3 Digital Modulation Techniques: Digital modulation formats, Phase shift Keying techniques

using coherent detection: BPSK, QPSK generation, detection and error probabilities, M-ary PSK,

M-ary QAM.Frequency shift keying techniques using Coherent detection: BFSK

generation,detection and error probability. Non coherent orthogonal modulation techniques:

BFSK, DPSK Symbol representation, Block diagrams treatment of Transmitter and Receiver,

Probability of error (Without derivation) (Text 1).

Module 4 Communication through Band Limited Channels: Digital Transmission through Band limited

channels - Inter Symbol Interference, Eye diagrams, Signal design for Band limited ideal channel

with zero ISI – Nyquist Criterion (statement only), Sinc and Raised pulse shaping.Signal design

for Band limited channel with controlled ISI – Correlative coding, DB and MDB, Precoding.

Basic Concepts of Equalization for non ideal channels – ZFE, MMSE, (without derivations),

Adaptive Equalizers (Block diagram only) (Text 2, Ref 2).

Module 5

Principles of Spread Spectrum: Concept of Spread Spectrum, Direct Sequence/SS, Frequency

Hopped SS, Processing Gain, Interference, and probability of error statement only. PN sequences

for Spread Spectrum – M- sequences with Properties; Gold, Kasami sequences with basic

properties. Direct sequence spread spectrum system concepts, Frequency Hopped Spread

spectrum system concepts, Spread Spectrum Synchronization (block diagram treatment) - Code

Acquisition and Tracking. (Text 2)





Text Book

1. Simon Haykin, “Digital Communication Systems”, John Wiley & sons, First Edition,

2014, ISBN 978-0-471-64735-5.

2. John G Proakis and Masoud Salehi, “Fundamentals of Communication Systems”, 2014

Edition, Pearson Education, ISBN 978-8-131-70573-5.

Reference Books

1. Ian A Glover and Peter M Grant, “Digital Communications”, Pearson Education, Third

Edition, 2010, ISBN 978-0-273-71830-7.

2. B.P.Lathi and Zhi Ding, “Modern Digital and Analog communication Systems”, Oxford

University Press, 4th Edition, 2010, ISBN: 978-0-198-07380-2.

Prerequisites for the course The subject study requires a good background of probability theory, Signals & Systems and

Information Theory and coding.

2.1. Overview of the course

The purpose of any communication system is to transfer information from one place to another.

Noise limits our ability to communicate. Digital communication system have better immunity

towards noise compare to other system. Model1 deals with principles that governs the conversion

of bandpass signal to equivalent low pass signal and also discusses about different line coding

techniques to represent digital data. The Model 2 discusses about optimum design of digital

communication system. The Model 3 deals with different digital modulation techniques and

performance evaluation using constellation diagram. The model 4 deals with design of digital

signal for transmission over band limited channel to achieve zero ISI. The model 5 attempts to

achieve secured communication by designing digital signals for spread spectrum.

2.2. Relevance to the programme Digital communication is one of the fundamental subject in this program The subject deals

with digitization of information. Digitization saves bandwidth. And also provides better

immunity to noise which is one of the important issue in communication in recent years.

2.3. Course Outcomes

1. Define different line coding techniques and representation of bandpass signal.

2. Design optimum receiver for digital communication.

3. Performance Evalvation of different modulation techniques.

4. Design a signal for transmission over bandlimited channel to achieve zero ISI.

5. Design a spread spectrum signal for digital communication.

2.4. Applications The course information theory and coding plays a vital role in

1. Lossy and Lossless Compression

2. Error Control Coding

3. Cryptography

4. Measures the Information content of a message.

5. Computes the Entropy.

3. Modulewise Course Plan





Module 1 : Bandpass Signal to Equivalent lowpass Signal Number of Hours :10

a. Learning objectives 1. Compute Hilbert Transform of some standard signals.

2. Define different approaches of representing bandpass signal to equivalent low pass

signal.

3. Define different line coding techniques to represent digital data.

b. Lesson Plan

Lecture

No. Topics Covered

Teaching

Method

PO’s

Attained

CO’s

Attained

Text/Reference

book/

chapter no

1. Hilbert Transform Chalk and Board a,b,e,h,k CO1 Text 1, Ref 1,2

2 Pre-envelopes and

Complex envelopes

Chalk and Board a,b,e,h,k CO1 Text 1, Ref 1,2

3

Canonical

representation of band

pass signals

Chalk and Board a,b,e,h,k CO1 Text 1,Ref 1,2

4

Complex low pass

representation of

band-pass systems


5

Complex

representation of

bandpass signals and

systems


6

Line codes: Unipolar,

Polar, Bipolar (AMI).

Manchester code


7

Power spectral

densities of different

line coding

techniques.


8 Overview of HDB3 Chalk and Board a,b,e,h,k CO1 Text 1, Ref 1,2

9 Overview of B3ZS Chalk and Board a,b,e,h,k CO1 Text 1, Ref 1,2

10 Overview of B6ZS. Chalk and Board a,b,e,h,k CO1 Text 1, Ref 1,2

c. Question Bank

Sl. No. Questions COs

Attained

1 Compute Hilbert Transform of some standard signals CO 1

2 Define Pre envelop and Complex envelop of band pass signal. CO 1

3 Explain canonical representation of band pass signal CO 1

4 Explain complex low pass representation of bandpass signal. CO 1

5 Explain different line coding techniques for representing digital data CO 1

6 Write a note on HDB3, B3ZS and B6ZS. CO 1





Module 2 : Signaling over AWGN channels-Detection and Estimation Number of Hours :10

a. Learning objectives 1. Design optimum receiver for digital communication.

b. Lesson Plan

Lecture

No. Topics Covered

Teaching

Method

PO’s

Attained

CO’s

Attained

Text/Reference

book/

chapter no

1. Introduction Chalk and Board a,b,e,h,k CO 2 Text 1

2 Model of digital

communication system

Chalk and Board a,b,e,h,k CO 2 Text 1

3 Geometric representation

of signals


4

Gram-Schmidt

Orthogonalization

procedure

Chalk and Board a,b,e,h,k CO 2

Text 1

5

Conversion of the

continuous AWGN

channel into a vector

channel


Text 1

6 Optimum receivers using

coherent detection


7 ML Decoding Chalk and Board a,b,e,h,k CO 2 Text 1

8 Correlation receiver Chalk and Board a,b,e,h,k CO 2 Text 1

9 Matched filter receiver


10 Properties of Matched

Filter


c. Question Bank


Attained

1. Explain the model of a digital communication system. CO 2

2 Explain Gram-Schmidt Orthogonalization procedure. CO 2

3 Explain correlation type of receiver. CO 2

4 Explain ML decoding CO 2

5 Explain Matched filter receiver. CO 2

6 Explain the properties of match filter receiver CO 2





Module 3 : Digital Modulation Techniques Number of Hours :10

a. Learning objectives 1. Performance evaluation of different modulation techniques.

b. Lesson Plan

Lecture

No. Topics Covered

Teaching

Method

PO’s

Attained

CO’s

Attained

Text/Reference

book/

chapter no

1 Digital modulation formats Chalk and Board a,b,e,h,k CO 3 Text 1

2

Phase shift Keying

techniques using coherent

detection


Text 1

3 QPSK generation and

detection


4 Probability of error of

QPSK


5 M-ary PSK Chalk and Board a,b,e,h,k CO 3 Text 1

6

M-ary QAM , Frequency

shift keying techniques

using Coherent detection


Text 1

7 BFSK generation,detection

and error probability


8 Non coherent orthogonal

modulation techniques


9

BFSK, DPSK Symbol

representation, Block

diagrams treatment of

Transmitter and Receiver


Text 1

10 Probability of error Chalk and Board a,b,e,h,k CO 3 Text 1

c. Question Bank

Sl.

No. Questions

COs

Attained

1 Explain coherent PSK transmitter and receiver. Derive an expression for

probability of error of coherent PSK. CO 3

2 Explain QPSK transmitter and receiver. Derive an expression for probability

of error.

CO 3

3 Explain M-ary PSK transmitter and receiver CO 3

4 Explain M-ary QAM transmitter and receiver CO 3

5 Explain coherent FSK transmitter and receiver. Derive an expression for

probability of error of coherent FSK.

CO 3

6 Explain Non Coherent orthogonal modulation CO 3

7 Explain DPSK transmitter and receiver CO 3





Module 4 : Communication through Band Limited Channels Number of Hours :10

a. Learning objectives 1. Design of digital signal for band limited channel.

b. Lesson Plan

Lecture

No. Topics Covered

Teaching

Method

PO’s

Attained

CO’s

Attained

Text/Reference

book/

chapter no

1.

Digital Transmission

through Band limited

channels

Chalk and Board a,b,e,h,k CO 4 Text 2, Ref 2

2 Inter Symbol Interference

and Eye diagrams


3

Signal design for Band

limited ideal channel with

zero ISI


4 Nyquist Criterion (statement

only)


5 Sinc and Raised pulse

shaping


6

Signal design for Band

limited channel with

controlled ISI


7 Correlative coding, DB and

MDB,


8

Basic Concepts of

Equalization for non ideal

channels


9 ZFE, MMSE, (without

derivations)


10 Adaptive Equalizers (Block

diagram only)


c. Question Bank


Attained

1 Explain Eye diagram CO 4

2 Explain correlative coding CO 4

3 Explain Equalization of non ideal channel CO 4

4 Explain adaptive equalizer CO 4





Module 5 : Principles of Spread Spectrum Number of Hours :10

a. Learning objectives 1. Design of signals of spread spectrum communication.

b. Lesson Plan

Lecture

No. Topics Covered

Teaching

Method

PO’s

Attained

CO’s

Attained

Text/Reference

book/

chapter no

1.

Concept of Spread

Spectrum, Direct

Sequence/SS

Chalk and Board a,b,e,h,k CO5 Text 2

2 Frequency Hopped SS Chalk and Board a,b,e,h,k CO5 Text 2

3 Processing Gain Chalk and Board a,b,e,h,k CO5 Text 2

4 Interference, and probability

of error statement only


5 PN sequences for Spread

Spectrum


6 M- sequences with

Properties


7 Gold, Kasami sequences

with basic properties


8 Direct sequence spread

spectrum system concepts


9 Frequency Hopped Spread

spectrum system concepts,


10

Spread Spectrum

Synchronization (block

diagram treatment) - Code

Acquisition and Tracking.


c. Question Bank


Attained

1. Define spread spectrum. CO 5

2 Define PN sequence. List the properties of PN sequence. CO 5

3 Explain Direct sequence spread spectrum CO 5

4 Explain frequency hopped spread spectrum CO 5

5 Explain the block diagram of spread spectrum synchronization. CO 5

4. Portion for Internal Assessments

I.A Modules

I Model 1 and 2

II Model 3 and 4

III Model 5





5. Assignment Questions

Sl. No. Assignment I COs

Attained

1 Explain canonical representation of band pass signal CO 1

2 Explain complex low pass representation of bandpass signal. CO 1

3 Explain different line coding techniques for representing digital data CO 1

4 Explain Gram-Schmidt Orthogonalization procedure. CO 2

5 Explain correlation type of receiver. CO 2

Assignment II

1 Explain coherent PSK transmitter and receiver. Derive an expression for

probability of error of coherent PSK. CO 3

2 Explain QPSK transmitter and receiver. Derive an expression for

probability of error.

CO 3

3 Explain DPSK transmitter and receiver CO 3

4 Explain Equalization of non ideal channel CO 4

5 Explain adaptive equalizer CO 4

Assignment III

1 Define spread spectrum. CO 5

2 Define PN sequence. List the properties of PN sequence. CO 5

3 Explain Direct sequence spread spectrum CO 5

4 Explain frequency hopped spread spectrum CO 5

5 Explain the block diagram of spread spectrum synchronization. CO 5





COURSE: ARM Microcontroller & Embedded System

Semester: VI Year: 2017-18 (Even Semester)

Subject Code: 15EC62 IA Marks :20

Number of Lecture Hours/Week:04 VTU Exam Marks :80

Total Number of Lecture Hours :50 Exam Hours :3

Credits – 04

1. Syllabus PART-A

MODULE I: ARM-32 bit Microcontroller: Thumb-2 technology and applications of ARM, Architecture of

ARM Cortex M3, Various Units in the architecture, Debugging support, General Purpose

Registers, Special Registers, exceptions, interrupts, stack operation, reset sequence ---10 Hours

MODULE II : ARM Cortex M3 Instruction Sets and Programming: Assembly basics, Instruction list and

description, useful instructions, Assembly and C language Programming---10 Hours

MODULE III :

Embedded System Components: Embedded Vs General computing system, Classification of

Embedded systems, Major applications and purpose of ES. Core of an Embedded System

including all types of processor/controller, Memory, Sensors, Actuators, LED, 7 segment LED

display, Optocoupler, relay, Piezo buzzer, Push button switch, Communication Interface

(onboard and external types), Embedded firmware, Other system components.---10 Hours

MODULEIV : Embedded System Design Concepts: Characteristics and Quality Attributes of Embedded

Systems, Operational and non-operational quality attributes, Embedded Systems-Application and

Domain specific, Hardware Software Co-Design and Program Modelling (excluding UML),

Embedded firmware design and development (excluding C language). ---10 Hours

MODULE V : RTOS and IDE for Embedded System Design: Operating System basics, Types of operating

systems, Task, process and threads (Only POSIX Threads with an example program), Thread

preemption, Preemptive Task scheduling techniques, Task Communication, Task synchronization

issues – Racing and Deadlock, Concept of Binary and counting semaphores (Mutex example

without any program), How tochoose an RTOS, Integration and testing of Embedded hardware

and firmware, Embedded system Development Environment – Block diagram (excluding Keil),

Disassembler/decompiler, simulator, emulator and debugging techniques

---10 Hours

TEXT BOOKS: T1. JosephYiu, “The Definitive Guide to the ARM Cortex-M3”, 2nd Edition, Newnes,(Elsevier),

2010.

T2. Shibu K V, “Introduction to Embedded Systems”, Tata McGraw Hill Education Private

Limited, 2009.





Subject : ARM Microcontroller & EMBEDDED SYSTEM

Subject Code : 15EC62

2. Prerequisites for the course This subject requires the student to know about the

• Basic concepts of computer and C programming.

• Knowledge of microprocessor and microcontrollers.

3. Overview of the course Embedded system is a highly specialized branch of electronic engineering where the

technological advances of electronics and the design expertise of mechanical engineering work

hand-in-hand to deliver cutting edge technology and high end products to variety of diverse

domains. Computing system are everywhere, it is probably no surprise that millions of

computing system are built every year destined for desktop computer like personal computers,

laptops, workstations mainframes and servers. Here we are going to learn the essential aspects of

the hardware and software necessary for the design and development of contemporary embedded

systems and also the ARM Microcontroller.

4. Relevance to this program Billions of computing systems are built every year , that are embedded within larger electronic

and mechanical devices repeatedly carrying out particular function often going unrecognized by

device user. Creating precise definition of such embedded computing system, an embedded

system represent integration of computer hardware , software along with programming concepts

for developing special purpose computer system designed to specific one or few dedicated

function. Conventional microprocessors has been outdated, nowadays most of the embedded

designers prefer ARM controller. Hence it becomes very essential on the part of students to get

acquainted with the ARM controller, so as to cope up with the industry standards.

5. Course Outcomes After studying this course the student will be able to

1. Know the architecture of ARM processor and its concepts.

2. Evaluate the different instruction list, their description and programming language.

3. Define embedded system and describe its development environment.

4. Recall and Summarize the different components that make up the embedded system .

5. Analyze the concepts of RTOS/OS with respect to embedded system.

6. Applications 1 Mobile phones, Electronic gadgets , Washing machines etc

2 Automotive industry

3 Aeronautical and space application

4 Defense and Surveillance application

5 Biomedical instruments , industrial instrumentation devices and Process control devices

There are so many application of embedded system and ARM Controller for which there

is no boundary.





7. Unitwise Plan

Module I : ARM-32 bit Microcontroller Number of Hours: 10

Learning Objectives:

After studying this chapter students will be able to:

1. Describe the shortcomings of conventional microprocessors and how the ARM processors

overcome the same.

2.Know the functionalities of each unit of ARM processor.

3.Understand the concept of Interrupts and Exceptions

Lesson Plan:

Lecture

No Topics Covered

Teaching

Method

PO’s

Attained

CO’s

Attained

Reference

book/

chapter

no

L1 Thumb-2 technology and

applications of ARM

Chalk & Board

a,b,c,i

1 T1/ Ch-1

L2 Architecture of ARM Cortex

M3

Chalk & Board 1 T1/ Ch-1

L3 Various Units in the

architecture


L4 Debugging support Chalk & Board 1 T1/ Ch-2

L5 General Purpose Registers Chalk & Board 1 T1/ Ch-3

L6 Special Registers Chalk & Board 1 T1/ Ch-3

L7 Exceptions Chalk & Board 1 T1/ Ch-3

L8 Interrupts Chalk & Board 1 T1/ Ch-3

L9 Stack operation Chalk & Board 1 T1/ Ch-3

L10 Reset sequence Chalk & Board 1 T1/ Ch-3

Module II :ARM Cortex M3 Instruction Sets and

Programming Number of Hours: 10

Learning Objectives: After studying this chapter students will be able to:

1. Know the Instructions which are supported by ARM CORTEX M3.

2. Learn the basics of embedded programming.





Lesson Plan:

Lecture

No Topics Covered

Teaching

Method

PO’s

Attained

CO’s

Attained

Reference

book/

chapter no

L11 Assembly Basics Chalk & Board

a,b,d,e,i,

k

2 T1/ Ch-4

L12 Assembly Basics

Continued


L13 Instruction List Chalk & Board 2 T1/ Ch-4

L14 Instruction List

Continued


L15 Instruction Description Chalk & Board 2 T1/ Ch-4

L16 Useful instructions Chalk & Board 2 T1/ Ch-4

L17 Useful instructions

Continued


L18 Overview and

Development Flow


L19 Embedded C language

Programming


L20 Assembly Language

Programming


Module III :Embedded System Components. Number of Hours: 10


1. Know the significance of embedded systems in daily lives of people.

2. Understand the different actuators and sensors which could be interfaced with ARM

CORTEX M3.

3. Differentiate between an embedded system and a general purpose system

Lesson Plan:

Lecture

No Topics Covered

Teaching

Method

PO’s

Attained

CO’s

Attained

Reference

book/

chapter no

L21 Embedded Vs General

computing system

Chalk & Board a,b,c,d,h,

i,k

3 T2 / Ch-1

L22 Classification of

Embedded systems

Chalk & Board 3 T2 / Ch-1

L23 Major applications and

purpose of ES


L24

Core of an Embedded

System including all

types of

processor/controller

Chalk & Board 3,4 T2 / Ch-2

L25

Memory, Sensors,

Actuators, LED, 7

Segment LED Display


L26 Optocoupler, Relay, Chalk & Board 3,4 T2 / Ch-2





L27 Piezo Buzzer, Push

Button Switch


L28 Communication Interface

(onboard& external types)


L29 Embedded Firmware Chalk & Board 3,4 T2 / Ch-2

L30 Other system

components.


Assignments

Module IV: Embedded System Design Concepts Number of Hours: 10


1.Understand characteristics and quality attributes of embedded system.

2.Understand the concept of Hardware and Software co-design.

3.Understand embedded firmware design and development

Lesson Plan:

Lecture

No

Topics Covered Teaching

Method

PO’s

Attained

CO’s

Attained

Reference

book/

chapter no

L31 Characteristics of

Embedded Systems

Chalk & Board a, d,g,i 4 T2 / Ch-3

L32 Operational Quality

Attributes of Embedded

Systems


L33 Non-Operational Quality

Attributes of Embedded

Systems


L34 Embedded Systems-

Application Specific


L35 Embedded Systems-

Domain specific


L36 Fundamental Issues in

Hardware Software Co-

Design


L37 Program Modelling –

Computational Models in

Embedded Design


L38 Embedded Design

Firmware Approaches


L39 Embedded Firmware

Development Languages


L40 Programming in

Embedded ‘C’






Module V : RTOS and IDE for Embedded System Design Number of Hours: 10



1.Know the basic principles underlying the Real time operating system/operating system

2.Learn the scheduling , communication and synchronization techniques

3.Understand compilation,simulation,emulation,debugging techniques.

Lesson Plan:

Lecture

No Topics Covered

Teaching

Method

PO’s

Attained

CO’s

Attained

Reference

book/

chapter no

L41

Operating System basics ,

Types of operating

systems

Chalk & board a,g,i,k, 5 T2/Ch-10

L42 Task, Process and

Threads

Chalk & board 5 T2/Ch-10

L43

Thread Preemption ,

Preemptive Task

Scheduling techniques


L44 Task Communication Chalk & board 5 T2/Ch-10

L45

Task Synchronization

Issues & Techniques –

Racing and Deadlock


L46

Concept of Binary and

counting semaphores ,

How tochoose an RTOS


L47

Integration and testing of

Embedded Hardware and

Firmware


L48

Embedded System

Development

Environment – IDE


L49 Disassembler/Decompiler

, Simulator


L50 Emulator and Debugging

Techniques






Assignments -I

Assignment Questions COs attained

1. With a neat diagram,describe the architecture of ARM CORTEX

M3.

1

2. What is Thumb-2 technology?Briefly explain 1

3.How the interrupts and exceptions are dealt by ARM CORTEX M3. 1

4. List the different arithmetic instructions that are supported by ARM

CORTEX M3, along with example

2

5. List the different Branch instructions that are supported by ARM

CORTEX M3, along with example

2

Assignments -II


1. Discuss the applications of embedded systems. 3

2. Differentiate between the embedded system and general purpose

system

3

3. Describe the various actuators and sensors. 4

4.Explain the quality attributes and characteristics of embedded system. 3

5. Explain embedded firmware design. 4

Assignments -III


1.Explain semaphores and deadlocks in RTOS. 5

2.What are the different types of operating system and explain in brief. 5

3. Describe the different task scheduling techniques. 5

4.Explain how validation and testing is performed.

5

5. What is decompiler ? Mention the difference between simulate and

an emulator.

5

8. Portion for IA Test:

TEST Module No. CO’ s Attained

First IA Test I,II 1,2

Second IA Test III,IV 3,4

Third IA test V 5





9. Program Outcomes:

a. An ability to apply knowledge of mathematics, science and engineering.

b. An ability to design and conduct experiments as well as to analyze and interpret data in

the field of Electronics & Communication engineering.

c. An ability to design a system, component or process to meet desired needs within

realistic constraints such as economic, environmental, social, political, ethical, health and

safety manufacturability and sustainability.

d. An ability to function on multi-disciplinary teams.

e. An ability to identify, formulate and solve Electronics & Communication engineering

related problems.

f. An understanding of professional and ethical responsibility.

g. An ability to communicate effectively.

h. The broad education necessary to understand the impact of Electronics &

Communication engineering solutions in a global, economic, environmental and societal

context.

i. A recognition of the need for and an ability to engage in lifelong learning.

j. A knowledge of contemporary issues in Electronics & Communication engineering.

k. An ability to use the techniques, skills and modern engineering tools necessary for

Electronics & Communication engineering practices.


V.P. Dr.P.G.Halakatti College of Engineering & Technology, BIJAPUR – 586 103


Programme: B.E in Electronics and Communication Engineering

VLSI Design

1. Course syllabus

Semester: VI Year: 2015-16(Even)

Subject code: 10EC63 IA Marks : 20

Total Contact Hours : 50 hrs Hours per week : 4 hrs

VTU Exam Marks : 80 Exam : 3 Hours

Module-1

Introduction: A Brief History, MOS Transistors, MOS Transistor Theory, Ideal

IVCharacteristics, Non-ideal I-V Effects, DC Transfer Characteristics (1.1, 1.3, 2.1, 2.2, 2.4,

2.5 of TEXT 2).

Fabrication: nMOS Fabrication, CMOS Fabrication [P-well process, N-well process,Twin

tub process], BiCMOS Technology (1.7, 1.8,1.10 of TEXT 1).

Module-2

MOS and BiCMOS Circuit Design Processes: MOS Layers, Stick Diagrams, DesignRules

and Layout.Basic Circuit Concepts: Sheet Resistance, Area Capacitances of Layers,

StandardUnit of Capacitance, Some Area Capacitance Calculations, Delay Unit, Inverter

Delays,Driving Large Capacitive Loads (3.1 to 3.3, 4.1, 4.3 to 4.8 of TEXT 1).

Module-3

Scaling of MOS Circuits: Scaling Models & Scaling Factors for Device

ParametersSubsystem Design Processes: Some General considerations, An illustration of

DesignProcesses, Illustration of the Design Processes- Regularity, Design of an

ALUSubsystem, The Manchester Carry-chain and Adder Enhancement Techniques(5.1, 5.2,

7.1, 7.2, 8.2, 8.3, 8.4.1, 8.4.2 of TEXT 1).

Module-4

Subsystem Design: Some Architectural Issues, Switch Logic, Gate(restoring) Logic,Parity

Generators, Multiplexers, The Programmable Logic Array (PLA)(6.1 to 6.3, 6.4.1, 6.4.3,

6.4.6 of TEXT1).

FPGA Based Systems: Introduction, Basic concepts, Digital design and FPGA’s,

FPGAbased System design, FPGA architecture, Physical design for FPGA’s(1.1 to 1.4, 3.2,

4.8 of TEXT 3).

Module-5

Memory, Registers and Aspects of system Timing- System Timing Considerations,Some

commonly used Storage/Memory elements (9.1, 9.2 of TEXT 1). Testing and Verification:

Introduction, Logic Verification, Logic Verification Principles, Manufacturing Test

Principles, Design for testability (12.1, 12.1.1, 12.3, 12.5,12.6 of TEXT 2).





Question paper pattern:

• The question paper will have ten questions.

• Each full question consists of 16marks.

• There will be 2 full questions (with a maximum of four sub questions) from each module.

• Each full question will have sub questions covering all the topics under a module.

• The students will have to answer 5 full questions, selecting one full question from each

module.

Text Book: 1. “Basic VLSI Design”- Douglas A. Pucknell & Kamran Eshraghian, PHI 3rdEdition

(original Edition – 1994).

2. “CMOS VLSI Design- A Circuits and Systems Perspective”- Neil H.E. Weste, David

Harris, Ayan Banerjee, 3rd Edition, Pearson Education.

3. “FPGA Based System Design”-Wayne Wolf, Pearson Education, 2004,Technology and

Engineering.

2. Prerequisite: This subject requires the students to know the following:

1) Knowledge of Basic Electronics.

2) Basic course in Analog Electronics.

3) Basic course in Digital Electronics

3. Overview of the course: This course provides an introduction to the design and implementation of VLSI

circuits for complex digital systems. The focus is on CMOS technology. Issues to be covered

include deep submicron design, clocking, power dissipation, testing and design methodology.

The course includes a laboratory component in which student will design the schematic and

layout for the digital circuits.

The aim of course is to learn how to design and implement VLSI digital circuits

and optimize them with respect to different objectives such as area, speed, and power. The

course discusses about the VLSI complexity and design flow, CMOS device as an ideal

switches & Boolean operations. The physical structure of CMOS IC’s, & designing of FETs

as an array, the basic concepts of layout and Cell concepts is explained. Electronics Analysis

of CMOS Logic gates which includes the DC-Analysis & Transient Analysis of Inverter &

Basic Gates. Discussion also includes Designing of High Speed CMOS Logic Networks

including gate delays & driving load capacitors, and Advanced Techniques in CMOS Logic

Circuits. Design and analysis will be carried out using computer-aided tools along with this

understanding and manipulation of VLSI circuit-design methods.

4. Relevance of the course: As said in course overview, this course gives fair idea about CMOS VLSI Technology which

is a professional core subject of this program. The course also helps in understanding ICs

design concepts and this is a basic course to VLSI specialization so the course is very much

relevant to this program.

The course discusses about the VLSI complexity and design flow, CMOS device as an ideal

switches & Boolean operations. The physical structure of CMOS IC’s, & designing of FETs

as an array, the basic concepts of layout and Cell concepts is explained.





5. Course outcomes:

After studying this course, students will be able to: 1. Explain basics of MOS technology and various MOS devices also different fabrication

techniques.

2. Develop an insight into methods and means for materializing circuit design in silicon and

design different CMOS logic structures also Calculate sheet resistance, area capacitance,

& delay calculation.

3. Discuss different scaling models and scaling factors, design process of ALU subsystem,

Adder technique.

4. Design and optimization of MOS circuits and subsystems, FPGA based system design.

5. Design different memories and analyze the design for testing and IC testing methods.

6. Applications 1. DSP.

2. Communications.

3. Microwave and RF.

4. MEMS.

5. Cryptography.

6. Consumer Electronics.

7. Automobiles

8. Space Applications

9. Robotics.

10. Health domain.

11. Agriculture

7. UNITWISE PLAN

MODULE-1 : INTRODUCTION AND FABRICATION Number of Hours : 10


1) Explain the operation of MOS transistor and its I-V characteristics.

2) Explain the MOS transistor DC Transfer characteristics.

3) Elaborate the n-MOS, CMOS and Bi-CMOS fabrication Process.





Lesson Plan:

Lecture

No


Method

PO’s

Attained

CO’s

Attained

Reference

book/

chapter no

L1 A Brief history. Chalk & Board a, b, e, i 1 T2/1

L2 MOS Transistors, MOS

Transistor theory.

Chalk & Board 1 T2/1

L3 Ideal I-V Characteristics. Chalk & Board 1 T2/2

L4 Non-ideal I-V Effects. Chalk & Board 1 T2/2

L5 DC Transfer Characteristics Chalk & Board 1 T2/2

L6 DC Transfer Characteristics. Chalk & Board 1 T2/2

L7 nMOS Fabrication Chalk & Board 1 T1/1

L8 CMOS Fabrication [P-well

process]


L9 CMOS Fabrication [n-well

process], Twin tub process


L10 Bi-CMOS Technology Chalk & Board 1 T1/1

MODULE 2: MOS AND BICMOS CIRCUIT DESIGN PROCESS

AND BASIC CIRCUIT CONCEPTS Number of Hours : 10


1) Draw the Stick diagrams for basic Digital Circuits.

2) Apply the lambda-based design rules and other rules for the Layout design.

3) Draw and Explain the Layout for Digital Circuits.

4) Calculate of sheet resistance, capacitance, Delay unit, Inverter delay calculation and driving

Large capacitive loads.

Lesson Plan:

Lecture

No Topics Covered

Teaching

Method

PO’s

Attained

CO’s

Attained

Reference

book/

chapter no

L11 MOS layers, Stick diagrams. Chalk & board

a, b, e,

i, k

2 T1/ 3

L12 Design rules Chalk & board 2 T1/ 3

L13 Design rules Chalk & board 2 T1/ 3

L14 Layout diagrams. Chalk & board 2 T1/ 3

L15 Layout diagrams Chalk & board 2 T1/ 3

L16 Sheet resistance calculation Chalk & board 2 T1/4

L17 Area capacitance of layers. Chalk & board 2 T1/ 4

L18 Standard unit of capacitance, some

area capacitance calculations Chalk & board 2 T1/ 4

L19 Delay unit, Inverter delays Chalk & board 2 T1/ 4

L20 Driving large capacitance loads Chalk & board 2 T1/ 4





Module 3: SCALING OF MOS CIRCUITS, SUBSYSTEM

DESIGN PROCESS, ILLUSTRATION OF THE DESIGN

PROCESS

Number of Hours : 10



1) Explain different scaling models and factors for different parameters.

2) Explain general considerations and illustrate the design process

3) Design ALU subsystem, Adder and Manchester carry-chain.

Lesson Plan:

Lecture

No Topics Covered

Teaching

Method

PO’s

Attained

CO’s

Attained

Reference

book/

chapter no

L21 Scaling of MOS Circuits:

Scaling Models.

Chalk & board a, b, d, e,

i, k

3 T1/5

L22 Scaling Models. Chalk & board 3 T1/5

L23 Scaling Factors for Device

Parameters.

Chalk & board 3 T1/5

L24 Scaling Factors for Device

Parameters.


L25 Subsystem Design Processes: Some General

considerations


L26 An illustration of Design

Processes.


L27 Illustration of the Design Processes- Regularity


L28 Design of an ALU

Subsystem


L29 The Manchester Carry-

chain


L30 Adder Enhancement

Techniques






Module 4: SUB SYSTEM, FPGA BASED SUBSYSTEMS Number of Hours : 10


1) Explain some architectural issues.

2) Distinguish switch logic and gate logic.

3) Design Parity generators, Multiplexers and PLA.

4) Explain the basic concept of FPGA based systems.

5) Design FPGA based system design.

Lesson Plan:

Lecture

No Topics Covered

Teaching

Method

PO’s

Attained

CO’s

Attained

Reference

book/

chapter no

L31 Subsystem Design: Some

Architectural Issues. Chalk & board

a, b, d, e,

i, 4

T1/6

L32 Switch Logic, Gate(restoring)

Logic. Chalk & board 4

T1/6

L33 Parity Generators. Chalk & board 4 T1/6

L34 Multiplexers. Chalk & board 4 T1/6

L35 FPGA Based Systems: Introduction, Basic concepts.


L36 Digital design and FPGA’s. Chalk & board 4 T3/1

L37 FPGA based System design. Chalk & board 4 T3/3

L38 FPGA architecture Chalk & board 4 T3/3

L39 FPGA architecture Chalk & board 4 T3/3

L40 Physical design for FPGA’s Chalk & board 4 T3/4

Module 5: MEMORY, REGISTERS AND ASPECT OF SYSTEM TIMING, TEST AND VARIFICATION



1. Explain different timing considerations.

2. Design static and dynamic memories.

3. Explain verification logic, principles and manufacturing test principles.

4. Design for testability.





Lesson Plan:

Lectur

e No Topics Covered

Teaching

Method

PO’s

Attained

CO’s

Attained

Reference

book/

chapter no

L41 Memory, Registers and Aspects of system Timing- System

Timing Considerations

Chalk & board a, b, d, e,

i,

5 T1/9

L42 Some commonly used

Storage/Memory elements








L45 Testing and Verification:

Introduction.


L46 Logic Verification Chalk & board 5 T2/12

L47 Logic Verification Principles. Chalk & board 5 T2/12

L48 Manufacturing Test Principles. Chalk & board 5 T2/12

L49 Design for testability Chalk & board 5 T2/12

L50 Design for testability Chalk & board 5 T2/12


TEST UNITS COs attained

First IA Test Module 1 and module 2 1, 2

Second IA Test Module 3 and module 4 3, 4

Third IA test Module 4 and module 5 4, 5

1st Assignment questions:

1. Derive the expression for Ids in saturated & non-saturated region.

2. Draw and explain the static transfer characteristics of CMOS inverter.

3. Elaborate the n-MOS, CMOS and Bi-CMOS fabrication Process.

4. Draw the Layout for Y=ABC+ADC+BDC(ACB+DEF+1)

5. With an example explain the calculation of sheet resistance & area capacitance.

2nd

Assignment questions: 1. Explain scaling factor for device parameters.

2. Design 4-bit barrel shifter.

3. Design 4-bit Adder.

4. Design 4 bit ALU subsystem arrangement.

5. Explain parity generator concept, design cmos parity and draw stick and a layout.

3rd

Assignment questions: 1. Draw 4-bit cmos multiplexer stick and layout diagram.

2. Discuss the physical design steps of a FPGA.

3. Explain 3T dynamic , 4T dynamic and 6T static memory.

4. Explain Pseudo nMOS and Dynamic CMOS logic structure.

5. Explain the logic verification principles.





1. List of PO’s: a: An ability to apply knowledge of mathematics, science, and engineering.

b: An ability to design and conduct experiments, as well as to analyze and interpret data.

c: An ability to design a system, component, or process to meet desired needs within

realistic constraints such as economic, environmental, social, political, ethical, health

and safety, manufacturability and sustainability.

d: An ability to function on multidisciplinary teams.

e: An ability to identify, formulate, and solve engineering problems.

f: An understanding of professional and ethical responsibility

g: An ability to communicate effectively (Oral)

g: An ability to communicate effectively (Written)

h: The broad education necessary to understand the impact of engineering solutions in a

global, economic, environmental and societal context.

i: A recognition of the need for, and an ability to engage in life-long learning.

j: A knowledge of contemporary issues.

k: An ability to use the techniques, skills, and modern engineering tools necessary for

engineering practice.





10. VTU Question Paper





















COURSE: COMPUTER COMMUNICATION NETWORKS



Total Contact Hours : 50 hrs (10 Hours / Module) Hours per week : 4 hrs


1. Course Details

1.1 SYLLABUS

Module-1

Introduction: Data Communications: Components, Representations, Data Flow, Networks:

Physical Structures, Network Types: LAN, WAN, Switching, Internet.

Network Models: Protocol Layering: Scenarios, Principles, Logical Connections, TCP/IP

Protocol Suite: Layered Architecture, Layers in TCP/IP suite, Description of layers,

Encapsulation and Decapsulation, Addressing, Multiplexing and Demultiplexing, The OSI

Model: OSI Versus TCP/IP.

Data-Link Layer: Introduction: Nodes and Links, Services, Categories’ of link, Sublayers,

Link Layer addressing: Types of addresses, ARP. Data Link Control (DLC) services:

Framing, Flow and Error Control, Data Link Layer Protocols: Simple Protocol, Stop and

Wait protocol, Piggybacking.

Module-2

Media Access Control: Random Access: ALOHA, CSMA, CSMA/CD, CSMA/CA.

Controlled Access: Reservation, Polling, Token Passing.

Wired LANs: Ethernet: Ethernet Protocol: IEEE802, Ethernet Evolution, Standard

Ethernet: Characteristics, Addressing, Access Method, Efficiency, Implementation, Fast

Ethernet: Access Method, Physical Layer, Gigabit Ethernet: MAC Sublayer, Physical Layer,

10 Gigabit Ethernet.

Module-3

Wireless LANs: Introduction: Architectural Comparison, Characteristics, IEEE 802.11:

Architecture, MAC sub layer, Addressing Mechanism, Physical Layer, Bluetooth:

Architecture, Layers.

Connecting Devices: Hubs, Switches, Virtual LANs: Membership, Configuration,

Communication between Switches, Advantages.

Network Layer: Introduction, Network Layer services: Packetizing, Routing and

Forwarding, Other services, Packet Switching: Datagram Approach, Virtual Circuit

Approach, IPV4 Addresses: Address Space, Classful Addressing, Classless Addressing,

DHCP, Network Address Resolution, Forwarding of IP Packets: Based on destination

Address and Label.





Module-4

Network Layer Protocols: Internet Protocol (IP): Datagram Format, Fragmentation,

Options, Security of IPv4 Datagrams, ICMPv4: Messages, Debugging Tools, Mobile IP:

Addressing, Agents, Three Phases, Inefficiency in Mobile IP.

Unicast Routing: Introduction, Routing Algorithms: Distance Vector Routing, Link State

Routing, Path vector routing, Unicast Routing Protocol: Internet Structure, Routing

Information Protocol, Open Shortest Path First, Border Gateway Protocol Version 4.

Module-5

Transport Layer: Introduction: Transport Layer Services, Connectionless and Connection

oriented Protocols, Transport Layer Protocols: Simple protocol, Stop and wait protocol, Go-

Back-N Protocol, Selective repeat protocol, User Datagram Protocol: User Datagram, UDP

Services, UDP Applications, Transmission Control Protocol: TCP Services, TCP Features,

Segment, Connection, State Transition diagram, Windows in TCP, Flow control, Error

control, TCP congestion control.

TEXT BOOK:

T1. Data Communications and Networking, Forouzan, 5th Edition, McGraw Hill, 2016

ISBN: 1-25-906475-3

REFERENCE BOOKS:

R1. Computer Networks, James J Kurose, Keith W Ross, Pearson Education, 2013, ISBN: 0-

273-76896-4

R2. Introduction to Data Communication and Networking, Wayarles Tomasi, Pearson

Education, 2007, ISBN: 0130138282

1.2 Prerequisite:

The prerequisite for this subject includes

4) Digital communication concepts, line formats, digital modulation techniques.

5) Information theory and coding concepts, CRC code, matrix method for generating

code words, etc.

6) Basics of computer networking.

Overview of the course

This course represents four basic concepts: data communications, networking, protocols, and

standards. The course is designed to understand the concepts of basic network principle and

protocols used for the communication based on reference models.





Relevance of the course to this Program

Data communication between remote parties can be achieved through a process called

networking, involving the connection of computers, media, and networking devices.

Networks are divided into LANs, WANs. Protocols and standards are vital to implementation

of data communications and networking. Network models serve to organize, unify and

control the hardware and software components of data communications and networking.

Course Outcomes (COs):

After studying this course, students will be able to:

1) Able to appreciate data communication principles, Networks modules like OSI

and TCP along with concept related to data link layer

2) Gain knowledge about various media access control schemes with ALOHA,

CSMA and its various concepts of wired LANs in the form of efficiency

Implements to generations of Ethernet.

3) Apply knowledge of various LANs into wireless LANs and connecting devices

such as Hubs and switches along with network layer functionality

4) Appreciate the various network layer protocol and unicast routing protocol

5) Gain the knowledge about TCP, UDP, flow control and error control.

1.6 Applications

1. The main application of computer network is “Resource Sharing” because of

reliability and parallel processing.

2. Implementation of various Networks like LANs,WANs etc.

3. Design and maintenance of a computer network for an organization or company.

2. MODULEWISE PLAN

Module 1: Introduction , Network Models, Data-Link Layer.


a. Learning Objectives:

1. Understand data communication basics like components Representations, Data Flow

along with Physical Structures, Network Types and Switching.

2. Gain knowledge about protocol layering principles involved along with architectures

of reference modules like OSI and TCP/IP and also functions like Encapsulation and

Decapsulation, Addressing, Multiplexing and Demultiplexing

3. To learn various functionality of data link layer like Nodes and Links, Services,

Categories’ of link.

4. To study various Sublayers functionalities, Types of addresses and Address resolution

protocols

5. To understand data link services like Framing, Flow and Error Control and various

protocols at Data Link Layer like Simple Protocol, Stop and Wait protocol,

Piggybacking.





b. Lesson Plan:

Lectur

e No Topics Covered

Teaching

Method

PO’s

Attained

CO’s

Attained

Reference

book/

chapter no

L1

Introduction: Data

Communications, Components,

Representations, Data Flow,

Networks: Physical Structures,

Chalk & Board

a, c, e

1 T1/1

L2

Network Types: LAN, WAN,

Switching, Internet.

Chalk & Board

1 T1/1

L3 Protocol Layering: Scenarios,

Principles, Logical Connections,


L4

TCP/IP Protocol Suite: Layered

Architecture, Layers in TCP/IP

suite,


L5

Description of layers,

Encapsulation and

Decapsulation, Addressing,

Multiplexing and

Demultiplexing,

Chalk & Board

1 T1/2

L6 The OSI Model: OSI Versus

TCP/IP.


L7

Data-Link Layer: Introduction:

Nodes and Links, Services,

Categories’ of link,

Chalk & Board

1 T1/2

L8

Sublayers, Link Layer

addressing: Types of addresses,

ARP.

Chalk & Board

1 T1/2

L9

Data Link Control (DLC)

services: Framing, Flow and

Error Control,

Chalk & Board

1 T1/2

L10

Data Link Layer Protocols:

Simple Protocol, Stop and Wait

protocol, Piggybacking.

Chalk & Board

1 T1/2

c. Question Bank COs attained

1. Define data communication?. Explain components of data

communication 1

2. Explain with neat diagram TCP/IP protocol suit 1

3. Explain with neat diagram the OSI model 1

4. Explain with neat diagram Address resolution protocol 1

5. Explain with neat diagram simple and stop and wait protocol 1





Module 2: Media Access Control, Wired LANs: Ethernet. Number of Hours : 10


1. Define and explain the concept of Media Access Control Protocol

2. Describe Wired LANs. Network

3. Explanations of Ethernet Standards

b. Lesson Plan:

Lecture

No Topics Covered

Teaching

Method

PO’s

Attained

CO’s

Attained

Reference

book/

chapter no

L11 Random Access: ALOHA,

CSMA

Chalk & Board

a, c, e

2 T1/3

L12

CSMA/CD, CSMA/CA


L13 Controlled Access:

Reservation


L14 Polling, Token Passing Chalk & Board 2 T1/3

L15

Ethernet Protocol: IEEE802,

Ethernet Evolution, Standard

Ethernet: Characteristics


L16 Addressing, Access Method,

Efficiency


L17 Implementation, Fast

Ethernet: Access Method,


L18 Physical Layer Chalk & Board 2 T1/4

L19 Gigabit Ethernet: MAC

Sublayer


L20 Physical Layer, 10 Gigabit

Ethernet


c. Question Bank

Question Bank COs attained

1. Explain with neat diagram ALOHA, CSMA protocol 2

2. Explain with neat diagram Polling, Token Passing 2

3. Explain IEEE802, Ethernet Evolution, Ethernet Characteristics 2

4. Explain with neat diagram MAC Sub layer. 2

5. Explain Physical Layer. 2





Module 3: Wireless LANs, Connecting Devices, Network Layer. Number of Hours : 06


1. Understand Architectural Comparison, Characteristics, IEEE 802.11

2. To study Architecture, MAC sub layer, Addressing Mechanism

3. To study Physical Layer, Bluetooth: Architecture, Layers.

4. To learn Network Layer services and Packetizing

5. To learn IPV4 Addresses: Address Space, Classful Addressing, Classless Addressing

Label

b. Lesson Plan:

Lecture

No Topics Covered

Teaching

Method

PO’s

Attained

CO’s

Attained

Reference

book/

chapter no

L21

Introduction: Architectural

Comparison,

Characteristics, IEEE

802.11

Chalk & Board

a, c, e

3 T1/5

L22

Architecture, MAC sub

layer, Addressing

Mechanism,


L23 Physical Layer, Bluetooth:

Architecture, Layers.


L24

Hubs, Switches, Virtual

LANs: Membership,

Configuration,

Communication between

Switches, Advantages.

Chalk & Board

3 T1/5

L25 Introduction, Network Layer

services: Packetizing


L26 Routing and Forwarding,

Other services,


L27

Packet Switching: Datagram

Approach, Virtual Circuit

Approach

Chalk & Board

3 T1/6

L28

, IPV4 Addresses: Address

Space, Classful Addressing,

Classless Addressing Label

Chalk & Board

3 T1/6

L29 , DHCP, Network Address

Resolution


L30

, Forwarding of IP Packets:

Based on destination

Address and

Chalk & Board

3 T1/6





c. Question bank

Question Bank COs attained

1. Explain Architectural Comparison, Characteristics, IEEE 802.11 3

2. Explain with diagram DHCP, Network Address Resolution 3

3. Explain Network Layer services: Packetizing 3

4. Distinguish between Packet Switching, Datagram Approach and

Virtual Circuit Approach 3

5. Explain Address Space, Classful Addressing, Classless

Addressing Label 3

4

Module 4: Network Layer Protocols, Unicast Routing Number of Hours : 10


1. To learn Internet Protocol (IP), ICMPv4

2. To Study Mobile IP: Addressing, Agents, Three Phases, Inefficiency in Mobile IP.

3. To learn Routing Algorithms, Path vector routing

4. To learn Internet Structure, Routing Information Protocol

5. To study Open Shortest Path First routing protocol

b. Lesson Plan:

Lecture

No Topics Covered

Teaching

Method

PO’s

Attained

CO’s

Attained

Reference

book/

chapter no

L31

Internet Protocol (IP):

Datagram Format,

Fragmentation, Options,

Security of IPv4 Datagrams,

Chalk & Board

a, c, e

4 T1/7

L32 ICMPv4: Messages, Debugging

Tools, Chalk & Board 4 T1/7

L33

Mobile IP: Addressing, Agents,

Three Phases, Inefficiency in

Mobile IP.


L34 Introduction, Routing

Algorithms: Chalk & Board 4 T1/7

L35 Distance Vector Routing, Chalk & Board 4 T1/7

L36 Link State Routing, Chalk & Board 4 T1/7

L37 Path vector routing, Unicast

Routing Protocol: Chalk & Board 4 T1/7

L38 Internet Structure, Routing

Information Protocol Chalk & Board 4 T1/7

L39 , Open Shortest Path First, Chalk & Board 4 T1/7

L40 Border Gateway Protocol

Version 4. Chalk & Board 4 T1/7





a. Questions Bank COs attained

1. Explain Internet Protocol (IP), ICMPv4 4

2 .Explain Mobile IP: Addressing, Agents, Three Phases, Inefficiency in

Mobile IP. 4

3 Explain Routing Algorithms, Path vector routing 4

4.Explain Internet Structure, Routing Information Protocol 4

5.Explain Open Shortest Path First routing protocol 4

Module 5: Transport Layer Number of Hours : 10


1. Describe the concepts involved in Transport Layer Services, Connectionless and

Connection oriented Protocols.

2. Explain the concepts of Simple protocol, Stop and wait protocol, Go-Back-N Protocol

3. Summarize User Datagram, UDP Services, UDP Applications.

b. Lesson Plan:

Lecture

No Topics Covered

Teaching

Method

PO’s

Attained

CO’s

Attained

Reference

book/

chapter no

L41

Introduction: Transport Layer

Services, Connectionless and

Connection oriented Protocols,

Chalk & Board

a, c, e

5 T1/10

L42 Transport Layer Protocols: Simple

protocol, Stop and wait protocol,


L43 Go-Back-N Protocol, T1/10

L44 Selective repeat protocol, Chalk & Board 5 T1/11

L45

User Datagram Protocol: User

Datagram, UDP Services, UDP

Applications,


L46 Transmission Control Protocol:

TCP Services,


L47 TCP Features, Segment,

Connection,


L48 State Transition diagram, Windows

in TCP,


L49 Flow control, Error control, Chalk & Board 5 T1/11

L50 TCP congestion control Chalk & Board 5 T1/11





c. Questions Bank

Questions Bank COs attained

1. Explain the Transport Layer Services, Connectionless and

Connection oriented Protocols 5

2. Explain TCP Services, TCP Features, Segment, Connection State

Transition diagram, Windows in TCP 5

3. Differentiate between TCP and UDP protocol 5

4. With neat diagram Flow control, Error control, TCP congestion

control 5

5. Explain Go-Back-N Protocol 5

3. Portion for I.A Test:

Test Modules COs

I I.A Test Module 1,2 1,2

II I.A Test Module 3,4 3,4

III I.A Test Module 5 5






Assignment - I COs attained

1. Define data communication?. Explain components of data

communication. 1

2. Explain with neat diagram the OSI model. 1

3. Explain with neat diagram Address resolution protocol 1

4. Explain with neat diagram ALOHA, CSMA protocol 2

5. Explain with neat diagram Polling, Token Passing 2

Assignment – II COs attained

1. Explain Architectural Comparison, Characteristics, IEEE802.11 3

2. Explain with diagram DHCP, Network Address Resolution 3

3. Explain Network Layer services: Packetizing 3

4. Explain Routing Algorithms, Path vector routing 4

5. Explain Internet Structure, Routing Information Protocol 4

Assignment – III COs attained

1. Explain the Transport Layer Services, Connectionless and

Connection oriented Protocols 5

2. Explain TCP Services, TCP Features, Segment, Connection

State Transition diagram, Windows in TCP 5

3. Differentiate between TCP and UDP protocol 5

4. With neat diagram Flow control, Error control, TCP congestion

control 5

5. Explain Go-Back-N Protocol 5

1. List of PO’s:

a: An ability to apply knowledge of mathematics, science, and engineering.


















COURSE: ARTIFICIAL NEURAL NETWORK





2. Course Details

2.1 SYLLABUS Module-1

Introduction: Biological Neuron – Artificial Neural Model - Types of activation functions –

Architecture: Feed forward and Feedback, Convex Sets, Convex Hull and Linear

Separability, Non-Linear Separable Problem. Xor Problem, Multilayer Networks. Learning:

Learning Algorithms, Error correction and Gradient Descent Rules, Learning objective of

TLNs, Perceptron Learning Algorithm, Perceptron Convergence Theorem.

Module-2

Supervised Learning: Perceptron learning and Non Separable sets, α-Least Mean Square

Learning, MSE Error surface, Steepest Descent Search, µ-LMS approximate to gradient

descent, Application of LMS to Noise Cancelling, Multi-layered Network Architecture, Back

propagation Learning Algorithm, Practical consideration of BP algorithm.

Module-3 Support Vector Machines and Radial Basis Function: Learning from Examples,

Statistical Learning Theory, Support Vector Machines, SVM application to Image

Classification, Radial Basis Function Regularization theory, Generalized RBF Networks,

Learning in RBFNs, RBF application to face recognition.

Module-4

Attractor Neural Networks: Associative Learning Attractor Associative Memory, Linear

Associative memory, Hopfield Network, application of Hopfield Network, Brain State in a

Box neural Network, Simulated Annealing, Boltzmann Machine, Bidirectional Associative

Memory.

Module-5 Self-organization Feature Map: Maximal Eigenvector Filtering, Extracting Principal

Components Generalized Learning Laws, Vector Quantization, Self-organization Feature

Maps, Application of SOM, Growing Neural Gas.

TEXT BOOK:

Text Books: 1. Neural Networks A Classroom Approach– Satish Kumar, McGraw Hill

Education (India) Pvt. Ltd, Second Edition

REFERENCE BOOKS:

R1. Introduction to Artificial Neural Systems- J.M. Zurada, Jaico Publications 1994.

R2. Artificial Neural Networks- B. Yegnanarayana, PHI, New Delhi 1998





1.2 Prerequisite: The prerequisite for this subject includes

• Basic concepts of computer and programming.

• Knowledge of data analysis and classification for different application.

• Basic concept of machine learning.

The above topics help the students to understand the concepts of this subject in an efficient

way.

1.3 Overview of the course This course provides an introduction to the basic functions and some important

concepts used in modern machine learning systems. The course briefly discuss about

Biological Neuron – Artificial Neural Model, Supervised Learning, support vector machine,

Attractor Neural Networks, self organization.

1.4 Relevance of the course to this Program This Course is helpful to understand the Artificial Neural Model, which is an essential

tool for classification objects using artificial knowledge gained by system. Perceptron

learning is required to understand the probability of data being in one or more group. The

subject provides even application of LMS to Noise Cancelling, Multi-layered Network

Architecture, Backpropagation Learning Algorithm. Thus for an Electronics and

Communication student the subject provides enough information about interface and analyze

data using computer.

1.5 Course Outcomes (COs): After studying this course, students will be able to:

1. Explain basic concepts involved in biological neurons and neural network basics.

2. Analyze the basic functions involved in Supervised machine Learning methods.

3. Describe the concepts used in Support Vector Machines and Radial Basis Function.

4. Explain the features of Attractor Neural Networks concepts

5. Summarize the methods used for Self-organization and Feature Map in ANN.

1.6 Applications

1. The subject helps to understand the basic concepts of machine learning developed for

artificial intelligence. After studying this subject the student can easily understand the

algorithms used in machine learning system.

2. The student can apply this knowledge to build data classifications models.

3. The study of this subject also helps to understand clustering concept.

4. The student can also think and apply his mind to develop artificial knowledge based

algorithms.

5. The subject also provides application of LMS to Noise Cancelling.





2. MODULEWISE PLAN

Module 1: Introduction

Number of Hours : 8

d. Learning Objectives:

6. Explain the concept involved in biological Neuron.

7. Types of activation functions and their architecture.

8. Describe Multilayer Networks.

9. Explain the basics of Learning Algorithms.

10. Describe perceptron Convergence Theorem.

e. Lesson Plan:

Lecture

No Topics Covered

Teaching

Method

PO’s

Attained

CO’s

Attained

Reference

book/

chapter no

L1 Biological Neuron – Artificial

Neural Model.

Chalk & Board

a, i, k

1 T/2,3,4

L2

Types of activation functions –

Architecture: Feed forward and

Feedback,

Chalk & Board 1 T/2,3,4

L3

Convex Sets, Convex Hull and

Linear Separability, Non-Linear

Separable Problem

Chalk & Board

1 T/2,3,4

L4 Xor Problem, Multilayer

Networks.


L5

Learning: Learning Algorithms,

Error correction and Gradient

Descent Rules,

Chalk & Board

1 T/2,3,4

L6 Learning objective of TLNs, Chalk & Board 1 T/2,3,4

L7 Perceptron Learning Algorithm, Chalk & Board 1 T/2,3,4

L8 Perceptron Convergence

Theorem


Module 2: Supervised Learning

Number of Hours : 8


4. Explain α-Least Mean Square Learning, MSE Error surface.

5. Describe Application of LMS to Noise Cancelling,.

6. Explain OS view of processes.

7. Summarize Architecture of Back propagation Learning Algorithm

8. Explain Practical application of BP algorithm





e. Lesson Plan:

Lecture

No Topics Covered

Teaching

Method

PO’s

Attained

CO’s

Attained

Reference

book/

chapter no

L9 Perceptron learning and Non

Separable sets,

Chalk & Board

a, b, e, k

2 T/5,6

L10 α-Least Mean Square Learning,

MSE Error surface,

Chalk & Board 2 T/5,6

L11 Steepest Descent Search, Chalk & Board 2 T/5,6

L12 µ-LMS approximate to gradient

descent


L13 Application of LMS to Noise

Cancelling


L14 Multi-layered Network

Architecture,


L15 Backpropagation Learning

Algorithm,


L16 Practical consideration of BP

algorithm


Module 3: Support Vector Machines and

Radial Basis Function Number of Hours : 08


6. Explain Statistical Learning Theory.

7. Describe the concept of Support Vector Machines.

8. Explain SVM application to Image Classification,

9. Describe Radial Basis Function and Regularization theory

10. Summarize Generalized RBF Networks and RBF application to face recognition.

e. Lesson Plan:

Lecture

No Topics Covered

Teaching

Method

PO’s

Attained

CO’s

Attained

Reference

book/

chapter no

L17 Learning from Examples, Chalk & Board

a, b, e, k

3 T/8

L18 Statistical Learning Theory Chalk & Board 3 T/8

L19 Support Vector Machines Chalk & Board 3 T/8

L20 SVM application to Image

Classification

Chalk & Board 3 T/8

L21 Radial Basis Function

Regularization theory,

Chalk & Board 3 T/8

L22 Generalized RBF Networks, Chalk & Board 3 T/8

L23 Learning in RBFNs, Chalk & Board 3 T/8

L24 RBF application to face

recognition

Chalk & Board 3 T/8





Module 4: Attractor Neural Networks: Number of Hours : 8

b. Learning Objectives:

6. Explain Associative Learning Attractor and Linear Associative memory

7. Describe Hopfield Network and its application.

8. Explain Brain State in a Box neural Network.

9. Summarize the interface between file system and IOCS.

10. Explain Simulated Annealing process and Boltzmann Machine

c. Lesson Plan:

Lecture

No Topics Covered

Teaching

Method

PO’s

Attained

CO’s

Attained

Reference

book/

chapter no

L25 Associative Learning Attractor. Chalk & Board

a, b, e, k

4 T/10

L26 Associative Memory, Linear

Associative memory, Chalk & Board 4 T/10

L27 Hopfield Network, Chalk & Board 4 T/10

L28 application of Hopfield

Network,. Chalk & Board 4 T/10

L29 Brain State in a Box neural

Network, Chalk & Board 4 T/10

L30 Simulated Annealing, Chalk & Board 4 T/10

L31 Boltzmann Machine,

Chalk & Board 4 T/10

L32 Bidirectional Associative

Memory. Chalk & Board 4 T/10

Module 5: Self-organization Feature Map Number of Hours : 8


4. Describe the concepts involved in Maximal Eigenvector Filtering.

5. Explain the concept of extracting Principal Components.

6. Summarize Generalized Learning Laws

7. Explain Self-organization Feature Maps

8. Describe Vector Quantization process

e. Lesson Plan:

Lecture

No Topics Covered

Teaching

Method

PO’s

Attained

CO’s

Attained

Reference

book/

chapter no

L33 Maximal Eigenvector Filtering. Chalk & Board

a, b, e, k

5 T/12

L34 Extracting Principal Components Chalk & Board 5 T/12

L35 Generalized Learning Laws, Chalk & Board 5 T/12

L36 Generalized Learning Laws Chalk & Board 5 T/12

L37 Vector Quantization, Chalk & Board 5 T/12

L38 Self-organization Feature Maps, Chalk & Board 5 T/12

L39 Application of SOM, Chalk & Board 5 T/12

L40 Growing Neural Gas Chalk & Board 5 T/12





5. Portion for I.A Test:

Test Modules COs

I I.A Test Module 1,2 1,2

II I.A Test Module 3,4 3,4

III I.A Test Module 5 5


Assignment - I COs attained

1. Explain artificial neural model and types of activation functions. 1

2. Explain architecture of feed forward and Feedback network. 1

3. Explain i) Convex Sets ii) Convex Hull iii) Linear Separability, 1

4. Describe Error correction and Gradient Descent Rules, 1

5. Explain Perceptron Learning Algorithm and n Convergence Theorem. 1,2

Assignment – II COs attained

6. Explain MSE Error surface and Steepest Descent Search 2

7. Describe Multi-layered Network Architecture. 2

8. Explain Back propagation Learning Algorithm. 2

9. Explain practical applications of BP algorithm 2

10. Explain SVM applications to image classification 3

Assignment – III COs attained

11. Describe generalized RBF network 4

12. Explain Hopified network and it’s apllications 5

13. Describe maximal Eigenvector filtering 5

14. Explain how to extract principal components 5

15. Explain self-organization feature maps 5





DIGITAL SYSTEM DESIGN USING VERILOG

2. Course syllabus





Module-1 Introduction and Methodology Digital Systems and Embedded Systems, Real-World Circuits,

Models, Design Methodology (1.1, 1.3 to 1.5 of Text). Combinational Basics: Combinational

Components and Circuits, Verification of Combinational Circuits. (2.3 and 2.4 of Text)

Sequential Basics: Sequential Datapaths and Control Clocked Synchronous Timing

Methodology (4.3 upto 4.3.1, 4.4 upto 4.4.1 of Text).

Module-2 Memories: Concepts, Memory Types, Error Detection and Correction (Chap 5 of Text).

Module-3 Implementation Fabrics: Integrated Circuits, Programmable Logic Devices, Packaging and

Circuit boards, interconnection and Signal integrity (Chap 6 of Text).

Module-4 I/O interfacing: I/O devices, I/O controllers, Parallel Buses, Serial Transmission, I/O software

(Chap 8 of Text).

Module-5 Design Methodology: Design flow, Design optimization, Design for test, Nontechnical Issues

(Chap 10 of Text).

Question paper pattern: • The question paper will have ten questions.


• There will be 2 full questions (with a maximum of four sub questions) from eachmodule.

• Each full question will have sub questions covering all the topics under amodule.

• The students will have to answer 5 full questions, selecting one full questionfrom each

module.

Text Book:

Peter J. Ashenden, “Digital Design: An Embedded Sytems Approach Using VERILOG”,

Elesvier, 2010.






7) Engineering Knowledge

8) Problem Analysis

9) Design / development of solutions(partly)

10) Investigations

3. Overview of the course: This course highlights the design and implementation of VLSI circuits for complex

digital systems Designs. The focus is on Introduction and Methodology:

Digital Systems and Embedded Systems, Real-World Circuits, Models, Design

Combinational Basics and Sequential Basics: Sequential Datapaths and Control Clocked

Synchronous Timing Methodology.

Issues to be covered Memories: Concepts, Memory Types, Error Detection and Correction

Implementation Fabrics: Integrated Circuits, Programmable Logic Devices, Packaging and

Circuit boards, interconnection and Signal integrity I/O interfacing: I/O devices, I/O

controllers, Parallel Buses, Serial Transmission, I/O software Design Methodology: Design

flow, Design optimization, Design for test, Nontechnical Issues

4. Relevance of the course: As said in course overview, this course gives fair idea about DIGITAL SYSTEM DESIGN

USING VERILOG which is an open elective subject of this program. The course also helps

in understanding ICs design concepts and this is a basic course to VLSI specialization so the

course is very much relevant to this program.

The course discusses about the complexity and design flow. The physical structure of digital

systems & designing,

5. Course outcomes: After studying this course, students will be able to: 8. Explain basics of Digital Systems and Embedded Systems, Real-World Circuits,

Models, Design.

9. Give an insight into Memories: Concepts, Memory Types, Error Detection and

Correction

10. Discuss different Implementation Fabrics: Integrated Circuits, Programmable Logic

Devices, Packaging and Circuit boards, interconnection and Signal integrity.

11. Design of I/O interfacing: I/O devices, I/O controllers, Parallel Buses, Serial

Transmission, I/O software.

12. Design Methodology Design flow, Design optimization, Design for test, Nontechnical

Issues.

13. Applications

1. Communications.

2. Cryptography.


4. Automobiles


6. Robotics.Agriculture…and so on.





14. UNITWISE PLAN

MODULE-1 : Introduction and Methodology Number of Hours : 8



4) Explain the operation of Digital Systems and Embedded Systems, Real-World Circuits,

Models, Design Methodology.

5) Explain the Combinational Basics, Combinational Components and Circuits, Verification of

Combinational Circuits, Sequential Basics.

6) Elaborate the Sequential Data paths and Control Clocked Synchronous Timing

Methodology.

Lesson Plan:

Lecture

No


Method

PO’s

Attained

CO’s

Attained

Reference

book/

chapter no

L1 Digital Systems and Embedded

Systems,

Chalk &

Board

a, b, e, i 1 T1/C1,C2,

C4

L2 Real-World Circuits, Models,

Design Methodology

Chalk &

Board

1 T1/C1,C2,

C4

L3

Combinational Basics,

Combinational Components and

Circuits

Chalk &

Board

1 T1/C1,C2,

C4

L4 Verification of Combinational

Circuits, Sequential Basics.

Chalk &

Board

1 T1/C1,C2,

C4

L5 Verification of Sequential Basics. Chalk &

Board

1 T1/C1,C2,

C4

L6 Sequential Data paths Chalk &

Board

1 T1/C1,C2,

C4

L7 Control Clocked Synchronous Chalk &

Board

1 T1/C1,C2,

C4

L8 Timing Methodology. Chalk &

Board

1 T1/C1,C2,

C4

MODULE 2: Memories Number of Hours : 08



5) Explain the memory concepts.

6) Explain memory types

7) Do Error Detection and Correction





Lesson Plan:

Lecture

No Topics Covered

Teaching

Method

PO’s

Attained

CO’s

Attained

Reference

book/

chapter no

L9 Memory concepts. Chalk & board

a, b, e,

i, k

2 T1/ C5

L10 Memory concepts cntdd.. Chalk & board 2 T1/ C5

L11 Memory types Chalk & board 2 T1/ C5

L12 Memory types contd.. Chalk & board 2 T1/ C5


L14 Error Detection and Correction Chalk & board 2 T1/ C5


L16 Error Detection and Correction

contd..

Chalk & board 2 T1/ C5

Module 3: Implementation Fabrics Number of Hours : 08


4) Explain interconnection and Signal integrity

5) Explain Programmable Logic Devices, Packaging and Circuit boards

6) Design Integrated Circuits

Lesson Plan:

Lecture

No Topics Covered

Teaching

Method

PO’s

Attained

CO’s

Attained

Reference

book/

chapter no

L17 Integrated Circuits Chalk & board a, b, d, e,

i, k

3 T1/C6

L18 Programmable Logic Devices Chalk & board 3 T1/C6

L19 Programmable Logic Devices contd.. Chalk & board 3 T1/C6

L20 Packaging and Circuit boards Chalk & board 3 T1/C6

L21 Packaging and Circuit boards contdd Chalk & board 3 T1/C6

L22 Packaging and Circuit boards contdd Chalk & board 3 T1/C6

L23 interconnection and Signal integrity Chalk & board 3 T1/C6

L24 interconnection and Signal integrity

contd…

Chalk & board 3 T1/C6

Module 4: I/O interfacing Number of Hours : 08


1) Explain I/O devices.

2) Distinguish I/O controllers.

3) Design Parallel Buses.

4) Explain the Serial Transmission

5) Design I/O software.





Lesson Plan:

Lecture

No Topics Covered

Teaching

Method

PO’s

Attained

CO’s

Attained

Reference

book/

chapter no

L25 I/O devices Chalk & board a, b, d, e,

i,

4 T1/C8

L26 I/O controllers Chalk & board 4 T1/C8

L27 Parallel Buses Chalk & board 4 T1/C8


L29 Serial Transmission Chalk & board 4 T1/C8


L31 I/O software Chalk & board 4 T1/C8


Module 5: Design Methodology Number of Hours : 08



5. Explain Design flow

6. Understand Design optimization.

7. Explain Design for test

8. Know Nontechnical Issues

Lesson Plan:

Lecture

No Topics Covered

Teaching

Method

PO’s

Attained

CO’s

Attained

Reference

book/

chapter no

L33 Design flow Chalk & board a, b, d, e,

i,

5 T1/C10

L34 Design flow Chalk & board 5 T1/C10

L35 Design optimization Chalk & board 5 T1/C10


L37 Design for test Chalk & board 5 T1/C10


L39 Nontechnical Issues Chalk & board 5 T1/C10






Third IA test Module 5 5





9. Assignment questions


6. Explain Digital Systems and Embedded Systems.

7. Explain the Real-World Circuits, Models, Design Methodology.

8. Elaborate the Combinational Basics Combinational Components and Circuits,

Verification of Combinational Circuits and Sequential Basics.

9. Explain Memories Concepts and Memory Types.

10. With an example explain Error Detection and Correction.

2nd

Assignment questions: 6. Explain Integrated Circuits.

7. What are Programmable Logic Devices.

8. Explain Packaging and Circuit boards, interconnection and Signal integrity.

9. Explain I/O interfacing: I/O devices, and I/O controllers.

10. Explain Parallel Buses, Serial Transmission, and I/O software.

3rd

Assignment questions: 6. Discuss the Design optimization.

7. Explain Design for test.

8. Explain Nontechnical Issues.

9. Explain the Design flow.

10. List of PO’s: a: An ability to apply knowledge of mathematics, science, and engineering.















engineering practice





DIGITAL SYSTEM DESIGN USING VERILOG 3. Course syllabus





Module-1

Introduction and Methodology Digital Systems and Embedded Systems, Real-World Circuits,

Models, Design Methodology (1.1, 1.3 to 1.5 of Text). Combinational Basics: Combinational

Components and Circuits, Verification of Combinational Circuits. (2.3 and 2.4 of Text)

Sequential Basics: Sequential Datapaths and Control Clocked Synchronous Timing

Methodology (4.3 upto 4.3.1, 4.4 upto 4.4.1 of Text).

Module-2

Memories: Concepts, Memory Types, Error Detection and Correction (Chap 5 of Text).

Module-3

Implementation Fabrics: Integrated Circuits, Programmable Logic Devices, Packaging and

Circuit boards, interconnection and Signal integrity (Chap 6 of Text).

Module-4

I/O interfacing: I/O devices, I/O controllers, Parallel Buses, Serial Transmission, I/O software

(Chap 8 of Text).

Module-5 Design Methodology: Design flow, Design optimization, Design for test, Nontechnical Issues

(Chap 10 of Text).

Question paper pattern: • The question paper will have ten questions.


• There will be 2 full questions (with a maximum of four sub questions) from eachmodule.

• Each full question will have sub questions covering all the topics under amodule.

• The students will have to answer 5 full questions, selecting one full questionfrom each module.

Text Book: Peter J. Ashenden, “Digital Design: An Embedded Sytems Approach Using VERILOG”,

Elesvier, 2010.


11) Engineering Knowledge

12) Problem Analysis

13) Design / development of solutions(partly)

14) Investigations





3. Overview of the course: This course highlights the design and implementation of VLSI circuits for complex

digital systems Designs. The focus is on Introduction and Methodology:

Digital Systems and Embedded Systems, Real-World Circuits, Models, Design

Combinational Basics and Sequential Basics: Sequential Datapaths and Control Clocked

Synchronous Timing Methodology.

Issues to be covered Memories: Concepts, Memory Types, Error Detection and

Correction Implementation Fabrics: Integrated Circuits, Programmable Logic Devices,

Packaging and Circuit boards, interconnection and Signal integrity I/O interfacing: I/O

devices, I/O controllers, Parallel Buses, Serial Transmission, I/O software Design

Methodology: Design flow, Design optimization, Design for test, Nontechnical Issues

4. Relevance of the course: As said in course overview, this course gives fair idea about DIGITAL SYSTEM

DESIGN USING VERILOG which is an open elective subject of this program. The course

also helps in understanding ICs design concepts and this is a basic course to VLSI

specialization so the course is very much relevant to this program.

The course discusses about the complexity and design flow. The physical structure of

digital systems & designing,

5. Course outcomes: After studying this course, students will be able to:

15. Explain basics of Digital Systems and Embedded Systems, Real-World Circuits,

Models, Design.

16. Give an insight into Memories: Concepts, Memory Types, Error Detection and

Correction

17. Discuss different Implementation Fabrics: Integrated Circuits, Programmable Logic

Devices, Packaging and Circuit boards, interconnection and Signal integrity.

18. Design of I/O interfacing: I/O devices, I/O controllers, Parallel Buses, Serial

Transmission, I/O software.

19. Design Methodology Design flow, Design optimization, Design for test,

Nontechnical Issues.

20. Applications

1. Communications.

2. Cryptography.


4. Automobiles


6. Robotics.Agriculture…and so on.





UNITWISE PLAN

MODULE-1 : Introduction and Methodology Number of Hours : 8


7) Explain the operation of Digital Systems and Embedded Systems, Real-World Circuits,

Models, Design Methodology.

8) Explain the Combinational Basics, Combinational Components and Circuits, Verification of

Combinational Circuits, Sequential Basics.

9) Elaborate the Sequential Data paths and Control Clocked Synchronous Timing Methodology.

Lesson Plan:

Lecture

No


Method

PO’s

Attained

CO’s

Attained

Reference

book/

chapter no

L1 Digital Systems and Embedded

Systems,

Chalk & Board a, b, e, i 1 T1/C1,C2,C4

L2 Real-World Circuits, Models, Design

Methodology

Chalk & Board 1 T1/C1,C2,C4

L3 Combinational Basics, Combinational

Components and Circuits


L4 Verification of Combinational Circuits,

Sequential Basics.


L5 Verification of Sequential Basics. Chalk & Board 1 T1/C1,C2,C4

L6 Sequential Data paths Chalk & Board 1 T1/C1,C2,C4

L7 Control Clocked Synchronous Chalk & Board 1 T1/C1,C2,C4

L8 Timing Methodology. Chalk & Board 1 T1/C1,C2,C4

MODULE 2: Memories Number of Hours : 08


8) Explain the memory concepts.

9) Explain memory types

10) Do Error Detection and Correction

Lesson Plan:

Lecture

No Topics Covered

Teaching

Method

PO’s

Attained

CO’s

Attained

Reference

book/

chapter no

L9 Memory concepts. Chalk & board

a, b, e, i,

k

2 T1/ C5

L10 Memory concepts cntdd.. Chalk & board 2 T1/ C5

L11 Memory types Chalk & board 2 T1/ C5







L14 Error Detection and Correction Chalk & board

2 T1/ C5


L16 Error Detection and Correction

contd..

Chalk & board 2 T1/ C5

Module 3: Implementation Fabrics Number of Hours : 08


7) Explain interconnection and Signal integrity

8) Explain Programmable Logic Devices, Packaging and Circuit boards

9) Design Integrated Circuits

Lesson Plan:

Lecture No Topics Covered Teaching

Method

PO’s

Attained

CO’s

Attained

Reference

book/

chapter no

L17 Integrated Circuits Chalk & board a, b, d, e,

i, k

3 T1/C6

L18 Programmable Logic Devices Chalk & board 3 T1/C6

L19 Programmable Logic Devices

contd..


L20 Packaging and Circuit boards Chalk & board 3 T1/C6

L21 Packaging and Circuit boards

contdd


L22 Packaging and Circuit boards

contdd


L23 interconnection and Signal

integrity


L24 interconnection and Signal

integrity contd…


Module 4: I/O interfacing Number of Hours : 08


1) Explain I/O devices.

2) Distinguish I/O controllers.

3) Design Parallel Buses.

4) Explain the Serial Transmission

5) Design I/O software.





Lesson Plan:

Lecture

No Topics Covered

Teaching

Method

PO’s

Attained

CO’s

Attained

Reference

book/

chapter no

L25 I/O devices Chalk & board a, b, d, e,

i,

4 T1/C8

L26 I/O controllers Chalk & board 4 T1/C8







Module 5: Design Methodology Number of Hours : 08


9. Explain Design flow

10. Understand Design optimization.

11. Explain Design for test

12. Know Nontechnical Issues

Lesson Plan:

Lecture

No Topics Covered

Teaching

Method

PO’s

Attained

CO’s

Attained

Reference

book/

chapter no

L33 Design flow Chalk & board a, b, d, e,

i,

5 T1/C10

L34 Design flow Chalk & board 5 T1/C10











Third IA test Module 5 5





9. Assignment questions


11. Explain Digital Systems and Embedded Systems.

12. Explain the Real-World Circuits, Models, Design Methodology.

13. Elaborate the Combinational Basics Combinational Components and Circuits,

Verification of Combinational Circuits and Sequential Basics.

14. Explain Memories Concepts and Memory Types.

15. With an example explain Error Detection and Correction.

2nd

Assignment questions:

11. Explain Integrated Circuits.

12. What are Programmable Logic Devices.

13. Explain Packaging and Circuit boards, interconnection and Signal integrity.

14. Explain I/O interfacing: I/O devices, and I/O controllers.

15. Explain Parallel Buses, Serial Transmission, and I/O software.

3rd

Assignment questions:

10. Discuss the Design optimization.

11. Explain Design for test.

12. Explain Nontechnical Issues.

13. Explain the Design flow.

11. List of PO’s:

a: An ability to apply knowledge of mathematics, science, and engineering.















engineering practice





Embedded Controller Lab

Semester: VI Exam Marks : 80

Subject Code:15ECL67 IA Marks : 20

No. of Practical Hrs/Week: 03 Exam Hours : 03

Expt.

no

Name of Experiment Week

1 ALP to multiply two 16 bit binary numbers. I

2 ALP to find the sum of first 10 integer numbers. II

3 Display “Hello World” message using Internal UART. III

4 Interface and Control a DC Motor. IV

5 Interface a Stepper motor and rotate it in clockwise and anti-clockwise

Direction.

V

6 Determine Digital output for a given Analog input using Internal

Controller.

VI

7 Interface a DAC and generate Triangular and Square waveforms. VII

8 Interface a 4x4 keyboard and display the key code on an LCD. VIII 9 Using the Internal PWM module of ARM controller generate PWM and

vary its duty cycle.

IX

10 Demonstrate the use of an external interrupt to toggle an LED On/Off. X

11 Display the Hex digits 0 to F on a 7-segment LED interface, with an

appropriate delay in between.

XI

12 Interface a simple Switch and display its status through Relay, Buzzer and

LED.

XII

13 Measure Ambient temperature using a sensor and SPI ADC IC. XIII

Sl.No. Particulars Marks

1 Laboratory Journal 10

2 I. A. Test 05

3 Viva-voce 05

Course Outcomes (CO)

After studying this course the student will be able to

1. Perform arithmetic and logical operation.

2. Interface simple switch, DAC , stepper motor and control DC motor.

3. Display keycode, Hex segments on LCDand switch status on LED.

4. Perform pulse width modulation.

5. Measure the temperature using sensor.





COMPUTER NETWORKS LABORATORY

SEMESTER –VI

Laboratory Code 15ECL68

Number of Lecture

Hours/Week

01Hr Tutorial (Instructions)+

02 Hours Laboratory = 03 Hrs.

Exam Marks 80

Exam Hours 03

IA Marks 20

CREDITS – 02

Course objectives: This laboratory course will enable students to:

1. Choose suitable tools to model a network and understand the protocols at various OSI

reference levels.

2. Design a suitable network and simulate using a Network simulator tool.

3. Simulate the networking concepts and protocols using C/C++ programming.

4. Model the networks for different configurations and analyze the results.

Laboratory Experiments

PART-A: Simulation experiments using NS2/NS3/OPNET/ NCTUNS/NetSim/QualNet/

Packet Tracer or any other equivalent tool

1. Implement a point to pint network with four nodes and duplex links between them.

Analyze the network performance by setting the queue size and varying the

bandwidth.

2. Implement a four-node point to point network with links n0-n2, n1-n2 and n2-n3.

Apply TCP agent between n0-n3 and UDP between n1-n3. Apply relevant

applications over TCP and UDP agents changing the parameter and determine the

number of packets sent by TCP/UDP.

3. Implement Ethernet LAN using n (6-10) nodes. Compare the throughput by changing

the error rate and data rate.

4. Implement Ethernet LAN using n nodes and assign multiple traffic to the nodes and

obtain congestion window for different sources/ destinations.

5. Implement ESS with transmission nodes in Wireless LAN and obtain the performance

parameters.

6. Implementation of Link state routing algorithm.





PART-B: Implement the following in C/C++

1. Write a program for a HLDC frame to perform the following.

i) Bit stuffing

ii) Character stuffing.

2. Write a program for distance vector algorithm to find suitable path fortransmission.

3. Implement Dijkstra’s algorithm to compute the shortest routing path.

4. For the given data, use CRC-CCITT polynomial to obtain CRC code. Verify

theprogram for the cases

a. Without error

b. With error

5. Implementation of Stop and Wait Protocol and Sliding Window Protocol

6. Write a program for congestion control using leaky bucket algorithm.

Course Outcomes: On the completion of this laboratory course, the students will beable to:

1. Design and Simulate Network elements with various protocols and standards.

2. Use the network simulator tools for learning and practice of networking algorithms.

3. Demonstrate the working of various protocols and algorithms using C programming.

Graduate Attributes (as per NBA)

• Engineering Knowledge.

• Problem Analysis.

• Design/Development of solutions.

Documents

B.L.D.E. Association’s V.P. Dr. P. G. Halakatti …bldeacet.ac.in/PDF/CourseFile/EC/EC_6th_CBCS_2017-18.pdfBandpass Signal to Equivalent lowpass Signal : Hilbert Transform, Pre-envelopes,