55:131 Introduction to VLSI Design

Flash and DRAM Adapted from Weste and Harris notes except as noted

Flash and DRAM sections adapted from “Digital Integrated Circuits”, copyright 2003 Prentice Hall/

Pearson

Outline   Memory Arrays   Flash   DRAM

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Memory Arrays

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Array Architecture   2n words of 2m bits each   If n >> m, fold by 2k into fewer rows of more columns

  Good regularity – easy to design   Very high density if good cells are used

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Non-Volatile Memories   Floating-gate transistor

Floating gate

Source

Substrate

Gate Drain

n + n +_ p

t ox t ox

Device cross-section Schematic symbol

G

S

D

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Floating-Gate Transistor Programming

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FN Tunneling FN Tunneling Remove e- Add e- Negative Vt Positive Vt “1” “0”

NAND Flash Memory

Unit Cell

Word line(poly)

Source line

(Diff. Layer)

Courtesy Toshiba 7 55:131 Introduction to VLSI Design

NAND Flash Memory Word lines Select transistor

Bit line contact Source line contact

Active area

STI

Courtesy Toshiba 8 55:131 Introduction to VLSI Design

Read-Write Memories (RAM)   Static (SRAM)

  Data stored as long as supply is applied   Large (6 transistors/cell)   Fast   Differential

  Dynamic (DRAM)   Periodic refresh required   Small (1-3 transistors/cell)   Slower   Single Ended

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3-Transistor DRAM Cell   No constraints on device ratios   Reads are non-destructive   Value stored at node X when writing a “1” = Vwwl-Vtn

WWL BL 1

M 1 X

M 3

M 2 C S

BL 2

RWL

V DD V DD V T

Δ V V DD - V T BL 2

BL 1

X

RWL

WWL

-

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3T-DRAM — Layout

BL2 BL1 GND

RWL

WWL

M3

M2

M1

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1-Transistor DRAM Cell   Write: Cs is charged or discharged by asserting WL

and BL   Read: Charge redistribution takes place between bit

line and storage capacitance   Voltage swing is small; typically around 250 mV

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DRAM Cell Observations   1T DRAM requires a sense amplifier for each bit line, due to

charge redistribution read-out.   DRAM memory cells are single ended in contrast to SRAM

cells.   The read-out of the 1T DRAM cell is destructive; read and

refresh operations are necessary for correct operation.   Unlike 3T cell, 1T cell requires presence of an extra

capacitance that must be explicitly included in the design.   When writing a “1” into a DRAM cell, a threshold voltage is

lost. This charge loss can be circumvented by bootstrapping the word lines to a higher value than VDD

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Sense Amp Operation

Δ V (1)

V (1)

V (0) t

V PRE

V BL

Sense amp activated Word line activated

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1-T DRAM Cell

Uses Polysilicon-Diffusion Capacitance Expensive in Area

M 1 word line

Diffused bit line

Polysilicon gate

Polysilicon plate

Capacitor

Cross-section Layout

Metal word line

Poly

SiO 2

Field Oxide n + n + Inversion layer induced by plate bias

Poly

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Advanced 1T DRAM Cells

Cell Plate Si

Capacitor Insulator

Storage Node Poly

2nd Field Oxide

Refilling Poly

Si Substrate

Trench Cell Stacked-capacitor Cell

Capacitor dielectric layer Cell plate Word line Insulating Layer

Isolation Transfer gate Storage electrode

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DRAM Timing

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Redundancy

Memory Array

Column Decoder

Row Decoder

Redundant rows

Redundant columns

Row Address

Column Address

Fuse Bank :

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