4.8 kHz, Ultralow Noise, 24-Bit Sigma-Delta ADC with PGA ...?4.8 kHz, Ultralow Noise, 24-Bit Sigma-Delta ADC with PGA AD7192 Rev. A Information furnished by Analog Devices is believed

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  • 4.8 kHz, Ultralow Noise, 24-Bit Sigma-Delta ADC with PGA

    AD7192

    Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

    One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 2009 Analog Devices, Inc. All rights reserved.

    FEATURES RMS noise: 11 nV @ 4.7 Hz (gain = 128) 15.5 noise-free bits @ 2.4 kHz (gain = 128) Up to 22 noise-free bits (gain = 1) Offset drift: 5 nV/C Gain drift: 1 ppm/C Specified drift over time 2 differential/4 pseudo differential input channels Automatic channel sequencer Programmable gain (1 to 128) Output data rate: 4.7 Hz to 4.8 kHz Internal or external clock Simultaneous 50 Hz/60 Hz rejection 4 general-purpose digital outputs Power supply

    AVDD: 3 V to 5.25 V DVDD: 2.7 V to 5.25 V

    Current: 4.35 mA Temperature range: 40C to +105C Package: 24-lead TSSOP

    INTERFACE 3-wire serial SPI, QSPI, MICROWIRE, and DSP compatible Schmitt trigger on SCLK

    APPLICATIONS Weigh scales Strain gage transducers Pressure measurement

    Temperature measurement Chromatography PLC/DCS analog input modules Data acquisition Medical and scientific instrumentation

    GENERAL DESCRIPTION The AD7192 is a low noise, complete analog front end for high precision measurement applications. It contains a low noise, 24-bit sigma-delta (-) analog-to-digital converter (ADC). The on-chip low noise gain stage means that signals of small amplitude can be interfaced directly to the ADC.

    The device can be configured to have two differential inputs or four pseudo differential inputs. The on-chip channel sequencer allows several channels to be enabled, and the AD7192 sequentially converts on each enabled channel. This simplifies communication with the part. The on-chip 4.92 MHz clock can be used as the clock source to the ADC or, alternatively, an external clock or crystal can be used. The output data rate from the part can be varied from 4.7 Hz to 4.8 kHz.

    The device has two digital filter options. The choice of filter affects the rms noise/noise-free resolution at the programmed output data rate, the settling time, and the 50 Hz/60 Hz rejection. For applications that require all conversions to be settled, the AD7192 includes a zero latency feature.

    The part operates with a power supply from 3 V to 5.25 V. It consumes a current of 4.35 mA. It is housed in a 24-lead TSSOP package.

    FUNCTIONAL BLOCK DIAGRAM

    MCLK1 MCLK2 P0/REFIN2() P1/REFIN2(+)

    DVDD DGND REFIN1(+) REFIN1()

    AIN1AIN2AIN3AIN4

    AINCOM

    BPDSW

    AGND

    AD7192REFERENCE

    DETECT

    SERIALINTERFACE

    ANDCONTROL

    LOGIC

    TEMPSENSOR

    CLOCKCIRCUITRY

    AVDD

    AGND

    DOUT/RDY

    DIN

    SCLKCS

    SYNC

    P3P2

    AVDDAGND

    -ADCPGA

    MUX

    0782

    2-00

    1

    Figure 1.

  • AD7192

    Rev. A | Page 2 of 40

    TABLE OF CONTENTS Features .............................................................................................. 1 Interface ............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Timing Characteristics ..................................................................... 7

    Circuit and Timing Diagrams ..................................................... 7 Absolute Maximum Ratings ............................................................ 9

    Thermal Resistance ...................................................................... 9 ESD Caution .................................................................................. 9

    Pin Configuration and Function Descriptions ........................... 10 Typical Performance Characteristics ........................................... 12 RMS Noise and Resolution ............................................................ 14

    Sinc4 Chop Disabled ................................................................... 14 Sinc3 Chop Disabled ................................................................... 15 Sinc4 Chop Enabled .................................................................... 16 Sinc3 Chop Enabled .................................................................... 17

    On-Chip Registers .......................................................................... 18 Communications Register ......................................................... 18 Status Register ............................................................................. 19 Mode Register ............................................................................. 19 Configuration Register .............................................................. 21 Data Register ............................................................................... 23 ID Register ................................................................................... 23 GPOCON Register ..................................................................... 24

    Offset Register ............................................................................ 24 Full-Scale Register ...................................................................... 24

    ADC Circuit Information .............................................................. 25 Overview ..................................................................................... 25 Filter, Output Data Rate, and Settling Time ........................... 25 Digital Interface .......................................................................... 28

    Circuit Description......................................................................... 32 Analog Input Channel ............................................................... 32 Programmable Gain Array (PGA) ........................................... 32 Bipolar/Unipolar Configuration .............................................. 32 Data Output Coding .................................................................. 32 Clock ............................................................................................ 32 Burnout Currents ....................................................................... 33 Reference ..................................................................................... 33 Reference Detect ......................................................................... 33 Reset ............................................................................................. 34 System Synchronization ............................................................ 34 Temperature Sensor ................................................................... 34 Bridge Power-Down Switch ...................................................... 34 Logic Outputs ............................................................................. 34 Enable Parity ............................................................................... 35 Calibration ................................................................................... 35 Grounding and Layout .............................................................. 36

    Applications Information .............................................................. 37 Weigh Scales ................................................................................ 37

    Outline Dimensions ....................................................................... 38 Ordering Guide .......................................................................... 38

    REVISION HISTORY 5/09Rev. 0 to Rev. A

    Change to Gain Error Specification ............................................... 3 Changes to Table 3 ............................................................................ 9

    5/09Revision 0: Initial Version

  • AD7192

    Rev. A | Page 3 of 40

    SPECIFICATIONS AVDD = 3 V to 5.25 V, DVDD = 2.7 V to 5.25 V, AGND = DGND = 0 V; REFINx(+) = AVDD, REFINx() = AGND, MCLK = 4.92 MHz, TA = TMIN to TMAX, unless otherwise noted.

    Table 1. Parameter AD7192B Unit Test Conditions/Comments1 ADC

    Output Data Rate 4.7 to 4800 Hz nom Chop disabled 1.17 to 1200 Hz nom Chop enabled, sinc4 filter 1.56 to 1600 Hz nom Chop enabled, sinc3 filter No Missing Codes2 24 Bits min FS > 1, sinc4 filter3 24 Bits min FS > 4, sinc3 filter3 Resolution See the RMS Noise and Resolution section RMS Noise and Output Data Rates See the RMS Noise and Resolution section Integral Nonlinearity

    Gain = 12 10 ppm of FSR max 2 ppm typical, AVDD = 5 V 15 ppm of FSR max 2 ppm typical, AVDD = 3 V Gain > 1 30 ppm of FSR max 5 ppm typical, AVDD = 5 V

    30 ppm of FSR max 12 ppm typical, AVDD = 3 V Offset Error4, 5 150/gain V typ Chop disabled 0.5 V typ Chop enabled Offset Error Drift vs. Temperature 150/gain nV/C typ Gain = 1 to 16; chop disabled 5 nV/C typ Gain = 32 to 128; chop disabled 5 nV/C typ Chop enabled Offset Error Drift vs. Time 25 nV/1000 hours typ Gain > 32 G