Digital Integrated Circuits 2nd Manufacturing Digital IntegratedCircuits Manufacturing Process

EE141 © Digital Integrated Circuits2nd Manufacturing

Digital IntegratedCircuits

Manufacturing Process


CMOS Process

Complementary metal–oxide–semiconductor (CMOS)


photoresist


photoresist

light

develop

positive

light

develop

negative

mask opaque


Patterning of SiO2

Si-substrate

Si-substrate Si-substrate

(a) Silicon base material

(b) After oxidation and deposition of negative photoresist

(c) Stepper exposure

Photoresist

SiO 2

UV-light

Patterned optical mask

Exposed resist

Si-substrate

Si-substrate

Si-substrate

SiO 2

SiO 2

(d) After development and etching of resist, chemical or plasma etch of SiO

2

(e) After etching

(f) Final result after removal of resist

Remove possible residue

Hardened resist

Chemical or plasma etch


CMOS Process


CMOS Process


CMOS Process


CMOS Process

Key feature of

CMOS process


Circuit Under Design VDD VDD

VinVout

M1

M2

M3

M4

Vout2

metal

Active region

N-select Poly silicon

N-well

N-select


Its Layout View VDD VDD

VinVout

M1

M2

M3

M4

Vout2

2

1

In

V DD

GND

Stick diagram of inverter

2

1

In Out


Design Rules


3D Perspective

Polysilicon Aluminum


Design Rules

Interface between designer and process

engineer

Guidelines for constructing process masks

Unit dimension: Minimum line width

scalable design rules: lambda parameter

absolute dimensions (micron rules)


CMOS Process Layers

Layer

Polysilicon

Metal1

Metal2

Contact To Poly

Contact To Diffusion

Via

Well (p,n)

Active Area (n+,p+)

Color Representation

Yellow

Green

Red

Blue

Magenta

Black

Black

Black

Select (p+,n+) Green


Intra-Layer Design Rules


Intra-Layer Design Rules

Metal2 4

3

10

90

Well

Active3

3

Polysilicon

2

2

Different PotentialSame Potential

Metal13

3

2

Contactor Via

Select

2

or6

2Hole

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Digital Integrated Circuits 2nd Manufacturing Digital IntegratedCircuits Manufacturing Process